JPH0130412B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a capacitive conversion device that converts a physical quantity (eg, displacement) into an electrical signal.

A capacitive conversion device converts a change in a physical quantity into a change in capacitance, and further converts this change in capacitance into an electrical signal, and is widely used in the field of industrial measurement and the like.

FIG. 1 is a circuit diagram showing an example of a conventional capacitive conversion device of this type, and in this figure, reference numeral 1 indicates a sensor that detects a change in a physical quantity. This sensor 1 is constructed by disposing a movable electrode 1c between fixed electrodes 1a and 1b, which moves according to changes in physical quantities.When the movable electrode 1c moves, the capacitance C between the electrodes 1a and 1c ₁ and electrode 1b,1
The capacitances C ₂ between the capacitances C and C change in a complementary manner. 2a and 2b are switches that operate in conjunction with each other, and are turned on alternately in accordance with the Qn output of the counter 3. 4 and 5 are both inverting amplifiers, and these inverting amplifiers 4,
5 and the capacitances C ₁ and C ₂ of the sensor 1 constitute an oscillation circuit 9. The counter 3 is an n-bit binary counter that counts the output of the oscillation circuit 9, and its Qn output is averaged by the smoothing circuit 6, amplified by the amplifier 7, and output from the output terminal 8. .

In the above configuration, when the Qn output of the counter 3 is at the "H" (high) level (referred to as the first state), the switch 2a is in the on state, and the switch 2b is in the on state.
is in the off state, and when the Qn output of the counter 3 is at the "L" (low) level (referred to as the second state), the switch 2a is in the off state, and the switch 2a is in the off state.
b is turned on. As a result, in the first state, the oscillation circuit 9 oscillates using the capacitance C ₁ as the oscillation element, and in the second state, the oscillation circuit 9 oscillates using the capacitance C ₂ as the oscillation element.
As a result, the Qn output of counter 3 is the capacitance
The signal has a duty ratio corresponding to C ₁ and C ₂ , in other words, a duty ratio corresponding to the physical quantity applied to the movable electrode 1c. Therefore, this signal is averaged by the smoothing circuit 6 and sent to the amplifier 7. By amplifying the signal, an electrical signal corresponding to the physical quantity can be obtained from the output terminal 8.

By the way, it is not limited to the above-mentioned capacitive conversion device.
A problem with this type of converter is that errors occur in measured values due to stray capacitance such as capacitance between each electrode of the sensor and the sensor housing or capacitance between wiring. Among these stray capacitances, the stray capacitance Cs shown in FIG. 1 is particularly problematic, and the stray capacitance generated at this position causes a decrease in measurement accuracy and instability of characteristics.

In view of the above-mentioned circumstances, the present invention provides a capacitive conversion device that is not affected by stray capacitance. an oscillation circuit in which the electrostatic capacitance of is used as an element that alternately determines the oscillation frequency; a counter that counts the output of the oscillation circuit; and the first and second capacitances corresponding to the output of the counter. It comprises a switching means for switching, a smoothing means for smoothing the output of the counter, and an amplification means for amplifying the output of the smoothing means and transmitting a device output, and the output of the smoothing means is equal to the output of the first and second counters. At least one of the voltages applied to the first and second capacitances is controlled by the output of the amplification means so as to always maintain a constant value regardless of the value of the capacitance. It is.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing the configuration of the first embodiment of the present invention, and in this figure, reference numeral 11 is a sensor for detecting a physical quantity. This sensor 11
A movable electrode 11a that moves according to changes in physical quantities, a fixed electrode 11b, and these movable electrodes 1
1a, and a fixed electrode 11c disposed between the fixed electrode 11b and the fixed electrode 11b. That is, in this sensor 11, the capacitance C ₄ between the fixed electrodes 11b and 11c is always constant, and only the capacitance C ₃ between the movable electrode 11a and the fixed electrode 11c changes as the physical quantity changes. ing. The fixed electrode 11c is connected to the input end of the inverting amplifier 12, the movable electrode 11a is connected to the output end of the NAND gate 13, and the fixed electrode 11b is connected to the output end of the NAND gate 14.

Furthermore, a resistor 1 is connected between the input and output terminals of the inverting amplifier 12.
5 is inserted, and the output terminal of the inverting amplifier 12 is connected to one input terminal of each of the NAND gates 13 and 14 and to the clock terminal CL of the flip-flop 16. The output terminal Q of the flip-flop 16 is connected to the other input terminal of the NAND gate 13, and the output terminal is connected to the other input terminal of the NAND gate 14 and the input terminal D of the flip-flop 16. The output terminal of the integrating circuit 17 is connected.

In the above configuration, the sensor 11, the NAND gates 13 and 14, the inverting amplifier 12, and the resistor 15 constitute the oscillation circuit 18. This oscillation circuit 18
is basically the same as the oscillation circuit 9 shown in FIG. 1, except that the switches 2a, 2b and inverting amplifier 5 in FIG. 1 are replaced with NAND gates 13, 14, and the configuration of the sensor 11 is different. It's on. Further, this oscillation circuit 18 is particularly characterized in that the output of the integrating circuit 17 is supplied to the positive power supply terminal of the NAND gate 13. Furthermore, the flip-flop 16 is merely a 1-bit flip-flop as the counter 3 shown in FIG. 1, and there is no change in characteristics even if an n-bit counter is used instead of the flip-flop 16.

Therefore, the output terminal Q of the flip-flop 16
The signal obtained from the resistor 20 and capacitor 21
The integrating circuit 1
7. The integrating circuit 17 is connected to the amplifier 24
, a resistor 25 inserted between the inverting input terminal of the amplifier 24 and the output terminal of the integrating circuit 22, a capacitor 26 inserted between the inverting input terminal and the output terminal of the amplifier 24, and a non-inverting terminal of the amplifier 24. It is composed of resistors 27 and 28 that supply a bias voltage of voltage E/2 (E is the power supply voltage) to the input terminal,
The output of the amplifier 24 is supplied to an output terminal 29 and also to the positive power supply terminal of the NAND gate 13 described above.

Next, the operation of the capacitive converter having the above configuration will be explained while taking into account the stray capacitance Cs existing between the input terminal of the inverting amplifier 12 and the ground.

First, assuming that the power supply voltage +E (constant) is supplied to the positive power supply terminal of the NAND gate 13,
The operations of oscillation circuit 18 and flip-flop 16 will be explained. Note that the operation of the oscillation circuit 18 in this case is exactly the same as the operation of the oscillation circuit 9 shown in FIG.

First, the oscillation circuit 18 includes a flip-flop 16
When the output terminal Q of is at “H” level, the NAND gate 13 is open, so the capacitance
oscillates at a frequency determined by C ₃ , and
When the output terminal Q of the flip-flop 16 is in the "L" level, the NAND gate 14 is in an open state, so that it oscillates at a frequency determined by the capacitance _C4 . Further, the output of the flip-flop 16 is inverted every cycle of the output of the oscillation circuit 18. That is _, the output signal S _{1 of} the oscillation circuit 18 and the Q output signal S ₂ of the flip _- flop ₁₆ are calculated as They are shown in Figure 3 A and B, respectively. Also, Nand Gate 13
are the signals S ₁ and S ₂ , and the NAND gate 14 is the signal S ₁
and the NAND of the inverted signal of the signal _S2 , the output signals _S3 and _S4 of these NAND gates 13 and 14 are as shown in FIGS. 3C and 3D, respectively. Since these signals S ₃ and S ₄ are supplied to the movable electrode 11a and the fixed electrode 11b of the sensor 11, respectively, the signal obtained at the fixed electrode 11c of the sensor 11, that is, the input signal S ₅ of the inverting amplifier 12 is shown in Figure 3 (E). In this case, the threshold level of the inverting amplifier 12 is set to E/2.

Here, assuming that the output impedance of the NAND gates 13 and 14 is extremely small, the coupling from the output terminal of the NAND gate 13 to the input terminal of the inverting amplifier 12 is equivalently as shown in FIG.
The coupling from the output terminal of the NAND gate 14 to the input terminal of the inverting amplifier 12 is shown in _FIG .
C ₄ is replaced with each other. As a result, the signal in period _T1 when signal _S2 is at "H" level
The peak value e ₁ of S ₅ is the “H” level voltage of signal S ₃ e ₂
Then, e ₁ = C ₃ / C ₃ + C ₄ + Cs・e ₂ ...(2) and the period during which the signal S ₂ is at "L" level.
The peak value e′ ₁ of the signal S ₅ at T ₂ is “H” of the signal S ₄
If the level voltage is e ₃ , then e' ₁ = C ₄ /C ₃ + C ₄ + Cs・e ₂ ...(3). Note that the voltage e ₂ mentioned above is the NAND gate 1
When +E is applied to the positive power supply terminal of NAND gate 13, e ₂ = +E ...(4) However, when the output voltage V of the integrating circuit 17 is applied to the positive power supply terminal of NAND gate 13, e ₂ = V...(5). In this case, the above equation (2) becomes e ₂ =C ₃ /C ₃ +C ₄ +Cs·V (6). Further, the voltage e ₃ is always e ₃ =+E (7).

Next, the operation of the circuit shown in FIG. 2 when the output voltage V of the integrating circuit 17 is applied to the positive power supply terminal of the NAND gate 13 will be described.

In the circuit shown in FIG. 2, the output of the integrating circuit 17 is supplied to the positive power supply terminal of the NAND gate 13, thereby forming a feedback loop of the amplifier 24, so that the output voltage Va of the smoothing circuit 22 is always Regardless of the values of the capacitances C ₃ and C ₄ ), the voltage E/2 supplied to the non-inverting input terminal of the amplifier 24 is maintained. This means that the duty ratio of the output signal _S2 of the flip-flop 16 is always 1:
1, and also means that the periods T ₁ and T ₂ shown in FIG. 3B are always held as T ₁ =T ₂ (8).

That is, for example, if the capacitance _C3 increases at time _t1 shown in FIG. 5A, the "H" level period of the signal _S2 temporarily increases as shown in FIG.
_T1 becomes longer than the "L" level period _T2 , and as a result, the output voltage Va of the integrating circuit 22 gradually increases from the voltage E/2 as shown in FIG. 5E. Voltage
As Va increases, amplifier 24 gradually decreases its output voltage V to maintain the voltage at its inverting input terminal at E/2 (see FIG. 5). As the voltage V decreases, the peak value e ₁ of the signal S ₅ during the period T ₁ decreases, as is clear from the above equation (6), and therefore,
The period T ₁ becomes small, and the output voltage Va of the smoothing circuit 22
gradually decreases. Then, when the voltage Va returns to the voltage E/2 again, the output voltage V of the amplifier 24 stops decreasing, and the voltage is maintained thereafter until there is a change in the capacitance _C3 . In this way, the circuit shown in FIG. 2 operates such that the periods T ₁ and T ₂ are always such that T ₁ =T ₂ . In addition, Fig. 5 (b) and (c) are the signals _S5, respectively.
and signal S ₁ is shown. Further, a dashed line G in FIG. 5E indicates the voltage at the non-inverting input terminal of the amplifier 24.

By the way, the periods T ₁ and T ₂ are as follows: T=-2R ₁ (C ₃ +C ₄ +Cs)ln{e/(E/2)+e}...(9) However, R ₁ : Value of resistor 15 e : Period In T ₁ , the voltage e ₁ is given by the equation, and in the period T ₂ , the voltage e' ₁ is given by the equation. Note that "e" in the above equation (9) is the voltage e ₁ shown in FIG. 3E during the period T ₁ , and is given by the above-mentioned equation (2). Further, during the period T ₂ , the voltage e ₁ ' shown in FIG. 3E is given by the above-mentioned equation (3). In the above equation (9), −2R ₁ (C ₃ +C ₄ +Cs) is constant in both periods T ₁ and T ₂ .
Therefore, T ₁ = T ₂ holds, e ₁ / (E/2) + e ₁ = e' ₁ / (E/2) + e' ₁ ...
(10) This means that the formula holds true. And this (10)
By transforming the formula, we obtain the following formula: e ₁ = e′ ₁ ……(11). In this equation (11), the above equation (6) and (3)
By substituting the formula and then substituting the formula (7), the following formula is obtained: C ₃ /C ₃ +C ₄ +Cs・V=C ₄ /C ₃ +C ₄ +Cs・E...(12) From this formula, The following formula is obtained: V=C ₄ /C ₃ ·E (13).

That is, in the circuit shown in FIG. 2, the output voltage V of the integrating circuit 17 has a value proportional to C ₄ /C ₃ , and this value is not affected by the stray capacitance Cs at all. Furthermore, when the sensor 11 shown in FIG. 2 is used, C ₄ =constant, and therefore the output voltage V has a value proportional to 1/C ₃ . That is,
When using the sensor 11 shown in FIG. 2, an output proportional to 1/C ₃ that cannot be obtained with other methods,
In other words, an output proportional to a change in the physical quantity can be obtained as the output of the integrating circuit 17.

Note that there is a relationship between voltage V and power supply voltage E as follows: V<E...(14), and by substituting the above equation (13) into equation (14), C ₄ < C ₃ ...(15) The following relationship is obtained. That is, in order for the circuit shown in FIG. 2 to operate normally, the relationship expressed by equation (15) is required.

FIG. 6 is a circuit diagram showing the configuration of a second embodiment of the present invention, and in this figure, parts corresponding to those in FIG. 2 are given the same reference numerals. In the circuit shown in this figure, the output voltage V of the amplifier 24
is converted into a current signal of 4 to 20 mA by a series circuit of a field effect transistor 32 and a Zener diode 33, and is output.
The output current is current-voltage converted by an amplifier 36 and supplied to the positive power supply terminal of the NAND gate 13. This circuit also provides the same characteristics and effects as the circuit shown in FIG. 2.

In the first and second embodiments described above, one of the capacitances C ₃ and C ₄ is used as the sensor 11c.
Although a device in which only C ₃ changes according to a physical quantity was used, the capacitive conversion device according to the present invention has capacitance C ₁ ,
It is also possible to use one in which both C ₂ change according to physical quantities.

As explained above, according to the present invention, the oscillation frequency is determined alternately between the first and second capacitors connected in series, the capacitance of at least one of which changes in accordance with changes in the physical quantity to be detected. an oscillation circuit as an element, a counter for counting the output of the oscillation circuit, a switching means for switching the first and second capacitances in accordance with the output of the counter, and a smoothing device for smoothing the output of the counter. and an amplification means for amplifying the output of the smoothing means and transmitting the device output, the output of the smoothing means always being a constant value regardless of the values of the first and second capacitances. At least one of the voltages applied to the first and second capacitances is controlled by the output of the amplification means so that the first and second capacitances are maintained.
It is possible to provide a capacitive conversion device that is not affected by stray capacitance that exists between the connection point of the second capacitance and ground.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a configuration example of a conventional capacitive conversion device, FIG. 2 is a circuit diagram showing a configuration of a first embodiment of the present invention, and FIG. 3 is a circuit diagram showing an oscillation circuit 18 and a flip-flop in the same embodiment. 16, FIG. 4 is a diagram showing the coupling state between the inverter 13 and the inverting amplifier 12 in the same embodiment, and FIG. 5 is a waveform diagram for explaining the operation of the entire embodiment. The waveform diagram and FIG. 6 are circuit diagrams showing the configuration of a second embodiment of the present invention. 13, 14... NAND gate (switching means), 1
6...Flip-flop (counter), 17...
Integrating circuit, 18...Oscillating circuit, 22...Smoothing means, _C3 ...First capacitance, _C4 ...Second capacitance.

Claims (1)

[Claims] 1. A first and a second connected in series, the capacitance of at least one of which changes according to changes in the physical quantity to be detected.
an oscillation circuit that uses the electrostatic capacitance as an element that alternately determines the oscillation frequency; a counter that counts the output of the oscillation circuit; and the first and second electrostatic capacitances that correspond to the output of the counter. It comprises a switching means for switching, a smoothing means for smoothing the output of the counter, and an amplification means for amplifying the output of the smoothing means and transmitting a device output, and the output of the smoothing means is the same as that of the first and second counters. At least one of the voltages applied to the first and second capacitances is controlled by the output of the amplifying means so as to always maintain a constant value regardless of the value of the capacitance. capacitive conversion device.