JPH0412813B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a capacitive displacement converter that converts physical displacement based on changes in physical quantities such as pressure and tension into electrical signals via capacitance. In particular, the present invention relates to a capacitive displacement transducer that eliminates the influence of distributed capacitance that occurs between the case and the case.

<Prior art> Such a capacitive displacement transducer detects the flow rate or pressure of various processes as a change in capacitance,
It is used when converting into an electrical signal and transmitting it to a distant receiving unit.

However, in capacitive displacement transducers that detect displacement etc. as changes in capacitance, there is a distributed capacitance interposed between the fixed electrode and the movable electrode and the case, and these distributed capacitances cause the conversion characteristics to be non-linear. This has caused problems such as errors in measurements.

In order to solve these problems, for example, a ``capacitive displacement converter'' (Japanese Patent Laid-Open No. 57-26711) has been proposed. FIG. 1 shows an example of the configuration of a capacitive sensor. In FIG. 1a, the first electrode SP ₁ and the second electrode are fixed vertically opposite to the common electrode MP.
SP ₂ is arranged, and a capacitance C ₁ is formed between the common electrode MP and the first electrode SP ₁ , and a capacitance C ₂ is formed between the common electrode MP and the second electrode SP ₂ . When a mechanical displacement force P corresponding to the physical displacement to be detected is applied to the common electrode MP, the common electrode MP moves, and thus the capacitances C ₁ and C ₂ change. FIG. 1b shows an equivalent circuit corresponding to a. In the diagram
C _sp indicates the distributed capacitance formed between the case and the case.

FIG. 2 shows the proposed conversion circuit using this capacitive sensor. The connection point between the capacitances C ₁ and C ₂ is connected to the input end of the inverter G ₁ , and a constant value current limiting circuit CC ₁ is connected in negative feedback between the output end and the input end of the inverter G 1 . The output terminal of the inverter G ₁ is connected to the input terminal C _L of the n-bit counter CT ₁ , and its output terminal Q _o is connected to the first electrode side of the capacitor C ₁ via the NAND gate G ₂ . G ₃ , capacitance C ₂ through NAND gate G ₄
is connected to the second electrode side. Furthermore, the other input ends of the NAND gates G ₂ and G ₄ are connected to the output end of the inverter G ₁ .

With this configuration, the first positive feedback loop to the inverter _G1 is formed by the NAND gate _G2 and the capacitance _C1 ,
Inverter G ₁ with NAND gate G ₄ and capacitance C ₂
A second positive feedback loop is formed, and these loops are alternately switched by the output of the counter CT ₁ via NAND gates G ₂ and G ₄ to continue oscillation.

The output of the counter _CT1 is smoothed by a filter circuit _FC1 .

When the output A of the NAND gate _G2 is set to the "H" level (Fig. 3A) and the voltage +E is generated, the rise of the voltage increases the capacitance _C1 , the distributed capacitance _Cs0 , and the capacitance _C2. The combined capacitance C _t is charged in series, and the input terminal of the inverter G ₁ suddenly reaches a constant voltage and rises almost vertically as shown in FIG. 3B. Therefore, the terminal voltage change e ₁ of the distributed capacitance C _s0 with respect to the threshold level V _TH of the inverter G ₁ is expressed by the following equation.

e ₁ = C ₁ /C ₁ +C _t (1) At this time, the output C of inverter G ₁ is at “L” level (C in Figure 3), and the inverter
Since constant value current limit circuit CC ₁ is connected between the input and output of G ₁ , the charge in distributed capacitance C _s0 and capacitance C ₂ is transferred to constant value current limit circuit CC ₁ and inverter.
Discharge begins immediately through the output impedance of _G1 , but this discharge current i is controlled by the constant current limiter.
Since the current is regulated to a constant value by CC ₁ , the output B decreases linearly (Fig. 3B). The discharge time _t1 required to reduce the voltage to the threshold level _VTH can be obtained from the following equation.

it ₁ = e ₁ (C ₁ +C _t ) (2) From equations (1) and (2), t ₁ = C ₁ E/i (3). When the threshold level V _TH of inverter G ₁ is reached, the output C of inverter G ₁ is inverted and becomes "H" level, and as a result, the output A of NAND gate G ₂ becomes "L" level, and (1), (2) Charging and discharging with opposite polarity are performed with the same value as the equation. That is, when the output A of the NAND gate _G2 changes from the "L" level to the "H" level, charging is performed with a voltage (E-0) that changes from zero to E, and formula (1) is obtained. For the change from “H” level to “L” level (0-
Charging is performed by changing voltage E), and the charging is the same value as Equation (1) and has the opposite polarity. For this reverse polarity charging, discharging is performed using a constant current i from the constant current limiting circuit CC ₁ , so that the discharging time t′ ₁
is also equal to the discharge time _t1 , and the following equation holds.

t ₁ =t′ ₁ (4) Since these relationships are the same even if the output of the counter CT ₁ is switched to the capacitance C ₂ side after a predetermined number of counts, the following equation holds true.

t ₂ = C ₂ E/i (5) Therefore, during the “H” period of the pulse signal obtained from the output Q _o of the counter CT ₁ , the capacitance C ₁ is “L”
The period corresponds to the capacitance C ₂ , and if this is averaged by the filter circuit FC ₁ , the duty ratio of the pulse signal can be found, so C ₁ / (C ₁ + C ₂ )
The result is the calculation result. This calculation result is the common electrode MP
gives a value proportional to the displacement of .

However, in such a conversion circuit, the capacitance
Since the "H" time width and "L" time width signals of the output of the counter CT _{1 ,} which are proportional to the values of C 1 and C ₂ , are determined depending on the constant current characteristics of the constant value current limiting circuit CC, the constant value current is It has the disadvantage that if the limiting circuit _CC1 deteriorates, it will cause an error. For example, in Figure 2, if a degraded resistance R _cc is formed as shown by the dotted line as a result of deterioration of the constant value current limiting circuit CC ₁ , considering equation (1), there is a difference between switching to the capacitance C ₁ side and the capacitance Since the terminal voltage changes e ₁ and e ₂ that occur when switching to the capacitance C ₂ side are different, the constant value current limiting circuit CC ₁ is bypassed by the degraded resistor R _cc and the current flows between the capacitance C ₁ side and the capacitance C ₂ side. It has the disadvantage that the difference between the sides creates an error factor.

<Object of the invention> The present invention aims to provide a versatile capacitive displacement converter that is not dependent on such characteristic deterioration of a constant value current limiting circuit and can further effectively eliminate distributed capacitance. purpose.

<Configuration of the Invention> The main configuration of the present invention that achieves this object is a capacitive displacement transducer, which is formed by a first electrode and a second electrode with respect to a common electrode, and is configured to detect a physical displacement to be detected. a pair of capacitances that change accordingly, an amplifying means for detecting the potential of the common electrode, a pair of fixed voltages that are in a differential mode with respect to a reference potential, and a common mode variable voltage that is related to the output of the amplifying means. a switch means for switching and applying the voltage to the first and second electrodes in a predetermined switching procedure; and switching means for switching the first selection voltage and the second selection voltage in a predetermined switching procedure and applying them to the common electrode via the fixed capacitor. and a feedback means for controlling the variable voltage so that the voltage of the common electrode detected by the amplifying means becomes a predetermined value, and outputting the variable voltage corresponding to the physical displacement. This is how it was done.

<Example> Hereinafter, an example of the present invention will be described based on the drawings. In the following description, parts having the same functions will be designated by the same reference numerals and the description will be omitted as appropriate.

FIG. 4 is an explanatory diagram for explaining the basic concept of the present invention. In FIG. 4a, a positive fixed voltage +E is applied to the first electrode SP ₁ via the switch S ₁ with respect to the reference potential point, and the second electrode SP ₂ is applied via the switch S ₂
A negative fixed voltage -E is applied to the reference potential point via. Furthermore, a first selection voltage, for example a variable voltage V, is applied to the common electrode MP via a switch _S5 and a fixed capacitor _Ccp . The potential of the common electrode MP is extracted as a voltage e. In FIG. 4b, the first electrode SP ₁ and the second electrode SP ₂ are connected to the switch S ₃ ,
A variable voltage V is applied between the connection point of switches _S3 and _S4 and _the reference potential point. Furthermore, a second selection voltage, for example a reference voltage, is applied to the common electrode MP via a switch _S6 and a fixed capacitor C _cp . Note that C _s0 in FIG. 4 indicates distributed capacitance.

In the above configuration, the first electrode SP ₁ and the second electrode
SP ₂ is excited in the differential mode shown in FIG. 4a in the first phase and in the common mode shown in FIG. 4b in the second phase. Further, the common electrode MP is excited with the variable voltage shown in FIG. 4a in the first phase, and with the reference voltage shown in FIG. 4b in the second phase. The example shown in FIG. 4 is characterized in that these first and second phases are repeated.

FIG. 5 shows how the voltage of each electrode changes in this case. Figure 5a shows the voltage of the first electrode;
b shows the voltage of the second electrode, and c shows the change in the voltage of the common electrode for each phase.

FIG. 6 shows an embodiment in which the concept shown in FIG. 4 is implemented in a concrete form. A positive fixed voltage +E is applied to the first electrode SP ₁ with respect to the reference potential point via the switch S ₁ , and a negative fixed voltage −E is applied to the second electrode SP ₂ with respect to the reference potential point via the switch S ₂ . E is applied. Further, the common electrode MP is connected to a reference potential point via a fixed capacitor C _cp and a switch S ₆ .
C _s0 indicates distributed capacitance, and has the effect of changing the voltage e generated at the common electrode MP. Common electrode MP
The potential of is taken out as a voltage e and input to the integrator Q ₁ via the resistor R ₁ . Resistor R ₁ and integrator
A switch S _R for synchronous rectification is connected between the input connection point of Q ₁ and the common potential point. integrator
The voltage V at the output terminal of Q ₁ is determined by the switch S ₅ and the fixed capacitance C _cp
It is applied to the common electrode MP via the switch S ₃ and S ₄ to the first electrode SP ₁ and the second electrode SP ₂ via the switches S 3 and S 4 . Each switch S ₁ to _{S 6} and S _R is an oscillator OSC
is controlled by a switching signal.

First, in the first phase, switches S ₁ and S ₂ are turned on at the same time, so a fixed voltage of +E is applied to the first electrode SP ₁ and a fixed voltage of -E is applied to the second electrode SP ₂ . Since S ₃ and S ₄ are turned on simultaneously, the variable voltage V is applied to both the first electrode SP ₁ and the second electrode SP ₂ . Further, in the first phase, the switch _S5 is turned on to apply the converted voltage V to the common electrode MP via the fixed capacitor C _cp , and in the second phase, the switch _S6 is turned on to apply the reference voltage.

First, a switch that applies voltage to the common electrode
The operation when S ₅ , S ₆ and fixed capacitance C _cp are excluded will be explained, and then the operation will be explained when a voltage is applied to the common electrode.

First, in the first phase, switches S ₁ and S ₂ are turned on at the same time, so a fixed voltage of +E is applied to the first electrode SP ₁ and a fixed voltage of -E is applied to the second electrode SP ₂ . Since S ₃ and S ₄ are turned on simultaneously, the variable voltage V is applied to both the first electrode SP ₁ and the second electrode SP ₂ . The amount of charge transfer accompanying the repetition of this first and second phase excitation is
C ₁ (E-V) - C ₂ (E+V), and the voltage e generated at the common electrode MP is equal to the total capacity (C ₁ +C ₂ +
C _s0 ) is given by the following equation.

C ₁ (E-V)-C ₂ (E+V) = (C ₁ +C ₂ +C _s0 )e (6) Here, when the excitation of each phase is repeated and the entire system is stable, the voltage e of the common electrode MP is Since it is zero, the voltage V of the output of the integrator _Q1 is expressed by the following equation, and has a value proportional to the displacement of the common electrode MP.

V=C ₁ −C ₂ /C ₁ +C ₂ (7) The distributed capacitance C _s0 between the common electrode MP and the case is controlled so that e=0, so it is not affected.

Next, the switch that applies voltage to the common electrode MP
The operation when S ₅ , S ₆ and fixed capacitance C _cp are used together will be explained.

In this case, the equation corresponding to equation (6) is the following equation (8).

C ₁ (E-V)-C ₂ (E+V)+C _cp V=(C
₁ +C ₂ +C _s0 +C _cp )e(8) The condition for e=0 in this equation is C ₁ (E-V)-
It is given by C ₂ (E+V)=−C _cp V, and e=0 is obtained when the difference between the amount of charge in capacitance C ₁ and the amount of charge in capacitance C ₂ differs by C _cp V. That is, the system shown in FIG. 6 where the unbalanced amount of charge between capacitances C ₁ and C ₂ is controlled by the variable voltage V is e
= converges to 0.

When the capacitance between the first electrode SP ₁ , the second electrode SP ₂ and the common electrode MP changes due to displacement such as deflection of the common electrode, the capacitances C ₁ and C ₂ have a component C′ ₁ that changes due to the displacement. , C′ ₂ , and a fixed capacitance component C _p between the electrodes where no displacement is applied. For example,
Components that change with displacement, such as C ₁ = C' ₁ + C _p and C ₂ = C' ₂ + C _p , become capacitances C _{1 '} and C ₂ ' that are smaller than capacitances C ₁ and C ₂ . .

In this case, the condition for e=0 in equation (8) using capacitances C ₁ ′ and C ₂ ′ is C ₁ ′(EV)−C ₂ ′(E+V)=(2C _p −C _cp )V (9), and if C _cp =2C _p is selected here, C ₁ ′(E−V)=C ₂ ′(E+V) (10). From this equation, the following equation similar to equation (7) is obtained: V=C ₁ ′−C ₂ ′/C ₁ ′+C ₂ ′E (11). Therefore, the fixed capacitance C _cp is defined as the fixed capacitance between the electrodes.
By selecting twice C _p , the influence of interelectrode fixed capacitance C _p can be removed.

As explained above, applying a fixed voltage in the differential mode and a variable voltage in the common mode to the first and second electrodes,
The concept of applying a variable voltage and a reference voltage through a fixed capacitance to a common electrode MP allows a pair of capacitances to be
It is possible to control the unbalanced amount of charge on C ₁ and C ₂ to create a negative feedback system with a predetermined unbalanced point as a stable point, and to detect the true capacitance change component that is not affected by stray capacitance. I can do it.

FIG. 7 shows an example of the concept shown in FIG. 4 in which each switch is switched in phases. That is, FIG. 5 shows the concept shown in FIG. 4 by introducing fixed voltage and variable voltage in the first phase.
Although the configuration is such that the switching is performed alternately as the second phase, in the case of FIG. 7, the application of the fixed voltage and variable voltage is separated from the first phase to the fourth phase, and this is repeated. The first phase is a differential mode, the third phase is a common mode, and the second and fourth phases are a mixed mode.

FIG. 8 shows an embodiment in which the phase separation shown in FIG. 7 is applied to the concept shown in FIG. 4.

The connection point of capacitance C ₁ and C ₂ is buffer gate G ₅
is connected to the input end of the inverter, and its output end is connected to the inverter
Connected to the input end of _G6 . Batshua Gate
A constant value current limiting circuit _CC1 is connected in negative feedback between the input terminal of _G5 and the output terminal of inverter _G6 .
The output end of inverter _G6 is an n-bit counter.
It is connected to the input end C _L of CT ₂ , and its output end Q _o is connected to the input end of charger G ₈ via a NAND gate G ₇ . Charger G ₈ is switch S ₁ , S ₃
is configured and the switch is activated by the logic signal at its input terminal.
S ₁ or S ₃ is turned on, and a positive fixed voltage +E or variable voltage V is supplied to the first electrode SP ₁ to charge the capacitances C ₁ and C ₂ and the distributed capacitance C _s0 . Charger _G8 is composed of, for example, a C-MOS inverter. The inverting output terminal _o of the counter CT ₂ is connected to the input terminal of the charger G ₁₀ via a NAND gate G ₉ . Charger G ₁₀ constitutes switches S ₂ and S ₄ , turns on switch S ₂ or S ₄ by a logic signal at its input terminal, and applies negative fixed voltage -E or variable voltage V to the second electrode.
SP ₂ and charges the capacitance C ₁ , C ₂ or distributed capacitance C _s0 . Furthermore, the other input ends of the NAND gates G ₇ and G ₉ are connected to the input end of the inverter G ₆ .
The output of counter CT ₂ is passed through integrator Q ₂ to voltage V
Output as . Voltage V is fed back to chargers G ₈ and G ₁₀ . Switches S ₅ , S ₆ and fixed capacitor C _cp in FIG. 8 correspond to switches S ₅ , S ₆ and fixed capacitor C _cp shown in FIG. 4, and apply a voltage to common electrode MP.

The operation of the embodiment shown in FIG. 8 will be explained with reference to FIG. First, a case in which switches S ₅ and S ₆ and fixed capacitor C _cp that apply a voltage to the common electrode MP are excluded will be explained, and then a case in which a voltage is applied to the common electrode MP will be explained.

In the first phase of Fig. 7, switch S ₁ is on,
Since switch S ₃ is turned off and switches S ₂ and S ₄ do not change state, a voltage varying from charger G ₈ to a positive fixed voltage +E is applied to capacitor C ₁ . At this time, the capacitance increases due to the rising edge.
Combined capacitance C _t of C ₁ , distributed capacitance C _s0 and electrostatic capacitance C ₂
are charged in series, and the input terminal of the buffer _G5 suddenly reaches a constant voltage and rises almost vertically as shown in Fig. 7h. At this time, the output of inverter _G6 is “L”
Since the constant value current limiting circuit _CC1 is connected between the input terminal of the buffer gate _G5 and the output terminal of the inverter _G6 , discharge starts immediately, but this discharge current i is a constant current. Since the voltage e is regulated to a certain value, the voltage e decreases linearly as shown by the dotted line in Fig. 7h, and _the input voltage of the buffer gate _G5 also _decreases . Since the output of the counter CT 2 decreases and the output terminal Q _o of the counter CT ₂ is at the "H" level, the switch S ₁ of the charger G ₈ is turned off, S ₃ becomes conductive, and the variable voltage V is applied to the capacitor C ₁ . is applied and enters the second phase. Charger G ₁₀
The voltage at the input terminal of counter CT ₂ is the inverted output terminal _o
Since it is at the "L" level, it does not change, and therefore the output of charger _G10 does not change. In this state, the input terminal of the buffer gate _G5 is at the "L" level, so the constant value current limiting circuit _CC1 discharges the charge of each capacitance in the opposite direction. When the voltage across the distributed capacitance C _s0 rises due to discharge and reaches the threshold voltage V _TH of the buffer G ₅ , the output of the buffer G ₅ becomes “L” level and enters the third phase.

In the third phase, the output of buffer _G5 is “L”
level, so the output of counter _CT2 is inverted. However, for simplicity, the output terminal of the counter _CT2 is selected as a bit output that is inverted in one cycle. In this case, since both the output terminal _o of the counter CT ₂ and the output terminal of the buffer G ₅ are at "H" level, the charger G ₁₀ is switched to the switch S ₄ side, and the variable voltage V is applied to both the capacitors C ₁ and C ₂ . (Fig. 7 f, g). After this, discharge is performed at a constant current value i in the same manner as in the first phase, and when the voltage across the distributed capacitance C _s0 reaches the threshold voltage V _TH of the buffer gate G ₅ , the output of the buffer G ₅ becomes “L”. ``The charger G ₁₀ switches to the level side and the charger G 10 switches to the switch S ₂ side and enters the fourth phase.

In the fourth phase, as in the second phase, each capacitance is discharged at a constant value i in the opposite direction as shown by the dotted line in FIG. 7h.

As described above, when charging and discharging are repeated from the first to fourth phases, a voltage corresponding to the threshold level V _TH is determined as the average potential of the distributed capacitance C _s0 , and charging and discharging are performed around this average potential. will be carried out.

The above points can be expressed as follows. Buffer gate in 1st phase and 2nd phase
The voltage change e ₁ with respect to the average potential at the input end of G ₅ is calculated by dividing it by each capacitance, taking into account the voltage change (E-V) shown in FIG. 7f and g, to obtain the following equation.

e ₁ = C ₁ / C ₁ + C _t (E-V) (12) The discharge time t ₁ of this voltage change to the average potential by the constant value current limiter circuit CC ₁ is t ₁ = e ₁ (C ₁ + C _t )/ i (13). From equations (12) and (13), t ₁ =C ₁ EV/i (14) is obtained. Since the operation is symmetrical, the discharge time t ₁ ′ is t ₁ =
t ₁ ′. This relationship is the same in the third and fourth phases, so considering the voltage changes (V-(-E)) shown in FIG. 7f and g, the discharge time t ₂ (=t ₂ ') is as follows.

t ₂ = C ₂ E-V/i (15) When each voltage change e ₁ , e ₁ ′, e ₂ , e ₂ ′ is equal, t ₁ =
Since the relation t ₂ is satisfied, in this state (14),
From equation (15), we obtain C ₁ (E-V)=C ₂ (E+V) (16), that is, V=C ₁ -C ₂ /C ₁ +C ₂ E (17). Since the coefficient of E in equation (17) is proportional to the displacement of the common electrode MP, the variable voltage V is
Proportional to MP displacement.

In the case of the prior art shown in Figure 2, the capacitance C ₁
Alternatively, when C ₂ is switched, a voltage corresponding to this capacitance is generated at the common electrode MP. Since the discharge current is regulated to a constant value i by the constant value current limiting circuit CC ₁ , for example, if the constant value current limiting circuit CC ₁ is short-circuited by the degraded resistor R _cc as shown by the dotted line in Fig. 2, the common electrode Different voltages corresponding to the capacitances C ₁ and C ₂ generated in MP cause discharge characteristics to differ and cause errors. In contrast, in the embodiment shown in FIG. 8, even if the capacitance C ₁ or C ₂ differs in size, the variable voltage V is fed back and adjusted to the fixed voltage by this difference, and the static Since we applied voltages with different amplitudes to the capacitors C ₁ and C ₂ and injected a constant amount of charge so that e ₁ = e ₂ , the characteristics of the constant current limiter CC ₁ deteriorated. However, it is not essentially a cause of error. Therefore, as described later, a resistor can be used in place of the constant value current limiting circuit _CC1 . In this case, the charge/discharge characteristics change exponentially, but this does not essentially result in an error.

Next, an explanation will be given of the operation when switches S ₅ and S ₆ for applying voltage to the common electrode MP and fixed capacitance C _cp are used together in FIG. 8.

The equilibrium condition in this case is given by the following equation.

C ₁ (E-V) + C _cp V = C ₂ (E + V) (18) Here, assuming that the capacitances C ₁ and C ₂ include the fixed capacitance component C _p between the electrodes, C ₁ = C ₁ ′+C _p , C ₂
= C′ ₂ +C _p and 2C _p = C _cp , equation (18) becomes C ₁ ′(E−V)=C ₂ ′(E+V) (19), which gives the same result as equation (11). .

Here, we look at the equilibrium condition of equation (18) in terms of the amount of charge.
First, C ₁ ′ = 60pF, C ₂ ′ = 40pF, C _p = 10pF, C ₁ =
Looking at each term in equation (18) assuming that 70 pF, C ₂ = 50 _p F, C _cp = 20 _p F, and E = 6 volts, C ₁ '(E-V) = 60 x 4.8 = 228 ( picocoulomb) C _p (E-V) = 10 x 4.8 = 48 ( ) C _cp V = 20 x 1.2 = 24 ( ) C ₂ ′ (E + V) = 40 x 7.2 = 288 ( ) C _p (E + V) =10×7.2=72 (〃). Next, this equilibrium state is determined by the above C ₁ =70pF,
Comparing the amount of charge at C ₂ = 50 pF, the above amount of charge is added as follows, and in the case of C ₁ ...C ₁ '(E-V) + C _p (E-V) = 336 (picocoulombs) C ₂ In the case...C ₂ '(E+V)+C _p (E+V)=360 (〃). In other words, the real value lies in balancing the amplification system while leaving behind the unbalanced charges of the large capacitances C ₁ and C ₂ .

FIG. 9 shows another embodiment of the present invention using a Schmitt trigger. The embodiment shown in FIG. 6 is a separately-excited system that realizes the concept shown in FIG. 5, and the embodiment shown in FIG. 9 is a self-excited system that implements the concept shown in FIG.

The common electrode MP and the input end of the amplifier _G11 are connected. Amplifier _G11 has an input hysteresis response and uses, for example, a Schmitt trigger of a C-MOS logic device. A resistor R ₂ is connected between the input and output terminals of the amplifier G ₁₁ to provide negative feedback. The output terminal of the amplifier G ₁₁ is connected to the input terminal C _L of the counter CT ₃ and at the same time to one terminal of each input of an AND gate G ₁₂ and a NAND gate G ₁₃ . The output terminal Q _o of counter CT ₃ is AND gate G ₁₂
and the other end of the input of NAND gate _G13 , respectively. The output terminal _o is connected to the input terminal of the integrator _Q2 . The output end of AND gate G ₁₂ is charger G ₈
The output end of NAND gate G ₁₃ is connected to the input end of charger G ₁₀ , respectively.

Next, the operation of the embodiment shown in FIG. 9 will be explained using the waveform diagram shown in FIG. 10.

Figure 10 1 shows the waveforms of various parts when C ₁ = C ₂ , 2
3 shows the waveform of each part when C ₁ <C ₂ , and 3 shows the waveform when C ₁ >C ₂ . First, assuming that V=0, when C ₁ = C ₂ , the voltage applied from the chargers G ₈ and G ₁₀ is canceled out through the capacitances C ₁ and C ₂ , and the amplifier G ₁₁ has a time constant R ₂ It apparently operates like a simple relaxation oscillation of (C ₁ +C ₂ +C _s0 ) and continues to oscillate at a constant period as shown in FIG. 10, 1, a. Then counter CT ₃
output is “H” level and capacitance is C ₁ < C ₂
For positive charge due to amplifier G ₁₁ , AND gate G ₁₂ , charger G ₈ , capacitance C ₁ and positive feedback to amplifier G ₁₁ , amplifier G ₁₁ , NAND gate G ₁₃ , charger G ₁₀ , static The negative charge due to capacitance C ₂ and negative feedback to amplifier G ₁₁ prevails, reducing the input of amplifier G ₁₁ and causing a decrease in T ₁ (FIG. 10, 2). Next, the output of counter _CT3 is “H”
If the capacitance at the level is C ₁ > C ₂ , the positive charge dominates the negative charge mentioned above, and the amplifier G ₁₁
(Figure ₁₀ , 3).

Here, the voltage e that fluctuates the input waveform of the amplifier _G11 due to these capacitance differences is as follows, assuming that the variable voltage V is fixed, taking into account the amount of charge movement: e=C ₁ (E-V) −C ₂ (E+V)/C ₁ +C ₂ +C _s0 (2
0) becomes. In Figure 9, the variable voltage V is fed back so that the voltage e becomes zero, so if we set e=0 in equation (8), we get V=C ₁ - C ₂ /C ₁ +C ₂ E (21) . The variable voltage V gives a value proportional to the displacement of the common electrode MP. Here, in equation (20), the voltage e is affected by the distributed capacitance C _s0 , and the capacitance C ₁ or
Although it exhibits nonlinearity with respect to changes in C ₂ , by controlling e=0, it is not affected by the distributed capacitance C _s0 and exhibits a linear relationship as shown in equation (21). In this case, the waveforms of each part have a relationship of T ₁ =T ₂ as shown in FIG. 10.

During the _T2 period when the output of counter _CT3 is "L" level, charger _G8 is +E and charger _G10 is -
E is fixedly applied to the capacitances C ₁ and C ₂ . on the other hand,
Amplifier G ₁₁ undergoes relaxation oscillation with a time constant of R ₂ (C ₁ +C ₂ +C _s0 ) and does not respond to the capacitance difference. In the embodiment shown in FIG. 10, switches S ₁ to S ₄ are controlled so that differential mode and common mode are repeatedly applied alternately. Note that the operations corresponding to the switches S ₅ and S ₆ in FIG. 4 are the same as those described above, and therefore their explanation will be omitted.

FIG. 11 shows an embodiment in which variable voltage is converted into current and transmitted through a two-wire line. The embodiment shown in FIG. 6 is a separately excited version of the concept shown in FIG. 5, and the embodiment shown in FIG. 11 is a system in which current is transmitted to a two-wire line.

The power source E _b is connected to the two-wire transmission line l ₁ , l ₂ via the load L.
It is connected to the. A constant current circuit CC ₂ , a Zener diode D _z , and a feedback resistor R _f are connected in series to the other ends of the transmission lines l ₁ and l ₂ to create a circuit power supply voltage +E across the Zener diode D _z .

On the other hand, inverters G ₁₄ , G ₁₅ , G ₁₆ , capacitors
C ₃ , C ₄ and resistor R ₃ constitute an oscillator OSC using a C-MOS circuit. Inverters G ₁₄ to _{G 16} are connected in cascade, and their power supply terminals are commonly connected. These power supply terminals are connected to both ends of a Zener diode _Dz , and are supplied with a power supply voltage +E.

There is also a C-MOS on both ends of the Zener diode _Dz .
Chargers G ₁₇ and G ₁₈ are connected in series, and an inverter is connected to the input end of charger G ₁₇ .
When the power at the input end of G ₁₄ is applied, the charger G ₁₈
The voltage at the output end of the inverter G14 is applied to the input end of the inverter _G14 . Charger G ₁₇ is switch S ₁ , S ₃
The charger _G18 constitutes the switches _S2 and _S4 .

Capacitances C ₁ and C ₂ related to the displacement to be detected are connected in series between the output terminals of the chargers G ₁₇ and G ₁₈ . The common connection point of capacitances C ₁ and C ₂ is connected to the input terminal of amplifier Q ₃ , and the voltage e at this point
amplify. A switch G ₁₉ formed by a C-MOS circuit is connected to the output terminal of the amplifier Q _{3 .}
are controlled and synchronously rectified by the respective voltages at the input and output ends of the inverter _G14 , respectively, and convert the voltage e into a DC voltage e and _d . This DC voltage e _d is smoothed by an integrator Q ₄ and applied to a transistor Q ₅ that controls the currents of the two-wire transmission lines l ₁ and l ₂ .

The voltage obtained by dividing the sum of the feedback voltage obtained at the midpoint of the feedback resistor R _f and the voltage E across the Zener diode D _z is amplified by the amplifier Q ₆ and is converted into a variable voltage V by chargers G ₁₇ , G ₁₈ are returned to the common connection point of

In addition, the voltage E across the Zener diode _Dz is halved at each non-inverting input terminal of the amplifiers Q ₃ , Q ₄ and Q ₆ .
A voltage divided into E/2 is applied, and the voltage point of E/2 is used as the operating reference point.

Next, the operation of FIG. 11 configured as above will be explained using the waveform diagram shown in FIG. 12.

Figure 12 1 shows the voltage waveform 2 of each part when the variable voltage V is fixed when the capacitance is C ₁ < C ₂
shows the voltage waveforms of each part when the feedback effect of the variable voltage V is taken into account.

Charger G ₁₇ Oscillator OSC Inverter G ₁₄
+
The voltages E and V are alternately applied to the voltage e ₁ (Fig. 12 1, c)
is applied to the first electrode SP ₁ forming a capacitance C ₁ . In addition, the charger _G18 receives the oscillation voltage of the output of the inverter _G14 , and alternately changes the voltage between 0 and V.
e ₂ (FIG. 12, 1, d) is applied to the second electrode SP ₂ forming a capacitance C ₂ . In this case, the voltage e generated at the common connection point of capacitances C ₁ and C ₂ is the voltage
It is given as a voltage (FIG. 12, 1, e) obtained by dividing e ₁ and e ₂ by capacitances C ₁ , C ₂ , and C _s0 , and is expressed by the following equation.

e=C ₁ /C ₁ +C ₂ +C _s0 e ₁ −C ₂ /C ₁ +C ₂ +C _s0 e ₂ (22) Here, each voltage e ₁ and e ₂ is e ₁ =E−V (23) e ₂ =V (24). This voltage e is the amplifier Q ₃
After being amplified by the switch _G19, the DC voltage _ed is synchronously rectified by the switch G19, as shown in FIG. 12, f. In this case, since C ₁ <C ₂ , the voltage _ed is a positive voltage with respect to the voltage E/2 at the operating reference point. This DC voltage e _d is transmitted to the integrator Q ₄ , and its output lowers the control current of the transistor Q ₅ to the feedback resistor R _f
, which reduces the value of the variable voltage V through the amplifier _Q6 .

In this way, the variable voltage V is charged as G ₁₇ ,
By feeding back to _G18 , the amplitude of voltage e decreases and converges to zero amplitude. This state is shown in Figure 12 2.
It is shown in In this state, e=0, so
By using equations (22) to (24) and setting e=0, we obtain V=-E/2·C ₁ −C ₂ /C ₁ +C ₂ (25). Since the variable voltage V is proportional to the output current, the output current has a value proportional to the displacement of the common electrode MP. Note that the operations of the switches S ₅ and S ₆ and the fixed capacitor C _cp shown by dotted lines in FIG. 11 are the same as before, and therefore their explanations will be omitted.

FIG. 13 is an explanatory diagram when the selection of the voltage applied to the common electrode is changed in the basic concept shown in FIG. 4. In Fig. 4, when applying a voltage to the common electrode via the fixed capacitor C _cp , a variable voltage V was applied as the first selection voltage and a reference voltage was applied as the second selection voltage, but in Fig. 13, the voltage was fixed to the common electrode. Capacity C ₀
The difference is that fixed voltages +E and -E are applied as the first and second selection voltages when applying a voltage through. In addition, in Figure 13, the fixed capacity
The configuration shown by the dotted line in which a variable voltage V or a reference voltage is applied to the common electrode MP via C _cp and the switch S ₅ or S ₆ has the same function as that shown by the corresponding symbol in FIG. Explanation will be omitted.

In Fig. 13a, a switch is applied from a positive fixed voltage +E to the common electrode MP of capacitances C ₁ and C ₂ .
S ₇ , a power supply operation is applied through the fixed capacitor C ₀ , and in the same figure b, the negative fixed power supply −E is connected to the switch S ₈ , the fixed capacitor
The feature is that it is configured so that power supply operation is applied via C ₀ .

FIG. 14 is a waveform diagram showing the operating procedure of each switch and the potential change of each electrode in FIG. 13. In the case of Fig. 7, the application of fixed voltage and variable voltage was phase-separated from the 1st phase to the 4th phase, but in the case of Fig. 14, it is common to Fig. 7 in that it is phase-separated. However, the difference is that it includes an oscillation mode. That is, Fig. 14a~
By switching the switches shown in g, voltage e is forcibly generated in all phases by turning on or off switches _S7 and _S8 during all phases from the first phase to the fourth phase. Therefore, self-sustained oscillation can be performed by switching the switch. That is, an oscillation mode is added. The voltage changes produced at each electrode by these switch operations are shown in FIGS. 14j-l.

In FIG. 14, no information regarding the capacitance C ₁ or C ₂ is included in each phase of the second phase and the second phase. The benefits in this regard will be discussed later. Differential mode in the third phase (Figure 13a) and common mode in the fourth phase (Figure 13b)
to obtain information about capacitance C ₁ or C ₂ . In this respect, in Fig. 7, information regarding the capacitance C ₁ is provided in the first and second phases, and
This is different from obtaining information about capacitance C ₂ in each phase. The waveforms indicated by dotted lines in FIG. 14h and i indicate the timing when the switches S ₅ and S ₆ shown in FIG. 13 are operated.

Figure 15 shows the 14th concept shown in Figure 13.
An example is shown in which the phase separation shown in the figure is performed.

In contrast to the embodiment shown in FIG. 8, the embodiment shown in FIG. 15 has a fixed capacitance between the input and output of the buffer gate _G5 .
The difference is that the output terminal Q _o of _{the counter CT 2 is} connected to the input terminal of the charger G ₁₀ via the AND gate G ₂₀ . Batshua Gate G ₅
is the gate of a C-MOS logic device,
As shown, two C-MOS inverters are connected in cascade, and the latter C-MOS inverter corresponds to the switches _S7 and _S8 in FIG. Switches S ₅ , S ₆ and fixed capacitance C _cp shown by dotted lines in FIG. 15 correspond to S ₅ , S ₆ , and C _cp shown in FIG. 13.

In the first and second phases of FIG. 14, when the output terminal Q _o of the counter CT ₂ is at the "L" level, the switches S ₃ and S ₄ are turned on, and the first electrode
The fixed voltage V remains applied to SP ₁ and the second electrode SP ₂ , respectively. In this state, the switches _S7 and _S8 are alternately switched based on the threshold level V _T of the buffer gate _G5 , and charging and discharging are repeated via the fixed capacitor _C0 . However, for the sake of simplicity, the waveform diagram shown in FIG. 14 shows the waveform when the counter CT ₂ is switched by counting one cycle. Common electrode MP in this case
_{The change in voltage e at _}
6) becomes. If the current in the constant value current limiting circuit CC ₁ is i, the discharge time t ₃ is given by t ₃ =1/i(C ₁ +C ₂ +C _s0 +C ₀ )e ₃ (27).

The counter changes due to a predetermined number of changes in the inverter G ₆ .
When the level of the output terminal _Qo of CT ₂ is inverted and becomes "H" level, as shown in the third and fourth phases of Fig. 14, the differential mode voltage is applied in the third phase, and the common voltage is applied in the fourth phase. Mode voltages are applied to the first electrode SP ₁ and the second electrode SP ₂ , respectively, and the change e ₄ in the voltage e at the common electrode MP has a value expressed by the following equation.

e ₄ = C ₀ (+E-(-E)) + C ₁ (+E
-V) -C ₂ (V-(-E))/C ₁ +C ₂ +C _s0 +C ₀ (28) The discharge time t ₄ due to the current i in the constant current limiter circuit CC ₁ is t ₄ = 1/i (C ₁ +C ₂ +C _s0 +C ₀ )e ₄ (29). From equations (26) to (29), we obtain t ₃ = 1/i・2C ₀ E (30) t ₄ = 1/i [2C ₀ E+C ₁ (EV)−C ₂ (E+V)] (31) .

FIG. 16 is a waveform diagram showing differences in waveforms depending on the magnitude of capacitances C ₁ and C ₂ . Assuming that the variable voltage V is zero and there is no feedback, Fig. 16 1 is
If C ₁ = C ₂ , 2 is C ₁ < C ₂ , 3 is C ₁ > C ₂
Each case is shown. Since the operation is symmetrical, t ₃ = t ₃ ′, and this time (t ₃ + t ₃ ′) is the capacitance
It does not change depending on the values of C ₁ and C ₂ . On the contrary,
(t ₄ +t ₄ ') changes depending on the magnitude of capacitance C ₁ and C ₂ . When C ₁ < C ₂ , the waveform (t ₃
+t ₃ ′)>(t ₄ +t ₄ ′), the average voltage of the output of counter CT ₂ decreases, the variable voltage V becomes smaller, and C ₁
>C ₂ , the waveform becomes as shown in FIG. 16, and the variable voltage V increases, contrary to the case 2. The variable voltage V is fed back to the capacitances C ₁ and C ₂ and is controlled and stabilized so that the output voltage of the counter CT ₂ becomes zero. At this time
t ₃ = t ₄ . Therefore, from equations (30) and (31), t ₃ = t ₄
Then, we obtain V=C ₁ −C ₂ /C ₁ +C ₂ E (32). Since the coefficient of E in equation (32) is proportional to the displacement of the common electrode MP, in the end, the variable voltage V is
Proportional to MP displacement.

In addition, in the embodiment shown in FIG.
The fixed capacitance C ₀ added between the input and output terminals of G ₅ makes it possible to maintain oscillation regardless of the presence or absence of capacitances C ₁ and C ₂ . This eliminates the need to alternately use capacitances C ₁ and C ₂ , increasing the degree of freedom in implementation.

That is _, in _the embodiment shown in FIG. 15 in which the operating procedure of each switch shown in FIG. ing.
Therefore, this empty slot can be used to measure the temperature of the sensor, the permittivity of the dielectric material, etc., and the capacitance _C1 or
It can be used as an information slot to insert other information that requires correction to the information in _C2 . Information can be inserted into empty slots by applying voltages similar to C ₁ , C ₂ , and C ₀ via arbitrary fixed capacitors.
It can be freely selected and executed as an effective quantity such as the capacitances C ₁ and C ₂ or as an invalid quantity such as the fixed capacitance C ₀ .

In addition, the addition of fixed capacitance C ₀ is a buffer gate.
G ₅ , the capacitance C 1 , _{C 2 when} the current of the constant value current limiting circuit CC ₁ decreases in a minute period when the inverter G ₆ inverts the level, that is, when the inversion occurs
The positive feedback loop to the buffer gate G 5 through the buffer gate G ₅ serves to eliminate the slowing effects shown in FIG. 17 associated with transmission loss elements in the positive feedback loop. In other words, the fixed capacitor _C0 , which serves as the shortest positive feedback loop to the buffer gate _G5 , realizes inversion before the current of the constant current limiter _CC1 decreases, and is useful for eliminating slight unstable error factors.

In addition, when configuring this with only resistor _R4 instead of constant value current limiter _CC1 , formulas (27) and (29)
The expressions are replaced with the following expressions (33) and (34), respectively.

t ₃ ″=−R ₄ (C ₁ +C ₂ +C _s0 +C ₀ ) [l _o E/e ₃ +E (33) t ₄ ″=−R ₄ (C ₁ +C ₂ +C _s0 +C ₀ ) [l _o E/ e ₄ + E (34) t ₃ and t ₄ in equations (27) and (29) are proportional to e ₃ and e ₄ , but in equations (33) and (34)
This shows that t ₃ ″ and t ₄ ″ have a nonlinear relationship with e ₃ and e ₄ . FIG. 18 is a waveform diagram corresponding to FIG. 16 in this case, and FIG. 19 shows a relative change in discharge time corresponding to a relative change in voltage e. In this case as well, the condition t ₃ ″=t ₄ ″ is derived as e ₃ =e ₄ , and equation (32) is finally obtained. In other words, when finding equilibrium based on t ₃ ″=t ₄ ″, it is possible to obtain an output proportional to displacement even when nonlinearity is exhibited as shown in equations (33) and (34). Therefore, the constant value current limit circuit _CC1 deteriorates and the deteriorated resistor
Even when it is assumed that both ends of R _cc are short-circuited, this will not be an error factor.

FIG. 20 shows an embodiment in which the circuit is constructed using a single power supply in contrast to the embodiment shown in FIG. 15.

That is, in the embodiment shown in FIG. 15, zero was the reference potential point for operation, but in FIG. 20, by moving the reference potential point for operation to E/2, it is possible to operate with a single power supply. In other words, for Fig. 15, the potential point of E/2 is zero, the potential point of +E is +E/2,
By regarding the common potential point as -E/2 and (V-E/2) as V, the embodiment in FIG. 20 operates similarly to the embodiment in FIG. 15.

FIG. 21 is a waveform diagram in FIG. 20 corresponding to FIG. 16.

In addition, in each of the embodiments shown in FIGS. 8, 9, and 15, considering the operation with a single power supply in FIG. 20, the current is converted to a two-wire line as shown in FIG. 11. It can be made to transmit.

FIG. 22 shows an embodiment that is slightly modified from the embodiment shown in FIG. In the embodiment shown in FIG. 8, the output of the inverter _G6 is negatively fed back to the input terminal of the buffer gate _G5 via the constant current limiting circuit _CC1 .
In the configuration shown in the figure, negative feedback is applied via resistor _R5 . Further, in the embodiment shown in FIG. 22, the output of the buffer gate _G5 is directly applied to the counter _CT2 . In the case of Fig. 8, positive feedback was applied to the capacitance C ₁ via the charger G ₈ which functions as an inverter composed of a NAND gate G ₇ and C-MOS, but in the case of Fig. 22, is and gate
Positive feedback is applied via a charger _G22 which functions as a buffer gate consisting of _G21 and C-MOS. Its logical operation is the same as in FIG. The rear stage that makes up Charger G ₂₂ is the switch.
It corresponds to S ₁ and S ₃ . As with the case of the _C1 side, feedback is applied to the capacitance _C2 side from the output of the buffer gate _G5 via the AND gate _G28 and the charger _G24 . The latter stage of charger G ₂₂ corresponds to switches S ₂ and S ₄ .

Since the operation is the same as that shown in FIG. 8, detailed explanation will be omitted, but waveforms of each part are shown in FIG. 23. The waveform diagram in this case shows the case where the output terminal Q _o is selected where the counter CT ₂ is inverted for two cycles of input change. Figure 23 shows C ₁ =
The waveforms of each part in the case of C ₂ are shown, but C ₁ = C ₂
When the state becomes C ₁ >C ₂ as shown in FIG. 24, e ₁ >e ₂ and T ₁ >T ₂ as shown in FIG. 24, b. Therefore, due to this change in the duty cycle, the average value of the output voltage of the counter CT ₂ increases and the variable voltage V of the integrator Q ₂ is increased to the 24th
As shown in Fig. 2, c, the state changes from 1 to 2 in Fig. 24, and finally, as shown in Fig. 23, e ₁ =
e Return to state ₂ . In this state, the variable voltage V is proportional to the displacement of the common electrode MP, as shown in FIG.

<Effects of the Invention> As specifically explained above with the examples,
According to the present invention, there are the following effects.

(1) According to the first invention, a differential mode fixed voltage and a common mode variable voltage are switched in a predetermined switching procedure and applied to the first and second fixed electrodes of the capacitance to be detected, Furthermore, by applying a selection voltage to the common electrode via a fixed capacitor and controlling the voltage generated from the common electrode due to switching to be kept constant, the "unbalanced amount of charge" is controlled to the first and second capacitors. I was able to give. As a result, detection that also excludes the constant components of the first capacitance and the second capacitance becomes possible.

Furthermore, when a self-oscillation type amplifier circuit is used as the amplification means, the influence of distributed capacitance can be removed without depending on the characteristic deterioration by using the oscillation constant by the constant value current limiting circuit according to the conventional technology. We have realized a capacitive displacement converter that can be applied both when switching a switch by external excitation and when switching a switch by self-excitation by causing the amplification system to self-oscillate.

(2) According to the second invention, in addition to the effects of the first invention, a positive feedback means having a fixed capacitance is provided and the phases are separated, so that a phase having an empty slot can be generated, and a phase having an empty slot can be generated. Other information for correction can also be inserted, allowing for multifaceted use.

Furthermore, adding a fixed capacitor has the effect of eliminating the slowing effect due to propagation delay in the positive feedback loop via the capacitances C ₁ and C ₂ .

(3) According to the third invention, in addition to the effects provided by the first invention, it is possible to further convert the current value to the value of the current flowing through the two-wire line.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a capacitive sensor, Fig. 2 is a conventional capacitive displacement converter using the capacitive sensor shown in Fig. 1, and Fig. 3 shows each part of the device shown in Fig. 2. FIG. 4 is an explanatory diagram showing the concept of the present invention. FIG. 5 is a waveform diagram showing the voltage waveform of each electrode shown in FIG. 4. FIG. 6 is a diagram illustrating the concept shown in FIG. 4. An example of implementation in a typical form, FIG.
A waveform diagram when phase separation is applied to the concept shown in the figure, Fig. 8 is an example when the phase separation of Fig. 7 is applied to the concept shown in Fig. 4, and Fig. 9 is a case where a Schmitt trigger is used. FIG. 10 is a waveform diagram showing voltage waveforms at various parts of the embodiment shown in FIG. 9, and FIG. 11 is an embodiment of the invention configured as a two-wire displacement converter. 12 is a waveform diagram showing the voltage waveforms of each part in FIG. 11, FIG. 13 is an explanatory diagram explaining the concept when an oscillation mode is added to the concept shown in FIG. 14 is a waveform diagram showing the switch operation in FIG. 13, FIG. 15 is a circuit diagram showing an example of the switch operation in FIG. 14 for the concept shown in FIG. 13, and FIG. 16 is a waveform diagram showing the switch operation in FIG. A waveform diagram showing the waveforms of each part in the figure, Figure 17 is a waveform diagram explaining the slow speed effect in Figure 15, and Figure 18 is a waveform diagram showing the waveform of each part in the figure.
Waveform diagram 1 corresponding to FIG. 16 when the constant value current limiter circuit in FIG. 5 is replaced with a resistor.
Figure 9 is a characteristic diagram illustrating nonlinearity when the constant value current limiting circuit in Figure 15 is replaced with a resistor, and Figure 20 is a characteristic diagram showing the circuit using a single power supply for the example shown in Figure 15. Circuit diagram when configured, No. 21
The figure is a waveform diagram showing the waveforms of each part in Fig. 20,
FIG. 22 is a circuit diagram showing a modified example of FIG. 8, FIG. 23 is a waveform diagram showing waveforms of each part of the embodiment shown in FIG. 22, and FIG. FIG. 3 is a waveform diagram illustrating differences in waveforms of each part. C ₁ , C ₂ ... Capacitance, C _s0 ... Distributed capacitance, SP ₁
...First electrode, SP ₂ ...Second electrode, MP...Common electrode, CC ₁ ...Constant current limit circuit, +E, -E...
Fixed voltage, V...Variable voltage, _S1 to _S8 ...Switch, _Q1 , _Q2 ...Integrator, _G8 , _G10 , _G17 , _G18 ...
Charger, CT ₁ , CT ₂ , CT ₃ ... Counter, G ₅
……Basshuagate, G ₆ ……Inverter, OSC
...Oscillator, C ₀ ...Fixed capacitance, CC ₂ ...Constant current circuit.

Claims (1)

[Scope of Claims] 1. A pair of capacitances formed by a first electrode and a second electrode relative to a common electrode and that change according to a physical displacement to be detected, and an amplification for detecting the potential of the common electrode. applying a pair of fixed voltages in a differential mode with respect to a reference potential and a variable voltage in a common mode related to the output of the amplifying means to the first and second electrodes in a predetermined switching procedure; another switch means that switches between a first selection voltage and a second selection voltage according to a predetermined switching procedure and applies the voltage to the common electrode via a fixed capacitance; and a voltage of the common electrode detected by the amplification means. feedback means for controlling the variable voltage so that the voltage becomes a predetermined value, and outputting the variable voltage corresponding to the physical displacement. 2. As the switching procedure, the fixed voltage in a differential mode and the variable voltage in a common mode are alternately applied to the first and second electrodes, and the variable voltage and the variable voltage are applied to the common electrode as the first selection voltage. Second
2. The capacitive displacement converter according to claim 1, wherein reference voltages from the reference potential are alternately applied as selection voltages via the fixed capacitors. 3. A first amplifier circuit having negative feedback means for detecting the potential of the common electrode based on a predetermined threshold value and returning the detected potential to the threshold value as the amplification means; and an output change period of the first amplifier circuit. A counter circuit for counting, and a second amplifier circuit for increasing or decreasing the variable voltage in response to the output level of an arbitrary bit of the counter circuit, the output level of the first amplifier circuit being equal to the output level of the counter circuit. Claim 1, characterized in that self-oscillation type amplification means is used which switches said switch means in relation to said switch means and switches said other switch means in relation to at least the output level of said first amplification circuit. The capacitive displacement converter described in Section 1. 4 The switching procedure includes a first phase in which the fixed voltage in a differential mode is applied to the first and second electrodes, and a first phase in which the variable voltage is applied to the first electrode and the second phase is applied to the second electrode. a second phase in which the fixed voltage of a predetermined polarity is applied, a third phase in which the variable voltage in a common mode is applied to the first and second electrodes, and the polarity is opposite to the first electrode. a fourth electrode that applies the fixed voltage of polarity and applies the variable voltage to the second electrode;
2. The capacitive displacement converting device according to claim 1, wherein each phase including a phase is repeated. 5 a pair of capacitances formed by a first electrode and a second electrode with respect to the common electrode and which change according to the physical displacement to be detected; an amplifying means for detecting the potential of the common electrode; switch means for switching and applying a pair of fixed voltages in a differential mode and a variable voltage in a common mode related to the output of the amplifying means to the first and second electrodes in a predetermined switching procedure; a fixed capacitor having one end connected to a common electrode; and a feedback means for controlling the variable voltage so that the voltage of the common electrode detected by the amplifying means becomes a predetermined value; A capacitive displacement converter that applies a fixed voltage that is in phase with the input voltage of the amplification means and outputs the variable voltage that corresponds to the physical displacement. 6. The switching procedure includes a first phase in which the variable voltage in a common mode is applied to the first and second electrodes and the second fixed voltage in a predetermined polarity is applied to the other end of the fixed capacitor; 1st and 2nd
a second phase in which the variable voltage in a common mode is applied to the electrode and the second fixed voltage having a polarity opposite to the fixed capacitor is applied to the other end of the fixed capacitor; and to the first and second electrodes. Said first in differential mode
a third phase in which a fixed voltage is applied and a second fixed voltage of the predetermined polarity is applied to the other end of the fixed capacitor;
a fourth applying the variable voltage in a common mode to the first and second electrodes, and applying the second fixed voltage having the opposite polarity to the other end of the fixed capacitor;
6. The capacitive displacement converter according to claim 5, wherein the variable voltage is output by repeating each phase including a phase. 7 a pair of capacitances formed by a first electrode and a second electrode with respect to a common electrode and which change according to the physical displacement to be detected; an amplifying means for detecting the potential of the common electrode; switch means for switching and applying a pair of fixed voltages in a differential mode and a variable voltage in a common mode related to the output of the amplifying means to the first and second electrodes according to a predetermined switching procedure; voltage stabilizing means for receiving power from the outside through the line to energize the internal circuit; current adjusting means for adjusting the current flowing through the two wires in response to the output of the amplifying means; A capacitive displacement converting device, comprising current/voltage converting means for feeding back a voltage proportional to the current as the variable voltage, and transmitting a current flowing through the two wires corresponding to the physical displacement.