JPS6351248B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a capacitive displacement converting device that converts physical displacement based on changes in physical quantities such as pressure and tension into electrical signals.

Such a displacement converter is used when detecting the flow rate or pressure of various processes using a capacitive sensor, converting it into an electrical signal, and transmitting the detection result to a remote receiving unit or the like. By the way, in commonly used capacitive sensors, there is a distributed capacitance as an invariant component that exists between a fixed electrode and a movable electrode, and a distributed capacitance that exists between a fixed electrode, a movable electrode, and a case. , these distributed capacitances cause a problem in which the conversion characteristics become non-linear.

Therefore, the applicant of the present invention first proposed a "capacitive displacement converter" (Japanese Patent Application No. 101699/1982) that can eliminate the influence of this distributed capacitance on the conversion characteristics.
has been applied for. Hereinafter, first, this "capacitive displacement converter" will be explained.

Figure 1 is a conceptual diagram of a differential capacitive sensor used in this "capacitive displacement transducer", in which a movable electrode MP provided between fixed electrodes SP ₁ and SP ₂ responds to the physical displacement to be detected. The first and second capacitances formed by fixed electrodes SP ₁ and SP ₂ move between fixed electrodes SP 1 and SP 2 according to the mechanical displacement caused by them.
C ₁ and C ₂ change differentially.

Figure 2 is an equivalent circuit of Figure 1 that takes into consideration the existence of distributed capacitance, and the distributed capacitances C _SG1 and C _SG2 between the fixed electrodes SP ₁ and SP ₂ and the case are the same as those between the terminals A and B and the ground. A distributed capacitance C _SG0 between the movable electrode MP and the case is interposed between the terminal C and the ground, while a first and second electrostatic capacitance is interposed between the terminals A-C and B-C. Distributed capacitance in parallel with capacitances C ₁ and C ₂
C _SP1 and C _SP2 exist.

FIG. 3 is a sectional view showing an example of a differential capacitance type sensor, in which fixed electrodes SP ₁ and SP ₂ supported by lead wires L are provided in a case F, and
A flexible movable electrode MP whose base is fixed by an insulating sealing material I such as glass is provided, and the movable electrode MP is deflected by a mechanical displacement force P applied to its tip. As a result, the first and second capacitances C ₁ and C ₂ configuring the differential capacitance type sensor vary differentially.

In this case, a constant capacitance is formed between the end Lt of the lead wire L and the base of the movable electrode MP, and this corresponds to the distributed capacitances C _SP1 and S _SP2 in Fig. 2. ing.

FIG. 4 is a block diagram showing a first embodiment of the "capacitive displacement converter" according to the earlier application, and terminals A to C of FIGS. 2 and 3 are connected to terminals A to C. First of all, distributed capacity
The operation will be explained while ignoring C _SP1 and C _SP2 .

That is, in the first and second gates G 2A and G _2B with inverted outputs whose outputs are respectively connected to the first and second capacitances C ₁ and C ₂ via terminals A and _B ,
When G _2A makes output A “H” and generates voltage +E, the first capacitance C ₁
and the distributed capacitance C _SG0 are charged in series, and the common connection point of the first and second capacitances C ₁ and C ₂ , that is, the terminal C
The voltage suddenly reaches a constant voltage and rises almost vertically as shown in FIG. 5B.

The _equivalent circuit for charging at this time is as shown in Figure 6, but since the output impedance of the first gate _G2A is extremely small, the existence of the distributed capacitance _CSG1 becomes irrelevant, and the The second capacitance C ₂ is inserted into the
The maximum voltage at terminal C is determined by the impedance ratio of the first capacitance C ₁ to the distributed capacitance C _SG0 and the second capacitance C ₂ .

Also, at this time, the output C of the inverter _G1 whose input is connected to the terminal C is "L", and the constant value current limiting circuit CC is connected between the input and output of the inverter _G1 , so the distribution The charges in the capacitor C _SG0 and the second capacitor C ₂ immediately start discharging via the constant value current limiting circuit CC and the output impedance of the inverter G ₁ , but this discharge current is reduced to a constant current by the constant value current limiting circuit CC. By being regulated to this value, the output B decreases linearly.

Note that at this time, the output A is still "H" (see Figure 5), and the charging current of the first capacitor _C1 also passes through the constant value current limiting circuit CC, so the current passing through the constant value current limiting circuit CC If you think about it,
The equivalent circuit at this time is as shown in FIG.

When the output B falls to the threshold level V _TH at which the output of the inverter G ₁ is inverted, the output C of the inverter G ₁ changes to “H”, thereby causing the output A of the first gate G _2A to become “L”. ”, the residual charges in the distributed capacitance C _SG0 and the second capacitance C ₂ are rapidly discharged through the first capacitance C ₁ , and after the output B drops vertically, the “H” of the output C ”, the distributed capacitance is increased by a constant current through the constant current limiter CC.
C _SG0 and the second capacitance C ₂ become charged, and the output B increases linearly.

When the output B reaches the threshold level _VTH , the output C of the inverter _G1 changes to "L" (see Figure 5), and the output A of the first gate _G2A becomes "H". Therefore, charging is performed again from the first gate _G2A , and the above operation is repeated.

On the other hand, the output C of the inverter _G1 is counted by the counter CT, and when a certain number of counts is performed, the count output n changes from "H" to "L".
In order to maintain this state until a certain number of counts are performed again, this signal is applied to the second gate _G2B via the inverter _G3 , thereby turning on the second gate _G2B and turning on the first gate G2B. _2A
is turned off, and the same charging and discharging as described above is performed repeatedly between terminals B and C. When the count output n turns to "H" again, the first gate G2A is turned on and the second gate _G2A is turned on. G _2B is turned off and terminal A-
Charging and discharging between C is performed.

Therefore, the first and second gates G _2A , G _2B
are turned on alternately, and along with this, terminals A-C
The charging/discharging operation between the two points and between B and C is repeated.

In this case, the first gate and the second gate selectively feed the in-phase output of the amplifying means to the first gate, the second gate, and the like through the feedback means.
A switching means connected to one end of the second capacitor is formed. Therefore, when a non-inverting amplifier is used as _G1 , the switching means formed by the first and second gates can be realized by a simple changeover switch circuit.

FIG. 8 is an example showing such a concept,
SW indicates a changeover switch controlled by the output of counter CT.

Here, the terminal voltage change e ₁ of the distributed capacitance C _SG0 with reference to the threshold level V _TH is the combined capacitance of the distributed capacitance C _SG0 and the second capacitance C ₂ from the relationship shown in Figure 6. Then, it is shown by the following equation.

e ₁ = C ₁ / C ₁ + Ct・E ...(1) Also, the terminal voltage change e ₁ is the threshold level
The time _t1 required for the voltage to decrease to V _TH is given by the following formula based on the relationship shown in Figure 7, where i is the discharge current of a constant value regulated by the constant value current limiting circuit CC. .

i・t ₁ = e ₁ (C ₁ +Ct) ...(2) Calculating t ₁ from equations (1) and (2), t ₁ = C ₁・E/i ...(3) Note that charging and discharging While this is repeated, a charge corresponding to the threshold level V _TH is determined as a reference potential in the distributed capacitance C _SG0 , and since charging and discharging are performed around this, the terminal voltage change e ₁ on the charging side The terminal voltage change _e2 on the discharging side is equal to the terminal voltage change e2, and by charging for ₂ minutes using the constant current i from the constant current limiter CC, the required charging time _t2 is also equal to _t1 . They are equal, and the following formula holds true.

t ₁ = t ₂ ...(4) These relationships are the same for charging and discharging between terminals B and C, and in this case, the first capacitance C ₁ and This results in a state in which the second capacitance C ₂ is exchanged, and equation (3) becomes the following equation.

_t1 = _C2・E/i...(5) Therefore, the "H" period of the pulse signal obtained from the count output n of the counter CT is applied to the first capacitance _C1 , and the "L" period is applied to the first capacitance. 2 corresponding to the electrostatic capacitance C ₂ , and by averaging this using an integrating circuit consisting of the resistor R ₃ and the capacitor C ₃ , the duty ratio of the pulse signal can be obtained, so C ₁ / (C ₁ + C ₂ )
This is the calculation result, which becomes the electrical signal as the conversion output Eo.

Figures 9 and 10 show distributed capacitances C _SP1 and C _SP2
This is an equivalent circuit similar to Figures 6 and 7 when considering the existence of .

e ₁ = (C ₁ +C _SP1 )E/C ₁ +C _SP1 +C _SG0 +
C ₂ +C _CP +C _CP・(-E)/C ₁ +C _SP1 +C _SG0 +C ₂ +C _CP …
…(6) i・t ₁ = e ₁ (C _CP +C _SP1 +C ₁ +C ₂ +C _SG0 )……(7) However, C _CP is the compensation capacitor connected in parallel with the constant current limiter circuit CC in Fig. 4. and
If this is set to the same capacitance value as the distributed capacitance C _SP1 , the compensation capacitor C _CP performs compensatory charging for the distributed capacitance C _SP1 in the charging state _shown in FIG. influence is eliminated.

Therefore, the following equation holds from equations (6) and (7).

t ₁ = (C ₁ + C _SP1 − C _CP ) E/i ...(8) Here, since C _SP1 = C _CP , equation (8) is, t ₁ = C ₁・E/i ...(9 ), and the same results as equations (3) and (5) are obtained.

Note that, due to the structure of the sensor, the relationship C _SP1 ≒ C _SP2 is obtained, so the purpose can be achieved using the same compensation capacitor C _CP .

In other words, the influence of distributed capacitances C _SG1 , C _SG2 , C _SG0 etc. is completely eliminated, and the compensation capacitor
By adding C _CP , the influence of distributed capacitances C _SP1 and C _SP2 can be eliminated, so the distributed capacitance can be reduced with a simple circuit configuration.
It is possible to obtain linear conversion characteristics without the influence of C _SG1 , C _SG2 , C _SG0 , C _SP1 , C _SP2, etc.

In the above embodiment, a single capacitance type sensor whose capacitance changes depending on the physical displacement to be detected is used as one of the first and second capacitances C ₁ and C ₂ , and the other capacitance is A similar objective can be achieved using a fixed reference capacitance.

Next, the "capacitive displacement converter" which is the earlier patent application.
A second example will be described. Figure 11 shows
4 is a circuit diagram showing the configuration of this second embodiment, and the integrating circuit including the differential capacitance sensor DS, resistors R _3A , R _3B and capacitors C _3A , C _3B is the same as that in FIG. 4, but with a fixed value. A specific circuit configuration is shown as the current limiting circuit CC.

In addition, the output of the integrating circuit is given to a two-wire output section OT mainly composed of differential amplifier A, and in differential amplifier A, the output voltage of the integrating circuit given to the inverting input and the resistor R ₄ , R ₅ and resistor
The difference with the reference voltage at the non-inverting input, set by potentiometer RV ₁ via R ₆ , is amplified and this output is used to connect the FET (field effect transistor)
Line terminal that controls Q ₇ and connects the 2-wire line
The current value between LT ₁ and LT ₂ is determined.

However, FET Q ₇ and constant voltage diode ZD
The current through the feedback potentiometer RV ₂
The resulting voltage is passed through resistor _R5 as negative feedback and is applied to the non-inverting input of differential amplifier A, so the voltage between both inputs of differential amplifier A becomes almost zero. , the current between the line terminals LT ₁ and LT ₂ is balanced, thereby stabilizing the current value between the line terminals LT ₁ and LT ₂ .

Note that the power supply voltage from the receiving section is applied to the line terminals LT ₁ and LT ₂ via a two-wire line.
This is stabilized by a constant voltage diode ZD and then supplied as the power supply voltage V _DD to each part.

In addition, the line current between line terminals LT ₁ and LT ₂ is within the change range 4 specified in the field of industrial measurement.
It is a unified signal of ~20 mA, and is adjusted by potentiometer RV ₁ so that the line current becomes a reference current of 4 mA in the balanced state of differential capacitance sensor DS, and the range of change is adjusted by potentiometer RV 1. ₂ , but since the voltage from each potentiometer RV ₁ and RV ₂ is applied to the differential amplifier A via the adding circuit made up of resistors R ₄ to _{R 6} , the difference between the reference current and the range of change is Coordination takes place without mutual interference.

The above are the details of the "capacitive displacement converter" which is the earlier application of the applicant of the present invention.

However, the above-mentioned "capacitive displacement converter" still has the following drawbacks. That is, the fourth
There is always a signal propagation delay in the gates G _2A and G _2B in the figure or in FIG. 11. For this reason,
When a distributed capacitance compensation capacitor C _CP is inserted,
Capacitors are connected prior to positive feedback of capacitances C ₁ and C ₂
Negative feedback is applied by _CCP , and as a result, distortion as shown in FIG. 12 occurs in the output of inverter _G1 . This phenomenon becomes a problem especially when the oscillation frequency is high.

This invention was made in order to eliminate the drawbacks of the earlier invention mentioned above, and is a capacitor for distributed capacitance compensation.
A delay means is inserted in series with _CCP , thereby eliminating distortion occurring in the output of inverter _G1 .

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 13 is a circuit diagram showing the main part of the present invention. In this diagram, the distributed capacitance compensation capacitor
A delay means D is inserted in series with C _CP , and the terminal Ta connected to the capacitor C _CP and the terminal Tb connected to the delay means D are set to constant current limits as shown in FIG. 4 or FIG. 11, respectively. Connected to both terminals of circuit CC. In this case, as the delay means D, for example, a resistor Ra and a capacitor shown in FIG.
A delay circuit made of Ca or a buffer amplifier A shown in FIG. 15 is used. Further, the delay time of this delay means D may be longer than the signal delay time caused by the gates G _2A and G _2B in FIG. 4 or FIG. 11. In the configuration shown in FIG. 8, inverter _G2 may be provided with a delay function.

As explained above, according to the present invention, the distributed capacitance compensating capacitor C _CP and the delay means D are connected in series, and this is connected in parallel to the constant value current limiting circuit _CC . The feedback does not precede the positive feedback due to the capacitances C ₁ and C ₂ , thereby making it possible to eliminate distortion occurring in the output of the inverter G ₁ .

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of a differential capacitance type sensor, Fig. 2 is an equivalent circuit of the sensor, Fig. 3 is a sectional view showing the specific configuration of the sensor, and Fig. 4 is a capacitance type sensor, which is the premise of this invention. Circuit diagram showing the configuration of the displacement converter, No. 5
The figure is a waveform diagram for explaining the operation of the same capacitive displacement converter, and Figures 6 and 7 are respectively when charging the distributed capacitance C _SG0 and electrostatic capacitance C ₁ and C ₂ in the same capacitive displacement converter. 8 is a circuit diagram showing another configuration example of the same capacitive displacement converter, and 9 is an equivalent circuit during discharge.
Figures 1 and 10 respectively show the sixth case when parallel distributed capacitance C _SP1 is considered in the same capacitive displacement converter.
11 is a circuit diagram showing the configuration of another capacitive displacement converter which is the premise of this invention, and FIG. 12 is a circuit diagram similar to that shown in FIG. 4 or 11.
Inverter in the capacitive displacement converter shown in the figure
_FIG. 13 is a circuit diagram showing the configuration of the main part of the capacitive displacement converter according to the present invention, and FIGS. 14 and 15 are specific examples of the delay means D in FIG. 12. FIG. 2 is a circuit diagram showing an example of the circuit. _C1 ...first capacitance, _C2 ...second capacitance,
G ₁ ...Inverter, CC...Constant current limit circuit,
C _CP ... Distributed capacitance compensation capacitor, D ... Delay means, CT ... Counter, G _2A ... First gate,
G _2B ... second gate, R ₃ , R _3A , R _3B ... resistance,
C ₃ , C _3A , C _3B ... Capacitor, OT ... Output section.

Claims (1)

[Claims] 1. First and second capacitances, at least one of which changes in response to a physical change to be detected, and one end of each of which is commonly connected, and the common connection point is connected to the input point thereof. a constant value current limiting circuit connected between the output of the amplifying means and the input point having an opposite phase to the signal at the input point; and a series connection connected in parallel with the constant value current limiting circuit. a distributed capacitance compensating capacitor and delay means, a counter for counting a fixed number of output signals of the amplifying means, and an output of the amplifying means that is in phase with the input point based on the count output of the counter, via a feedback means. and switching means selectively connected to the other ends of each of the first and second capacitances. 2. first and second capacitors, each of which changes slightly in response to a physical change to be detected, each of which has one end connected in common; and an amplification means with the common connection point connected to its input point. , a constant value current limiting circuit connected between the output of the amplifying means having an opposite phase to the signal at the input point and the input point, and a distributed capacitance compensation circuit connected in series with the constant value current limiting circuit and connected in parallel with the constant value current limiting circuit. a capacitor, a delay means, a counter for counting a fixed number of output signals of the amplifying means, and an output of the amplifying means that is in phase with the input point based on the count output of the counter, and feeding the output of the amplifying means that is in phase with the input point to the first
and a switching means selectively connected to the other end of each of the second capacitors, an integrating circuit for averaging pulse signals obtained from the count outputs of the counter, and an integrating circuit for connecting the output of the integrating circuit to a two-wire line. A capacitive displacement converter equipped with an output section that converts the current value into a current value.