JPS6356925B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a capacitive displacement converting device that converts physical displacement based on changes in physical quantities such as pressure and tension into electrical signals.

Such a displacement converter is used when detecting the flow rate or pressure of various processes using a capacitive sensor, converting it into an electrical signal, and transmitting the detection result to a remote receiving unit or the like. By the way, in commonly used capacitive sensors, there is a distributed capacitance as an invariant component that exists between the fixed electrode and the movable electrode, and a distributed capacitance that exists between the fixed electrode, the movable electrode, and the case. , these distributed capacitances cause a problem in which the conversion characteristics become non-linear.

Therefore, the applicant of the present invention first proposed a "capacitive displacement converter" (Japanese Patent Application No. 101699/1982) that can eliminate the influence of this distributed capacitance on the conversion characteristics.
has been applied for. Hereinafter, first, this "capacitive displacement converter" will be explained.

Figure 1 is a conceptual diagram of a differential capacitive sensor used in this "capacitive displacement transducer", in which a movable electrode MP provided between fixed electrodes SP ₁ and SP ₂ responds to the physical displacement to be detected. The first and second capacitances formed by fixed electrodes SP ₁ and SP ₂ move between fixed electrodes SP 1 and SP 2 according to the mechanical displacement caused by them.
C ₁ and C ₂ change differentially.

Figure 2 is an equivalent circuit of Figure 1 that takes into consideration the existence of distributed capacitance, and the distributed capacitances C _SG1 and C _SG2 between the fixed electrodes SP ₁ and SP ₂ and the case are the same as those between the terminals A and B and the ground. A distributed capacitance C _SG0 between the movable electrode MP and the case is interposed between the terminal C and the ground, while a first and second electrostatic capacitance is interposed between the terminals A-C and B-C. Distributed capacitance in parallel with capacitances C ₁ and C ₂
C _SP1 and C _SP2 exist.

FIG. 3 is a sectional view showing an example of a differential capacitance type sensor, in which fixed electrodes SP ₁ and SP ₂ supported by lead wires L are provided in a case F, and
A flexible movable electrode MP whose base is fixed by an insulating sealing material I such as glass is provided, and the movable electrode MP is deflected by a mechanical displacement force P applied to its tip. As a result, the first and second capacitances C ₁ and C ₂ configuring the differential capacitance type sensor vary differentially.

In this case, a constant capacitance is formed between the end Lt of the lead wire L and the base of the movable electrode MP, and this corresponds to the distributed capacitances C _SP1 and C _SP2 in Fig. 2. ing.

FIG. 4 is a block diagram showing a first embodiment of the "capacitive displacement converter" according to the earlier application, and terminals A to C of FIGS. 2 and 3 are connected to terminals A to C. First of all, distributed capacity
The operation will be explained while ignoring C _SP1 and C _SP2 .

That is, in the first and second gates G 2A and G _2B with inverted outputs whose outputs are respectively connected to the first and second capacitances C ₁ and C ₂ via terminals A and _B ,
When G _2A makes the output (A) “H” and generates voltage +E, the first capacitance C ₁
and distributed capacitance C _SG0 are charged in series, and the voltage at the common connection point of the first and second capacitances C ₁ and C ₂ , that is, the terminal C, suddenly reaches a constant voltage and becomes almost vertical as shown in Figure 5B. stand up.

The _equivalent circuit for charging at this time is as shown in Figure 6, but since the output impedance of the first gate _G2A is extremely small, the existence of the distributed capacitance _CSG1 becomes irrelevant, and the The second capacitance C ₂ is inserted into the
The maximum voltage at terminal C is determined by the impedance ratio of the first capacitance C ₁ to the distributed capacitance C _SG0 and the second capacitance C.

Also, at this time, the output (C) of the inverter _G1 whose input is connected to the terminal C is "L", and the constant current limiter circuit CC is connected between the input and output of the inverter _G1 . , the charges in the distributed capacitance C _SG0 and the second capacitance C ₂ immediately start discharging via the constant value current limiting circuit CC and the output impedance of the inverter G ₁ , but this discharge current is controlled by the constant value current limiting circuit CC. By regulating the current to a constant value, the output (B) decreases linearly.

At this time, the final output (A) is "H" (see Figure 5), and the charging current of the first capacitor _C1 also passes through the constant value current limiting circuit CC. If we focus on the current flowing through the
The equivalent circuit at this time is as shown in FIG.

When the output (B) drops to the threshold level V _TH at which the output of the inverter G ₁ is inverted, the output (C) of the inverter G ₁ changes to “H”, thereby causing the output of the first gate G _2A to change to “H”. (A) becomes “L”, so the residual charge in the distributed capacitance C _SG0 and the second capacitance C ₂ is rapidly discharged via the first capacitance C ₁ , and the output (B) decreases vertically. After that, due to “H” of the output (C), the distributed capacitance is increased by constant current through constant value current limiter circuit CC.
C _SG0 and the second capacitance C ₂ become charged, and the output (B) increases linearly.

When the output (B) reaches the threshold level _VTH , the output (C) of the inverter _G1 changes to "L" (see Figure 5), thereby causing the output of the first gate _G2A to
Since (A) becomes "H", charging from the first gate _G2A is performed again, and the above operation is repeated thereafter.

On the other hand, the output (C) of the inverter _G1 is counted by the counter CT, and when a certain number of counts is performed, the count output n changes from "H" to "L".
In order to maintain this state until a certain number of counts are performed again, this signal is applied to the second gate _G2B via the inverter _G3 , thereby turning on the second gate _G2B and turning on the first gate G2B. _2A
is turned off, and the same charging and discharging as described above is repeated between terminals B and C. When the count output n turns to "H" again, the first gate G2A turns on and the second gate _G2A turns on. G _2B turns off and terminal A-
Charging and discharging between C is performed.

Therefore, the first and second gates G _2A , G _2B
are turned on alternately, and along with this, terminals A-C
The charging/discharging operation between the two points and between B and C is repeated.

In this case, the first gate and the second gate selectively feed the in-phase output of the amplifying means to the first gate, the second gate, and the like through the feedback means.
A switching means connected to one end of the second capacitor is formed. Therefore, when a non-inverting amplifier is used as _G1 , the switching means formed by the first and second gates can be realized by a simple changeover switch circuit.

FIG. 8 is an example showing such a concept,
SW indicates a changeover switch controlled by the output of counter CT.

Here, the terminal voltage change e ₁ of the distributed capacitance C _SG0 with respect to the threshold level V _TH as a reference is the combined capacitance of the distributed capacitance C _SG0 and the second capacitance C ₂ from the relationship shown in Figure 6. Then, it is shown by the following equation.

e ₁ = C ₁ / C ₁ + Ct・E ...(1) Also, the terminal voltage change e ₁ is the threshold level
The time _t1 required for the voltage to decrease to V _TH is given by the following formula based on the relationship shown in Figure 7, where i is the discharge current of a constant value regulated by the constant value current limiting circuit CC. .

i・t ₁ = e ₁ (C ₁ +Ct) ...(2) Calculating t ₁ from equations (1) and (2), t ₁ = C ₁・E/i ...(3) In addition, charge/discharge While this is repeated, a charge corresponding to the threshold level V _TH is determined as a reference potential in the distributed capacitance C _SG0 , and since charging and discharging are performed around this, the terminal voltage change e ₁ on the charging side The terminal voltage change _e2 on the discharging side is equal to the terminal voltage change e2, and by charging for ₂ minutes using the constant current i from the constant current limiter CC, the required charging time _t2 is also equal to _t1 . They are equal, and the following formula holds true.

t ₁ = t ₂ ...(4) These relationships are the same in charging and discharging between terminals B and C, and in this case, the first capacitance C ₁ and This results in a state in which the second capacitance C ₂ is exchanged, and equation (3) becomes the following equation.

_t1 = _C2・E/i...(5) Therefore, the "H" period of the pulse signal obtained from the count output n of the counter CT is applied to the first capacitance _C1 , and the "L" period is applied to the first capacitance. 2 corresponding to the electrostatic capacitance C ₂ , and by averaging this using an integrating circuit consisting of the resistor R ₃ and the capacitor C ₃ , the duty ratio of the pulse signal can be obtained, so C ₁ / (C ₁ + C ₂ )
This is the calculation result, which becomes the electrical signal as the conversion output Eo.

Figures 9 and 10 show distributed capacitances C _SP1 and C _SP2
This is an equivalent circuit similar to Figures 6 and 7 when considering the existence of .

e=(C ₁ +C _SP1 )E/C ₁ +C _SP1 +C _SG0 +C ₂ +C _CP +C _CP・(−E)/C ₁ +C _SP1 +C _SG0 +C ₂ +C _CP ……(6) i・t ₁ =e ₁ (C _CP +C _SP1 +C ₁ +C ₂ +C _SG0 ) ...(7) However, C _CP is a compensation capacitor connected in parallel with the constant value current limiter CC in Fig. 4,
If this is set to the same capacitance value as the distributed capacitance C _SP1 , then in the charging state shown in Fig. 9, compensatory charging for the distributed capacitance C _SP1 is performed by the compensation capacitor C _CP , so the distributed capacitance C given to the output (C) is The effects of _SP1 are removed.

Therefore, the following equation holds from equations (6) and (7).

t ₁ = (C ₁ + C _SP1 − C _CP ) E/i ...(8) Here, since C _SP1 = C _CP , equation (8) is, t ₁ = C ₁・E/i ...(9 ), and the same results as equations (3) and (5) are obtained.

Note that, due to the structure of the sensor, the relationship C _SP1 ≒ C _SP2 is obtained, so the purpose can be achieved using the same compensation capacitor C _CP .

In other words, the influence of distributed capacitances C _SG1 , C _SG2 , C _SG0 etc. is completely eliminated, and the compensation capacitor
By adding C _CP , the influence of distributed capacitances C _SP1 and C _SP2 can be eliminated, so the distributed capacitance can be reduced with a simple circuit configuration.
It is possible to obtain linear conversion characteristics without the influence of C _SG1 , C _SG2 , C _SG0 , C _SP1 , C _SP2, etc.

The above are the details of the "capacitive displacement converter" which is the earlier application of the applicant of the present invention.

By the way, the above-mentioned "capacitive displacement converter" has the following drawbacks. That is, the fourth
In the figure, the time during which the output of the inverter _G1 is fed back to the input terminal of the inverter G1 via the parallel circuit of the compensation capacitor _CCP and the constant value current limiting circuit CC, and the time when the output of the inverter _G1 is fed back to the input terminal of the inverter _G2A or the second gate _G2B Since the time and feedback time to the input terminal of inverter _G1 via the capacitive sensors connected to terminals A, B, and C are different, distortion as shown in Figure 11 occurs in the output waveform of inverter _G1 . I end up. That is, when the input voltage of inverter _G1 reaches the threshold level, the output level of inverter G1 is inverted. Here, the voltage applied to the input terminal of the inverter _G1 is the voltage obtained by dividing the output voltage of the gate _G1 through the gate _G2A by the capacitor _C1 and the distributed capacitance _CSG0 , and the constant value current limiter CC. compensation capacitor
The voltage is superimposed with the voltage applied via the C _CP parallel circuit. This superposition is caused by inverter G ₁
This is done near the threshold level of .
There is no problem if these superimpositions occur at the same time, but if there is a slight time lag between them, the output switching at the threshold level will be disrupted, as shown in Figure 11. In response to voltage fluctuations near the threshold level of the input voltage of inverter _G1 , disturbances occur in the rectangular wave voltage appearing at the output terminal of inverter _G1 . Similarly, in the circuit shown in FIG. 8, if the time at which the output of the amplifier _G1 is fed back via the inverter _G2 etc. is different from the time at which the output is fed back via the changeover switch SW and the capacitive sensor, Amplifier G ₁
This may cause distortion in the output. Such distortion causes erroneous counting in the counter CT, which is extremely undesirable.

This invention was made to eliminate the drawbacks of the prior invention described above, and each output of the switching means (the first and second gates G _2A and G _2B in FIG. 4 or the changeover switch SW in FIG. 8) A device characterized in that a signal synthesizing means is provided, and a parallel circuit of a compensation capacitor and a constant current limiting circuit is inserted between the output terminal of the signal synthesizing means and the input terminal of an inverter (amplifier) _G1 . It is.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 12 is a circuit diagram showing the configuration of the capacitive displacement converter according to the present invention.
Components corresponding to those in the figure are given the same reference numerals. _The difference between the circuit shown in this figure and the circuit shown in _{FIG .} This Nand Gate G ₄
A parallel circuit consisting of a compensation capacitor _CCP and a constant current limiting circuit CC is inserted between the output terminal of the inverter G1 and the input terminal of the inverter _G1 . Here, the NAND gate G ₄ constitutes a signal synthesizing means for synthesizing each output of the first and second gates G _2A and G _2B .

In the circuit shown in Fig. 12, the counter
Assuming that the output of CT is at H (high) level, the output of gate _G3 is at L (low) level, so the output of second gate _G2B is at H level, and this H level is the output of NAND gate _G4 . The signal is supplied to the second input terminal. In this state, if the output of the inverter _G1 is at H level, the first gate _G2A
The output of NAND gate G4 becomes L level, and therefore the output of NAND gate _G4 becomes H level. Conversely, when the output of the inverter _G1 is at the L level, the output of the first gate _G2A is at the H level and the output of the NAND gate _G4 is at the L level. i.e. inverter G ₁
The output of and the output of NAND gate G ₄ always match,
Therefore, the circuit shown in FIG. 12 basically operates exactly the same as the circuit shown in FIG. 4. Note that the same applies when the output of the counter CT is at the L level.

Next, the operational differences between the circuit shown in FIG. 4 and the circuit shown in FIG. 12 will be described.

In the circuit shown in Fig. 4, a feedback signal is fed back to the input terminal of the inverter _G1 via a parallel circuit of a compensation capacitor _CCP and a constant value current limiting circuit CC, and a capacitive type connected to terminals A to C. A feedback signal fed back to the input end of the inverter _G1 via the sensor is superimposed near the threshold level of the inverter _G1 . Figure 13 is a diagram showing the input voltage waveform of inverter _G1 near the threshold level. As shown in this figure, small vibrations occur near the threshold level due to the above superposition, and this causes , distortion as shown in FIG. 11 occurs in the output of inverter _G1 .

On the other hand, in the circuit shown in FIG.
If the input signal of inverter _G1 is as shown in Figure 14A, the output of inverter _G1 is as shown in Figure 14B, and the output of the first gate _G2A (or second gate _G2B ) is as shown in Figure 14B. As shown in Figure D, the output of inverter _G1 is inverted and slightly delayed, and the output of NAND gate _G4 is the output of the first gate _G2A (or gate _G2B ) as shown in Figure D. is inverted and slightly delayed. As a result, the compensation capacitor
The signal fed back to the input terminal of inverter G ₁ through C _CP and constant value current limiter circuit CC is connected to gate G _2A
(or G _2B ) propagation delay and NAND gate
It is applied to the input terminal of inverter _G1 after being delayed by the total time of the transmission delay of _G4 . As a result, the signal fed back to the inverter _G1 via the compensation capacitor C _CP and constant value current limiter CC, and the signal fed back to the inverter G via the capacitive sensor are set to the threshold of the inverter _G1 . Superimposed on levels beyond levels. FIG. 15 is a diagram showing the input voltage waveform of inverter G ₁ near the threshold level, similar to FIG. 13. As shown in this figure, in the case of the circuit of FIG. The vibration occurs at a level above the threshold level, so this small vibration does not affect the output voltage of inverter _G1 , and the distortion shown in Figure 11 does not occur in the output voltage. .

Note that in the embodiment described above, the gate
Although NAND gates were used as G _2A , G _2B , G ₃ , and G ₄ , it is of course possible to use other logic elements. FIG. 16 shows a case where NOR gates are used for these gates. In addition, in the embodiment described above, the input signal of the counter CT is
It may also be obtained from the output end of _G4 .

An embodiment in which the present invention is applied to the circuit shown in FIG. 4 has been described above, but the present invention can of course also be applied to the circuit shown in FIG. 8.

Note that in the circuit shown in Figure 8, the inverter
It is also possible to provide delay characteristics to G ₂ so as to obtain the same effect as the present invention, but in this case, considering the product deviation of the delay characteristics of each component, the configuration according to the present invention may not be possible. This method can delay the signal more reliably and can be said to be better.

As explained above, according to the present invention, a signal synthesizing means for synthesizing each output of the switching means (gates G _2A and G _2B in FIG. 4) is provided, and the output terminal of this signal synthesizing stage and the amplifying means (inverter Since the third capacitance and constant value current limiting circuit are inserted between the input terminal of G ₁ ), it is possible to prevent distortion from occurring at the output terminal of the amplifying means.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of a differential capacitance type sensor, Fig. 2 is an equivalent circuit of the sensor, Fig. 3 is a sectional view showing the specific configuration of the sensor, and Fig. 4 is a capacitance type sensor, which is the premise of this invention. Circuit diagram showing the configuration of the displacement converter, No. 5
The figure is a waveform diagram for explaining the operation of the same capacitive displacement converter, and Figures 6 and 7 are respectively when charging the distributed capacitance C _SG0 and electrostatic capacitance C ₁ and C ₂ in the same capacitive displacement converter. 8 is a circuit diagram showing another configuration example of the same capacitive displacement converter, and 9 is an equivalent circuit during discharge.
Figures 1 and 10 respectively show the sixth case when parallel distributed capacitance C _SP1 is considered in the same capacitive displacement converter.
The equivalent circuit similar to Fig. 7 and Fig. 7, Fig. 11 is
Fig. 4 or Fig. 8 is a diagram showing the distortion occurring in the output of the inverter (amplifier) _G1 in the capacitive displacement converter shown in Fig. 8, Fig. 12 is a circuit diagram showing the configuration of an embodiment of the present invention, Fig. 13 are waveform diagrams for explaining the operation of the circuit shown in FIG. 4, FIG.
5 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 12, and FIG. 16 is a circuit diagram showing the configuration of another embodiment of the present invention. _C1 ...first capacitance, _C2 ...second capacitance,
G ₁ ... Inverter (amplification means), CC ... Constant value current limiting circuit, C _CP ... Distributed capacitance compensation capacitor (third capacitance), CT ... Counter, G _2A ...
First gate (switching means), G _2B ... second gate (switching means), G ₄ ... NAND gate (signal combining means).

Claims (1)

[Claims] 1 first and second capacitances, at least one of which changes in response to a change in a physical quantity to be detected, each of which has one end connected in common; and an amplification means with the common connection point connected to its input end. , a switching means for switching the output of the amplifying means and supplying it to the other ends of each of the first and second capacitances, a signal synthesizing means for synthesizing each output of the switching means, and a signal synthesizing means for synthesizing each output of the switching means; A constant value current limiting circuit inserted in parallel between the output terminal and the input terminal of the amplifying means, a third capacitor for compensating stray capacitance, and counting the output of the amplifying means or the output of the signal synthesizing means. 1. A capacitive displacement converting device, comprising: a counter, the switching means being controlled based on the output of the counter.