WO2010131640A1 - Electrostatic capacitance detection circuit - Google Patents

Electrostatic capacitance detection circuit Download PDF

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Publication number
WO2010131640A1
WO2010131640A1 PCT/JP2010/057937 JP2010057937W WO2010131640A1 WO 2010131640 A1 WO2010131640 A1 WO 2010131640A1 JP 2010057937 W JP2010057937 W JP 2010057937W WO 2010131640 A1 WO2010131640 A1 WO 2010131640A1
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Prior art keywords
capacitor
terminal
detected
capacitors
wiring
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PCT/JP2010/057937
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French (fr)
Japanese (ja)
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達巳 藤由
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アルプス電気株式会社
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Publication of WO2010131640A1 publication Critical patent/WO2010131640A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance

Definitions

  • the present invention relates to a capacitance detection circuit that detects a differential capacitance value in a capacitance sensor including a pair of capacitance elements.
  • FIG. 9 is a configuration diagram of a capacitance detection circuit described in Patent Document 1.
  • One ends of the detected capacitor 11 and the reference capacitor 12 are connected in common, and the common connection terminal is connected to the inverting input terminal ( ⁇ ) of the operational amplifier 15.
  • the constant voltage source 16 is connected to the non-inverting input terminal (+) of the operational amplifier 15, the output terminal of the operational amplifier 15 is connected to the inverting input terminal via the integration capacitor 13, and the switch is connected in parallel to the integration capacitor 13. 14 is connected.
  • the capacitance detection circuit by driving the detected capacitor 11 and the reference capacitor 12 with pulses of opposite phases, charges corresponding to these capacitance differences are taken out from the common connection terminal. At that time, since the reference voltage (fixed potential) is input to the Vin + from the constant voltage source 16, the output of the operational amplifier 15 is integrated with the integrating capacitor 13 so that the inverting input terminal of Vin ⁇ and the non-inverting input terminal of Vin + have the same voltage. Is fed back through.
  • the detected capacitor 11 and the reference capacitor 12 connected to the inverting input terminal of the operational amplifier depend on the type of sensor, a capacitance of the order of pF or less is detected in a MEMS sensor or an electrostatic touch panel, and the resolution is as follows. The fF order or less is required.
  • the electrostatic coupling of the operational amplifier inverting input terminal with the noise source may be in the order of pF in terms of level, and degradation of the S / N ratio due to noise mixing becomes a serious problem.
  • a shield with a conductor can be considered as a countermeasure against noise mixing into the inverting input terminal of the operational amplifier.
  • a shield with a conductor can be considered as a countermeasure against noise mixing into the inverting input terminal of the operational amplifier.
  • the present invention has been made in view of such a point, and an object thereof is to provide a capacitance detection circuit that is excellent in noise resistance, can suppress current consumption, and can efficiently secure a dynamic range of a signal.
  • one end is connected to the first and second detected capacitors to which one terminal to which a driving pulse is applied is commonly connected, and the other terminal of the first detected capacitor.
  • a fully differential amplifier that detects charges moving on the first and second wirings in response to a capacitance difference generated between two detected capacitors and outputs the detected charge amount in the form of a differential voltage from an output terminal.
  • a common mode feedback circuit that detects the common-mode voltage of the first and second wirings and feeds back the output voltage that makes the detected common-mode voltage equal to the reference potential to the first and second wirings. It is characterized by that.
  • the common mode feedback circuit detects the common-mode voltage of the first and second wirings, and feeds back the output voltage that makes the detected common-mode voltage equal to the reference potential to the first and second wirings. Therefore, even if the first and second detected capacitors are driven by the drive pulse, the common-mode voltage of the first and second wirings is fixed to the reference potential, so that the parasitic capacitances of the first and second wirings Can be prevented from charging. As a result, only the electric charge corresponding to the capacitance difference between the first and second detected capacitors is transferred to the fully differential amplifier and differentially amplified. Improvement and low power consumption can be achieved.
  • the fully differential amplifier since the fully differential amplifier is used to detect the capacitance difference between the first and second detected capacitors, the common mode noise in the input stage of the fully differential amplifier can be canceled and removed. Common mode noise superimposed on the output stage side of the amplifier can be easily canceled.
  • the common mode feedback circuit includes a first input capacitor having one terminal connected to the first wiring, and a first input capacitor having one terminal connected to the second wiring.
  • a common connection point between the second input capacitor having the same capacity and the other terminals of the first and second input capacitors is connected to the inverting input terminal, and a reference voltage is applied to the non-inverting input terminal, whereby the first and second input capacitors are connected.
  • a single output differential amplifier that outputs an output voltage fed back to the wiring.
  • the intermediate potential of the first and second wirings appears at the common connection point on the differential amplifier side of the first and second input capacitors so that the intermediate amplifier and the reference voltage are equal to each other.
  • the first and second wirings are not affected by the parasitic capacitance formed in the first and second wirings. Only the electric charge corresponding to the capacitance difference between the first and second detected capacitors can be transferred to the fully differential amplifier. Further, by using a single output differential amplifier, the circuit can be reduced in size as compared with a differential amplifier having a plurality of outputs.
  • the common mode feedback circuit includes a first output capacitor having one terminal connected to the output terminal of the differential amplifier and the other terminal connected to the first wiring, and one terminal connected to the difference.
  • a second output capacitor connected to the output terminal of the dynamic amplifier and having the other terminal connected to the second wiring and having a capacity equal to that of the first output capacitor; the first and second input capacitors; and the first And a plurality of switches that are provided in parallel with the second output capacitor and close one end immediately before applying a drive pulse to the first and second detected capacitors to reset the corresponding capacitors, respectively. It is also good.
  • the switch provided in parallel with the first and second input capacitors and the first and second output capacitors is connected to the first and second detected capacitors immediately before applying a drive pulse. Closed and each corresponding capacitor can be reset, allowing high-precision common mode feedback.
  • the first wiring is connected to one differential input terminal of the fully differential amplifier
  • the second wiring is connected to the other differential input terminal of the fully differential amplifier.
  • One path and a second path connecting the first wiring to the other differential input terminal of the fully-differential amplifier and connecting the second wiring to one differential input terminal of the fully-differential amplifier
  • the fully-differential amplifier is provided in each feedback path that feeds back a differential voltage from the output terminal to a differential input terminal having a different polarity.
  • An integration capacitor for accumulating a corresponding amount of charge, and a reset switch provided in parallel with each of the integration capacitors. The path switch selects the first path at the rising edge of the drive pulse.
  • the path is switched so that the second path is selected at the fall of the drive pulse, and the fully differential amplifier accumulates electric charge in the integration capacitor at both the rise and fall of the drive pulse, and the number of integrations
  • the reset switch is closed to reset the integrating capacitor.
  • the path changeover switch selects the first path at the rising edge of the driving pulse, selects the second path at the falling edge of the driving pulse, and charges the integration capacitor at both the rising and falling edges of the driving pulse. Therefore, the integration operation can be repeated continuously until a necessary signal level is obtained.
  • the present invention may also include a common mode capacitor array connected to the first and second wirings and canceling the common mode component of the first and second detected capacitors.
  • the common mode capacitor array since the common mode capacitor array is provided, the common mode components of the first and second detected capacitors can be canceled out, and the first and second power supply voltages of the differential amplifier of the common mode feedback circuit are not increased.
  • the capacity of the input capacitor 2 can be reduced, and the circuit scale and power consumption can be reduced.
  • the common mode capacitor array may include a capacitor group including a plurality of capacitors each having one terminal connected to the first or second wiring, and the other terminal of each capacitor constituting the capacitor group.
  • a switch group including a plurality of switches connected to each other, and using the switch group, a plurality of capacitors having a canceling capacity corresponding to a common mode component of the first and second detected capacitors are selected, and the driving An inversion pulse obtained by inverting the pulse can be applied to the other terminal of the capacitor group via the switch group.
  • the present invention it is possible to realize a capacitance detection circuit that is excellent in noise resistance, can suppress current consumption, and can efficiently secure a dynamic range of signals.
  • FIG. 4A is a waveform diagram of a drive pulse applied to the detected capacitance of FIG. 4
  • FIG. 4B is a voltage waveform diagram when there is no input common mode feedback circuit
  • FIG. 4C is a voltage waveform diagram when there is an input common mode feedback circuit. It is. It is a timing chart for demonstrating the flow of operation
  • FIG. 1 is a configuration diagram of a capacitance detection circuit according to an embodiment of the present invention.
  • the drive pulse DRV supplied from the drive signal source 41 serves as one terminal of the detected capacitor 42 and the detected capacitor (or reference capacitor) 43 constituting the capacitance sensor. Applied to the electrodes.
  • One detected capacitor 42 has the other electrode connected to a differential input terminal (a positive terminal in the case of a straight path to be described later) of the fully differential amplifier 49 via the wiring 60-1, and the other detected capacitor 43 Similarly, the other electrode is connected to the other differential input terminal (negative terminal in the case of a straight path) of the fully differential amplifier 49 via the wiring 60-2.
  • An input common mode cancellation capacitor array 44 and an input common mode feedback circuit 45 are connected to the wirings 60-1 and 60-2.
  • a path changeover switch 46 is provided in the wirings 60-1 and 60-2. The path changeover switch 46 connects the electrode of the detected capacitor 42 to the differential input terminal (positive side) of the fully-differential amplifier 49 via the wiring 60-1, and connects the electrode of the detected capacitor 43 to the wiring 60-2.
  • the straight path connected to the differential input terminal (negative side) of the fully-differential amplifier 49 via the wire and the electrode of the capacitor 42 to be detected are connected to the differential input terminal (negative-side) of the fully-differential amplifier 49 via the wiring 60-1.
  • the switch ⁇ 1 is closed and the switch ⁇ 2 is opened, and in the cross path, the switch ⁇ 1 is opened and the switch ⁇ 2 is closed.
  • the fully differential amplifier 49 has a negative output terminal and a positive output terminal so that the difference between the input Vin + and Vin ⁇ input to the positive differential input terminal and the negative differential input terminal is zero.
  • the differential output (Vout ⁇ , Vout +) is controlled.
  • a reset switch 47a and an integrating capacitor 48a are connected in parallel between the negative output terminal and the positive differential input terminal of the fully differential amplifier 49, and between the positive output terminal and the negative differential input terminal.
  • the reset switch 47b and the integrating capacitor 48b are connected in parallel.
  • FIG. 2 is a configuration diagram of the input common mode canceling capacitor array 44.
  • the input common mode cancellation capacitor array 44 includes a capacitor group 51 composed of a plurality of capacitors arranged in parallel and a switch group composed of a plurality of switches provided for the individual capacitors constituting the capacitor group 51. 52.
  • the capacitor group 51 includes a first capacitor group 51a in which each capacitor is connected to one wiring 60-1, and a second capacitor group 51b in which each capacitor is connected to the other wiring 60-2. It consists of
  • the switch group 52 is configured to be on / off controlled by selector signals SEL-C0... Individually applied to individual switches.
  • the capacitors 51a and 51b are set to have the same capacitance.
  • a reverse-phase pulse obtained by inverting the drive pulse is applied to the capacitor via a switch selected (on-controlled) by the selector signal SEL-C0.
  • the same charge amount corresponding to the number of selection switches (capacitors) can be canceled.
  • FIG. 3 is a block diagram of the input common mode feedback circuit 45.
  • the input common mode feedback circuit 45 is connected to the wirings 60-1 and 60-2 and connected to the wirings 60-1 and 60-2.
  • Common mode input capacitors 67 and 68 set to values and a single output differential amplifier 69 are provided.
  • the common mode input capacitors 67 and 68 have one electrode connected to the corresponding wiring 60-1 and 60-2, respectively, and the other electrode connected in common is connected to the inverting input terminal of the differential amplifier 69. Further, switches 63 and 64 are connected in parallel to the two common mode input capacitors 67 and 68.
  • the reference voltage Vref is applied to the non-inverting input terminal of the differential amplifier 69.
  • An intermediate potential between the wiring 60-1 and the wiring 60-2 appears at the common connection point on the other electrode side of the common mode input capacitors 67 and 68. Therefore, the differential amplifier 69 outputs a differential amplification signal that fixes the intermediate potential between the wiring 60-1 and the wiring 60-2 to the reference voltage Vref.
  • the common mode output capacitors 65 and 66 have one electrode connected in common, and the output terminal of the differential amplifier 69 is connected to the common connection point.
  • the other electrodes of the common mode output capacitors 65 and 66 are connected to corresponding wirings 60-1 and 60-2, respectively.
  • Switches 61 and 62 are connected in parallel to the common mode output capacitors 65 and 66, respectively.
  • a drive pulse is applied from the drive signal source 41 to one electrode of the commonly connected detected capacitors 42 and 43, and the detected signal is detected between the wirings 60-1 and 60-2 at the change point (rising / falling) of the driving pulse.
  • a potential difference corresponding to the capacitance difference between the capacitors 42 and 43 is generated.
  • the electric charge corresponding to the capacitance difference between the detected capacitors 42 and 43 generated between the wirings 60-1 and 60-2 moves to the fully-differential amplifier 49 via the path switching switch 46 through a straight path or a cross path. Are accumulated in the integrating capacitors 48a and 48b.
  • the fully differential amplifier 49 repeats the reset operation and the integration operation by the integrating capacitors 48a and 48b and the reset switches 47a and 47b, and outputs a differential voltage (Vout ⁇ , Vout +) corresponding to the capacitance difference of the detected capacitance.
  • the common mode component canceling operation is performed by the input common mode feedback circuit 45 in the process in which the electric charge according to the capacitance difference between the detected capacitors 42 and 43 is transferred to the integrating capacitors 48a and 48b.
  • the operation principle of the input common mode feedback circuit 45 will be described. First, in order to explain the relationship between the charging voltage of the capacitors 42 and 43 to be detected and the voltage waveform of the wirings 60-1 and 60-2, a circuit model without the fully differential amplifier 49 as shown in FIG. 4 (no feedback) Is assumed.
  • the detected capacitors 105 and 106 shown in FIG. 4 correspond to the detected capacitors 42 and 43 shown in FIG. 1, and the wirings 102 and 103 correspond to the wirings 60-1 and 60-2, respectively.
  • the detected capacitors 105 and 106 are detected at the rising edge of the drive pulse 104. Is charged, and voltage waveforms corresponding to the charged potentials of the detected capacitors 105 and 106 appear on the wirings 102 and 103.
  • the potential difference Va between the detected capacitor 105 and the detected capacitor 106 is detected by the fully differential amplifier 49.
  • the parasitic capacitance 101 always exists in the wirings 102 and 103.
  • the parasitic capacitance 101 of the wirings 102 and 103 is charged according to the potential change Vb generated in each of the wirings 102 and 103.
  • the phenomenon that the parasitic capacitance 101 of the wirings 102 and 103 is charged by the potential change Vb acts in the direction of decreasing the potential difference Va that is a sensing target, and means that the sensitivity as a sensor is lowered. Since the phenomenon in which the parasitic capacitance 101 is charged results in a potential change Vb in the wirings 102 and 103, the present embodiment changes the intermediate potential between the wiring 102 and the wiring 103 to the reference voltage Vref by the input common mode feedback circuit 45. By fixing, charging of the parasitic capacitance 101 at the rising edge (and falling edge) of the driving pulse is prevented.
  • FIG. 5 (c) shows voltage waveforms of the wirings 102 and 103 at the time of driving pulse rise when the input common mode feedback circuit 45 is operated in the circuit model shown in FIG. Since the input common mode feedback circuit 45 performs feedback control so that the intermediate potential between the wiring 102 and the wiring 103 is fixed to the reference voltage Vref, the potential difference Va ′ between the detected capacitor 105 and the detected capacitor 106 is applied to the wirings 102 and 103. However, a potential change (Vb) that charges the parasitic capacitance 101 does not occur in the wirings 102 and 103. Therefore, it is possible to cancel only the input common mode component from the wirings 102 and 103 and transfer only the charge corresponding to the potential difference Va ′ between the detected capacitor 105 and the detected capacitor 106 to the fully differential amplifier 49.
  • Vb potential change
  • the switches ⁇ 1 and ⁇ 2 are complementarily turned on / off at the rise and fall of the drive pulse output from the drive signal source 41.
  • the path switch 46 is a straight path ( ⁇ 1 on), and when ⁇ 2 is High (closed), it is a cross path ( ⁇ 2 on).
  • the RST-C signal rises at the timing T1 in FIG. 6, the switches 47a and 47b provided in the integration capacitors 48a and 48b are closed, and the charges of the integration capacitors 48a and 48b are closed.
  • RST-I rises, whereby all the switches 61 to 64 of the input common mode feedback circuit 45 are closed, and the differential amplifier 69 has a voltage follower configuration. Accordingly, the wirings 60-1 and 60-2 connecting the detected capacitors 42 and 43 and the fully differential amplifier 49 are set to the reference voltage Vref, and the common mode output capacitors 65 and 66 and the common mode input capacitors 67 and 68 are connected to each other. The charge is reset.
  • the detected capacitors 42 and 43 are driven with the rising waveform of the drive pulse.
  • the input common mode feedback circuit 45 detects the common-mode voltage of the wirings 60-1 and 60-2. Specifically, an intermediate potential of the wirings 60-1 and 60-2 detected by the common mode input capacitors 67 and 68 configured with equal capacity is applied to the inverting input terminal of the differential amplifier 69.
  • the differential amplifier 69 amplifies and outputs the difference between the reference voltage Vref and the inverting input terminal input (intermediate potential). The output voltage at this time is fed back to the wirings 60-1 and 60-2 via the common mode output capacitors 65 and 66, but the common mode output capacitors 65 and 66 are configured with equal capacity.
  • a common-mode voltage of the voltages of the wirings 60-1 and 60-2 is given.
  • the common-mode voltage of the wirings 60-1 and 60-2 for transmitting signals output from the detected capacitors 42 and 43 (sensor capacitors) is operated to keep the reference voltage Vref.
  • the fully differential amplifier 49 includes integrating capacitors 48a and 48b from the outputs of the negative output terminal and the positive output terminal so that the voltage difference between the positive differential input terminal and the negative differential input terminal is zero. To perform feedback operation. As a result, the fully differential amplifier 49 outputs a voltage corresponding to the capacitance difference between the detected capacitors 42 and 43.
  • the voltage output at this time is defined as: ⁇ C is the capacitance difference between the detected capacitors 42 and 43, Ci is the integration capacitance, and Vi is the peak value of the drive pulse.
  • Vout + ⁇ Vout ⁇ ⁇ C ⁇ Vi / Ci It becomes.
  • the level of the output voltage can be set by appropriately determining the size of the integration capacitor Ci.
  • FIG. 7 shows a voltage output waveform of the fully differential amplifier 49.
  • the difference between the detected capacitors 42 and 43 is added to the integration capacitor 48 of the fully differential amplifier 49 by the number of integrations, and the positive side output Vout + and the negative side output Vut ⁇ increase stepwise with the reference voltage Vref as the center. .
  • the fully differential amplifier 49 can input and amplify only the amount of charge corresponding to the difference between the detected capacitors 42 and 43, so that it is not necessary to pass a wasteful bias current, and the S / N is improved.
  • the common mode output capacitors 65 and 66 of the input common mode feedback circuit 45 are provided to output the output voltage of the differential amplifier 69 to the wirings 60-1 and 60-2.
  • the capacitance is reduced, it is necessary to increase the output amplitude by supplying a large power supply voltage to the differential amplifier 69 that operates so as to eliminate the difference between the intermediate potential between the wiring 60-1 and the wiring 60-2 and the reference voltage Vref. There is.
  • the capacitances of the common mode output capacitors 65 and 66 it is necessary to increase the capacitances of the common mode output capacitors 65 and 66. Therefore, it is necessary to increase the capacitance area. An increase in the area of the common mode output capacitors 65 and 66 is also undesirable because it reduces the mounting area.
  • the common-mode charge amount is canceled by applying an inversion pulse having a phase opposite to that of the drive pulse to the capacitors connected to the wirings 60-1 and 60-2 by the input common-mode capacitance array 44. .
  • capacitor groups 51a and 51b are configured such that the electrodes on the wiring side of the capacitors are connected to the wirings 60-1 and 60-2 corresponding to the detected capacitors 42 and 43, respectively.
  • the electrode is connected to an inversion pulse supply terminal having a phase opposite to that of the drive pulse through the switch group 52.
  • Each capacitor takes an appropriate value or a weighted size, and a switch group is set by the SEL-C signal so that it becomes an average value of the detected capacitors 42 and 43.
  • the charge amount corresponding to the common mode of the detected capacitors 42 and 43 can be offset by the charge amount of the capacitor groups 51a and 51b from the charge amount of the common mode of the detected capacitors 42 and 43.
  • the size of the common mode output capacitors 65 and 66 of the input common mode feedback circuit 45 can be reduced, and the driving capability of the differential amplifier 69 can be suppressed, so that the circuit scale and power consumption can be reduced.
  • Fig. 8 shows a modification of the input common mode feedback circuit.
  • the operation of this input common mode feedback circuit is basically the same as that of the input common mode feedback circuit 45 shown in FIG. 3 except that an operational transconductance amplifier (OTA) 70 is used instead of the differential amplifier 69. ing.
  • OTA operational transconductance amplifier
  • the common mode output capacitors 65 and 66 shown in FIG. 3 can be omitted by providing two outputs to the operational transconductance amplifier 70, each of which has the same current output.

Abstract

Provided is an electrostatic capacitance detection circuit which excels in noise resistance characteristics, is capable of restricting consumption current, and is capable of efficiently ensuring dynamic ranges for signals. This electrostatic capacitance detection circuit is equipped with the following: a first detected capacitance (42) and a second detected capacitance (43) to each of which is jointly connected one terminal subjected to impression of drive pulses; a first wire (60-1) one end of which is connected to the other terminal for the aforementioned first detected capacitance (42); a second wire (60-2) one end of which is connected to the other terminal for the aforementioned second detected capacitance (43); a totally differential amplifier (49) wherein electric charges moving on the aforementioned first and second wires (60-1) and (60-2) corresponding to the capacitance difference generated in the aforementioned first and second detected capacitances (42) and (43) are detected and are output in a differential voltage form; and a common mode feedback circuit (45) wherein output voltages by which common mode voltages in the aforementioned first and second wires (60-1) and (60-2) are made equal to the reference voltage are fed back to the first and second wires.

Description

静電容量検出回路Capacitance detection circuit
　本発明は、一対の容量素子を備える容量センサにおける差分容量値を検出する静電容量検出回路に関する。 The present invention relates to a capacitance detection circuit that detects a differential capacitance value in a capacitance sensor including a pair of capacitance elements.
　従来、センサ容量（容量素子）がハーフブリッジで構成された容量センサの容量変化をシングルエンド型の差動増幅器で検出する静電容量検出回路がある（例えば、特許文献１参照）。図９は特許文献１に記載された静電容量検出回路の構成図である。被検出容量１１と参照容量１２の一端同士を共通接続し、共通接続端子をオペアンプ１５の反転入力端子（－）に接続している。オペアンプ１５の非反転入力端子（＋）に定電圧源１６を接続し、オペアンプ１５の出力端子を反転入力端子に対して積分コンデンサ１３を介して接続すると共に、積分コンデンサ１３に対して並列にスイッチ１４を接続している。 2. Description of the Related Art Conventionally, there is a capacitance detection circuit that detects a change in capacitance of a capacitance sensor in which a sensor capacitance (capacitance element) is a half bridge using a single-ended differential amplifier (for example, see Patent Document 1). FIG. 9 is a configuration diagram of a capacitance detection circuit described in Patent Document 1. In FIG. One ends of the detected capacitor 11 and the reference capacitor 12 are connected in common, and the common connection terminal is connected to the inverting input terminal (−) of the operational amplifier 15. The constant voltage source 16 is connected to the non-inverting input terminal (+) of the operational amplifier 15, the output terminal of the operational amplifier 15 is connected to the inverting input terminal via the integration capacitor 13, and the switch is connected in parallel to the integration capacitor 13. 14 is connected.
　上記静電容量検出回路において、被検出容量１１と参照容量１２をそれぞれ逆相のパルスで駆動することにより、共通接続端子からこれらの容量差に対応する電荷が取り出される。その時、Ｖｉｎ＋は定電圧源１６から参照電圧（固定電位）が入力されるので、Ｖｉｎ－の反転入力端子とＶｉｎ＋の非反転入力端子とが同電圧になるようにオペアンプ１５の出力が積分コンデンサ１３を介してフィードバックされる。 In the capacitance detection circuit, by driving the detected capacitor 11 and the reference capacitor 12 with pulses of opposite phases, charges corresponding to these capacitance differences are taken out from the common connection terminal. At that time, since the reference voltage (fixed potential) is input to the Vin + from the constant voltage source 16, the output of the operational amplifier 15 is integrated with the integrating capacitor 13 so that the inverting input terminal of Vin− and the non-inverting input terminal of Vin + have the same voltage. Is fed back through.
特開平８－１４５７１７号公報JP-A-8-145717
　ところが、上記した従来の静電容量検出回路は、当該回路が搭載される同じＩＣ内にあるロジック回路部分からのノイズやＩＣ外に存在する輻射ノイズが、オペアンプ１５の反転入力（Ｖｉｎ－）に混入した場合、Ｓ／Ｎ比が劣化する問題があった。 However, in the above-described conventional capacitance detection circuit, noise from the logic circuit portion in the same IC on which the circuit is mounted or radiation noise existing outside the IC is applied to the inverting input (Vin−) of the operational amplifier 15. When mixed, there is a problem that the S / N ratio deteriorates.
　オペアンプの反転入力端子に接続される被検出容量１１および参照容量１２はセンサの種類にもよるがＭＥＭＳセンサや静電タッチパネルなどではｐＦオーダー以下の大きさの容量を検出対象としており、分解能としてはｆＦオーダー以下が必要となっている。また、オペアンプの反転入力端子に対するノイズ源との静電結合もレベル的にはｐＦオーダーとなることがあり、ノイズ混入によるＳ／Ｎ比の劣化が大きな問題となる。 Although the detected capacitor 11 and the reference capacitor 12 connected to the inverting input terminal of the operational amplifier depend on the type of sensor, a capacitance of the order of pF or less is detected in a MEMS sensor or an electrostatic touch panel, and the resolution is as follows. The fF order or less is required. In addition, the electrostatic coupling of the operational amplifier inverting input terminal with the noise source may be in the order of pF in terms of level, and degradation of the S / N ratio due to noise mixing becomes a serious problem.
　なお、図９の構成ではオペアンプの反転入力端子へのノイズ混入に対する対策として導体によるシールドなどが考えられるが、コスト、スペースの増加となってしまう問題が生じる。 In the configuration of FIG. 9, a shield with a conductor can be considered as a countermeasure against noise mixing into the inverting input terminal of the operational amplifier. However, there arises a problem that the cost and space increase.
　本発明は、かかる点に鑑みてなされたものであり、ノイズ耐性に優れ、消費電流を抑制可能で、信号のダイナミックレンジを効率よく確保できる静電容量検出回路を提供することを目的とする。 The present invention has been made in view of such a point, and an object thereof is to provide a capacitance detection circuit that is excellent in noise resistance, can suppress current consumption, and can efficiently secure a dynamic range of a signal.
　本発明の静電容量検出回路は、駆動パルスが印加される一方端子が共通接続された第１及び第２の被検出容量と、前記第１の被検出容量の他方端子に一端が接続された第１の配線と、前記第２の被検出容量の他方端子に一端が接続された第２の配線と、前記第１及び第２の配線が差動入力端子に接続され、前記第１及び第２の被検出容量に生じた容量差に対応して前記第１及び第２の配線上を移動する電荷を検出し、検出した電荷量を出力端子から差動電圧形式で出力する全差動増幅器と、前記第１及び第２の配線の同相電圧を検出し、検出した同相電圧と基準電位とを等しくする出力電圧を、当該第１及び第２の配線へフィードバックするコモンモードフィードバック回路とを具備したことを特徴とする。 In the capacitance detection circuit of the present invention, one end is connected to the first and second detected capacitors to which one terminal to which a driving pulse is applied is commonly connected, and the other terminal of the first detected capacitor. A first wiring; a second wiring having one end connected to the other terminal of the second detected capacitor; and the first and second wirings connected to a differential input terminal; A fully differential amplifier that detects charges moving on the first and second wirings in response to a capacitance difference generated between two detected capacitors and outputs the detected charge amount in the form of a differential voltage from an output terminal. And a common mode feedback circuit that detects the common-mode voltage of the first and second wirings and feeds back the output voltage that makes the detected common-mode voltage equal to the reference potential to the first and second wirings. It is characterized by that.
　この構成によれば、コモンモードフィードバック回路が第１及び第２の配線の同相電圧を検出し、検出した同相電圧と基準電位とを等しくする出力電圧を、当該第１及び第２の配線へフィードバックするので、第１及び第２の被検出容量が駆動パルスで駆動されても、第１及び第２の配線の同相電圧は基準電位に固定されるため、第１及び第２の配線の寄生容量への充電を防止できる。この結果、第１及び第２の被検出容量の容量差に対応した電荷だけが全差動増幅器へ転送されて差動増幅されるので、無駄なバイアス電流を流す必要がなくなり、Ｓ/Ｎの向上と低消費電力化を図ることができる。しかも、第１及び第２の被検出容量の静電容量差の検出に全差動増幅器を用いているので、全差動増幅器の入力段におけるコモンモードノイズはキャンセルされて除去でき、全差動増幅器の出力段側で重畳するコモンモードノイズも容易にキャンセルすることができる。 According to this configuration, the common mode feedback circuit detects the common-mode voltage of the first and second wirings, and feeds back the output voltage that makes the detected common-mode voltage equal to the reference potential to the first and second wirings. Therefore, even if the first and second detected capacitors are driven by the drive pulse, the common-mode voltage of the first and second wirings is fixed to the reference potential, so that the parasitic capacitances of the first and second wirings Can be prevented from charging. As a result, only the electric charge corresponding to the capacitance difference between the first and second detected capacitors is transferred to the fully differential amplifier and differentially amplified. Improvement and low power consumption can be achieved. In addition, since the fully differential amplifier is used to detect the capacitance difference between the first and second detected capacitors, the common mode noise in the input stage of the fully differential amplifier can be canceled and removed. Common mode noise superimposed on the output stage side of the amplifier can be easily canceled.
　また、本発明において、前記コモンモードフィードバック回路は、前記第１の配線に一方端子が接続された第１の入力コンデンサと、前記第２の配線に一方端子が接続され前記第１の入力コンデンサと等しい容量を有する第２の入力コンデンサと、前記第１及び第２の入力コンデンサの他方端子の共通接続点が反転入力端子に接続され非反転入力端子に基準電圧が印加され前記第１及び第２の配線へフィードバックする出力電圧を出力するシングル出力の差動増幅器と、を具備した構成としても良い。 In the present invention, the common mode feedback circuit includes a first input capacitor having one terminal connected to the first wiring, and a first input capacitor having one terminal connected to the second wiring. A common connection point between the second input capacitor having the same capacity and the other terminals of the first and second input capacitors is connected to the inverting input terminal, and a reference voltage is applied to the non-inverting input terminal, whereby the first and second input capacitors are connected. And a single output differential amplifier that outputs an output voltage fed back to the wiring.
　この構成により、第１及び第２の入力コンデンサの差動増幅器側の共通接続点には第１及び第２の配線の中間電位が現れ、差動増幅器が中間電位と基準電圧とが等しくなるように第１及び第２の配線へ出力電圧をフィードバックして第１及び第２の配線の電位変化を抑えるので、第１及び第２の配線に形成される寄生容量の影響を受けることなく、第１及び第２の被検出容量の容量差に対応した電荷だけを全差動増幅器へ転送することができる。また、シングル出力の差動増幅器を用いたことにより、複数出力を有する差動増幅器に比べて、回路を小型化できる。 With this configuration, the intermediate potential of the first and second wirings appears at the common connection point on the differential amplifier side of the first and second input capacitors so that the intermediate amplifier and the reference voltage are equal to each other. In addition, since the output voltage is fed back to the first and second wirings to suppress the potential change of the first and second wirings, the first and second wirings are not affected by the parasitic capacitance formed in the first and second wirings. Only the electric charge corresponding to the capacitance difference between the first and second detected capacitors can be transferred to the fully differential amplifier. Further, by using a single output differential amplifier, the circuit can be reduced in size as compared with a differential amplifier having a plurality of outputs.
　また、本発明において、前記コモンモードフィードバック回路は、一方端子が前記差動増幅器の出力端に接続され他方端子が前記第１の配線に接続された第１の出力コンデンサと、一方端子が前記差動増幅器の出力端に接続され他方端子が前記第２の配線に接続され前記第１の出力コンデンサと等しい容量を有する第２の出力コンデンサと、前記第１及び第２の入力コンデンサ並びに前記第１及び第２の出力コンデンサに対して並列に設けられ前記第１及び第２の被検出容量に駆動パルスを印加する直前に一端閉じて各々対応するコンデンサをリセットさせる複数のスイッチと、を具備した構成としても良い。 In the present invention, the common mode feedback circuit includes a first output capacitor having one terminal connected to the output terminal of the differential amplifier and the other terminal connected to the first wiring, and one terminal connected to the difference. A second output capacitor connected to the output terminal of the dynamic amplifier and having the other terminal connected to the second wiring and having a capacity equal to that of the first output capacitor; the first and second input capacitors; and the first And a plurality of switches that are provided in parallel with the second output capacitor and close one end immediately before applying a drive pulse to the first and second detected capacitors to reset the corresponding capacitors, respectively. It is also good.
　この構成により、第１及び第２の入力コンデンサ並びに第１及び第２の出力コンデンサに対して並列に設けられたスイッチを、第１及び第２の被検出容量に駆動パルスを印加する直前に一端閉じて各々対応するコンデンサをリセットできるので、高精度なコモンモードフィードバックが可能となる。 With this configuration, the switch provided in parallel with the first and second input capacitors and the first and second output capacitors is connected to the first and second detected capacitors immediately before applying a drive pulse. Closed and each corresponding capacitor can be reset, allowing high-precision common mode feedback.
　また、本発明において、前記第１の配線を前記全差動増幅器の一方の差動入力端子に接続すると共に前記第２の配線を前記全差動増幅器の他方の差動入力端子に接続する第１経路と、前記第１の配線を前記全差動増幅器の他方の差動入力端子に接続すると共に前記第２の配線を前記全差動増幅器の一方の差動入力端子に接続する第２経路と、に切替え可能な経路切替スイッチを備え、前記全差動増幅器は、前記出力端子から極性の異なる差動入力端子へ差動電圧をそれぞれフィードバックする各フィードバック経路にそれぞれ設けられ当該差動電圧に応じた電荷量を蓄積する積分コンデンサと、前記各積分コンデンサに対して並列に設けられたリセットスイッチと備え、前記経路切替スイッチは、駆動パルスの立ち上がりでは第１経路を選択し、当該駆動パルスの立ち下がりでは第２経路を選択するように経路切替えを行い、前記全差動増幅器は、駆動パルスの立ち上がりと立下りの両方で前記積分コンデンサに電荷を蓄積し、積分回数が所定回数となったところで前記リセットスイッチを閉じて積分コンデンサをリセットすることを特徴とする。 In the present invention, the first wiring is connected to one differential input terminal of the fully differential amplifier, and the second wiring is connected to the other differential input terminal of the fully differential amplifier. One path and a second path connecting the first wiring to the other differential input terminal of the fully-differential amplifier and connecting the second wiring to one differential input terminal of the fully-differential amplifier The fully-differential amplifier is provided in each feedback path that feeds back a differential voltage from the output terminal to a differential input terminal having a different polarity. An integration capacitor for accumulating a corresponding amount of charge, and a reset switch provided in parallel with each of the integration capacitors. The path switch selects the first path at the rising edge of the drive pulse. Then, the path is switched so that the second path is selected at the fall of the drive pulse, and the fully differential amplifier accumulates electric charge in the integration capacitor at both the rise and fall of the drive pulse, and the number of integrations When the predetermined number of times is reached, the reset switch is closed to reset the integrating capacitor.
　この構成により、経路切替スイッチが駆動パルスの立ち上がりでは第１経路を選択し、当該駆動パルスの立ち下がりでは第２経路を選択して、駆動パルスの立ち上がりと立下りの両方で前記積分コンデンサに電荷を蓄積するようにしたので、必要な信号レベルが得られるまで連続して積分動作を繰り返すことができる。 With this configuration, the path changeover switch selects the first path at the rising edge of the driving pulse, selects the second path at the falling edge of the driving pulse, and charges the integration capacitor at both the rising and falling edges of the driving pulse. Therefore, the integration operation can be repeated continuously until a necessary signal level is obtained.
　また本発明は、前記第１及び第２の配線に接続され、前記第１及び第２の被検出容量のコモンモード成分を相殺するコモンモード容量アレイを備えてもよい。 The present invention may also include a common mode capacitor array connected to the first and second wirings and canceling the common mode component of the first and second detected capacitors.
　この構成により、コモンモード容量アレイを備えるので、第１及び第２の被検出容量のコモンモード成分を相殺でき、コモンモードフィードバック回路の差動増幅器の電源電圧を増大することなく、第１及び第２の入力コンデンサの容量を小さくでき、回路規模の縮小と消費電力の低減を図ることができる。 With this configuration, since the common mode capacitor array is provided, the common mode components of the first and second detected capacitors can be canceled out, and the first and second power supply voltages of the differential amplifier of the common mode feedback circuit are not increased. The capacity of the input capacitor 2 can be reduced, and the circuit scale and power consumption can be reduced.
　また、本発明において、前記コモンモード容量アレイは、前記第１又は第２の配線に一方端子がそれぞれ接続された複数のコンデンサからなるコンデンサ群と、前記コンデンサ群を構成する各コンデンサの他方端子にそれぞれ接続された複数のスイッチからなるスイッチ群とを備え、前記スイッチ群を用いて前記第１及び第２の被検出容量のコモンモード成分に相当するキャンセル容量となる複数コンデンサを選択し、前記駆動パルスを反転させた反転パルスを前記スイッチ群を介して前記コンデンサ群の他方端子に印加する構成とすることができる。 In the present invention, the common mode capacitor array may include a capacitor group including a plurality of capacitors each having one terminal connected to the first or second wiring, and the other terminal of each capacitor constituting the capacitor group. A switch group including a plurality of switches connected to each other, and using the switch group, a plurality of capacitors having a canceling capacity corresponding to a common mode component of the first and second detected capacitors are selected, and the driving An inversion pulse obtained by inverting the pulse can be applied to the other terminal of the capacitor group via the switch group.
　本発明によれば、ノイズ耐性に優れ、消費電流を抑制可能で、信号のダイナミックレンジを効率よく確保できる静電容量検出回路を実現できる。 According to the present invention, it is possible to realize a capacitance detection circuit that is excellent in noise resistance, can suppress current consumption, and can efficiently secure a dynamic range of signals.
本発明の一実施の形態に係る静電容量検出回路の構成図である。It is a block diagram of the electrostatic capacitance detection circuit which concerns on one embodiment of this invention. 上記実施の形態における入力コモンモードキャンセル容量アレイの構成図である。It is a block diagram of the input common mode cancellation capacity | capacitance array in the said embodiment. 上記実施の形態における入力コモンモードフィードバック回路の構成図である。It is a block diagram of the input common mode feedback circuit in the said embodiment. 被検出容量の充電電圧と配線の電圧波形との関係を説明するための説明図である。It is explanatory drawing for demonstrating the relationship between the charging voltage of to-be-detected capacity | capacitance, and the voltage waveform of wiring. （ａ）図４の被検出量容量に印加する駆動パルスの波形図、（ｂ）入力コモンモードフィードバック回路がない場合の電圧波形図、（ｃ）入力コモンモードフィードバック回路がある場合の電圧波形図である。4A is a waveform diagram of a drive pulse applied to the detected capacitance of FIG. 4, FIG. 4B is a voltage waveform diagram when there is no input common mode feedback circuit, and FIG. 4C is a voltage waveform diagram when there is an input common mode feedback circuit. It is. 上記実施の形態の動作の流れを説明するためのタイミングチャートである。It is a timing chart for demonstrating the flow of operation | movement of the said embodiment. 上記実施の形態における全差動増幅器の電圧出力波形である。It is a voltage output waveform of the fully differential amplifier in the said embodiment. コモンモードフィードバック回路の変形例を示す図である。It is a figure which shows the modification of a common mode feedback circuit. 従来のシングルエンド型の静電容量検出回路の構成図である。It is a block diagram of the conventional single end type capacitance detection circuit.
　以下、本発明の実施の形態について添付図面を参照して詳細に説明する。
　図１は本発明の一実施の形態に係る静電容量検出回路の構成図である。本実施の形態に係る静電容量検出回路は、駆動信号源４１から供給される駆動パルスＤＲＶが容量センサを構成する被検出容量４２及び被検出容量（又は参照容量）４３の一方端子となる一方の電極に印加される。一方の被検出容量４２は他方の電極が配線６０－１を介して全差動増幅器４９の差動入力端子（後述するストレート経路の場合、正側端子）に接続され、他方の被検出容量４３は同じく他方の電極が配線６０－２を介して全差動増幅器４９の他方の差動入力端子（ストレート経路の場合、負側端子）に接続されている。配線６０－１及び６０－２に対して入力コモンモードキャンセル容量アレイ４４と、入力コモンモードフィードバック回路４５とが接続されている。また、配線６０－１及び６０－２には経路切替えスイッチ４６が設けられている。経路切替えスイッチ４６は、被検出容量４２の電極を配線６０－１を介して全差動増幅器４９の差動入力端子（正側）に接続すると共に、被検出容量４３の電極を配線６０－２を介して全差動増幅器４９の差動入力端子（負側）に接続するストレート経路と、被検出容量４２の電極を配線６０－１を介して全差動増幅器４９の差動入力端子（負側）に接続すると共に、被検出容量４３の電極を配線６０－２を介して全差動増幅器４９の差動入力端子（正側）に接続するクロス経路とに切り替える。ストレート経路では、スイッチφ１を閉じると共にスイッチφ２を開放し、クロス経路ではスイッチφ１を開放すると共にスイッチφ２を閉じる。全差動増幅器４９は、正側の差動入力端子と負側の差動入力端子に入力する入力Ｖｉｎ＋とＶｉｎ－との差が０になるように負側の出力端子及び正側の出力端子の差動出力（Ｖｏｕｔ－、Ｖｏｕｔ＋）を制御する。全差動増幅器４９の負側出力端子と正側差動入力端子との間にはリセットスイッチ４７ａ及び積分コンデンサ４８ａが並列に接続され、正側出力端子と負側差動入力端子との間にはリセットスイッチ４７ｂ及び積分コンデンサ４８ｂが並列に接続されている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a configuration diagram of a capacitance detection circuit according to an embodiment of the present invention. In the capacitance detection circuit according to the present embodiment, the drive pulse DRV supplied from the drive signal source 41 serves as one terminal of the detected capacitor 42 and the detected capacitor (or reference capacitor) 43 constituting the capacitance sensor. Applied to the electrodes. One detected capacitor 42 has the other electrode connected to a differential input terminal (a positive terminal in the case of a straight path to be described later) of the fully differential amplifier 49 via the wiring 60-1, and the other detected capacitor 43 Similarly, the other electrode is connected to the other differential input terminal (negative terminal in the case of a straight path) of the fully differential amplifier 49 via the wiring 60-2. An input common mode cancellation capacitor array 44 and an input common mode feedback circuit 45 are connected to the wirings 60-1 and 60-2. Further, a path changeover switch 46 is provided in the wirings 60-1 and 60-2. The path changeover switch 46 connects the electrode of the detected capacitor 42 to the differential input terminal (positive side) of the fully-differential amplifier 49 via the wiring 60-1, and connects the electrode of the detected capacitor 43 to the wiring 60-2. The straight path connected to the differential input terminal (negative side) of the fully-differential amplifier 49 via the wire and the electrode of the capacitor 42 to be detected are connected to the differential input terminal (negative-side) of the fully-differential amplifier 49 via the wiring 60-1. To the cross path connected to the differential input terminal (positive side) of the fully-differential amplifier 49 via the wiring 60-2. In the straight path, the switch φ1 is closed and the switch φ2 is opened, and in the cross path, the switch φ1 is opened and the switch φ2 is closed. The fully differential amplifier 49 has a negative output terminal and a positive output terminal so that the difference between the input Vin + and Vin− input to the positive differential input terminal and the negative differential input terminal is zero. The differential output (Vout−, Vout +) is controlled. A reset switch 47a and an integrating capacitor 48a are connected in parallel between the negative output terminal and the positive differential input terminal of the fully differential amplifier 49, and between the positive output terminal and the negative differential input terminal. The reset switch 47b and the integrating capacitor 48b are connected in parallel.
　図２は入力コモンモードキャンセル容量アレイ４４の構成図である。入力コモンモードキャンセル容量アレイ４４は、並列に配列された複数のコンデンサで構成されたコンデンサ群５１と、コンデンサ群５１を構成する個々のコンデンサに対して設けられた複数のスイッチから構成されるスイッチ群５２とを有する。コンデンサ群５１は、個々のコンデンサが一方の配線６０－１に接続されている第１のコンデンサ群５１ａと、個々のコンデンサが他方の配線６０－２に接続されている第２のコンデンサ群５１ｂとで構成されている。スイッチ群５２は、個々のスイッチに個別に印加されるセレクタ信号ＳＥＬ－Ｃ０…によってオン／オフ制御されるように構成されている。またコンデンサ群５１ａとコンデンサ群５１ｂの各コンデンサの容量は同じになるように設定される。後述するように、セレクタ信号ＳＥＬ－Ｃ０…によって選択（オン制御）したスイッチを介して、駆動パルスを反転した逆相パルスをコンデンサに印加することで、配線６０－１及び６０－２に対して、選択スイッチ（コンデンサ）数に応じた同じ電荷量をキャンセルできるように構成している。 FIG. 2 is a configuration diagram of the input common mode canceling capacitor array 44. The input common mode cancellation capacitor array 44 includes a capacitor group 51 composed of a plurality of capacitors arranged in parallel and a switch group composed of a plurality of switches provided for the individual capacitors constituting the capacitor group 51. 52. The capacitor group 51 includes a first capacitor group 51a in which each capacitor is connected to one wiring 60-1, and a second capacitor group 51b in which each capacitor is connected to the other wiring 60-2. It consists of The switch group 52 is configured to be on / off controlled by selector signals SEL-C0... Individually applied to individual switches. The capacitors 51a and 51b are set to have the same capacitance. As will be described later, a reverse-phase pulse obtained by inverting the drive pulse is applied to the capacitor via a switch selected (on-controlled) by the selector signal SEL-C0. The same charge amount corresponding to the number of selection switches (capacitors) can be canceled.
　図３は入力コモンモードフィードバック回路４５の構成図である。入力コモンモードフィードバック回路４５は、配線６０－１、６０－２に接続され互いに等しい容量値に設定されたコモンモード出力コンデンサ６５、６６と、配線６０－１、６０－２に接続され互いに等しい容量値に設定されたコモンモード入力コンデンサ６７、６８と、シングル出力の差動増幅器６９とを備えている。 FIG. 3 is a block diagram of the input common mode feedback circuit 45. The input common mode feedback circuit 45 is connected to the wirings 60-1 and 60-2 and connected to the wirings 60-1 and 60-2. Common mode input capacitors 67 and 68 set to values and a single output differential amplifier 69 are provided.
　コモンモード入力コンデンサ６７、６８は、一方の電極が対応する配線６０－１、６０－２にそれぞれ接続され、共通接続された他方の電極は差動増幅器６９の反転入力端子に接続されている。また、２つのコモンモード入力コンデンサ６７、６８にはスイッチ６３，６４が並列に接続されている。 The common mode input capacitors 67 and 68 have one electrode connected to the corresponding wiring 60-1 and 60-2, respectively, and the other electrode connected in common is connected to the inverting input terminal of the differential amplifier 69. Further, switches 63 and 64 are connected in parallel to the two common mode input capacitors 67 and 68.
　差動増幅器６９の非反転入力端子には基準電圧Ｖｒｅｆが印加されている。コモンモード入力コンデンサ６７、６８の他方の電極側となる共通接続点には配線６０－１と配線６０－２の中間電位が現れる。したがって、差動増幅器６９は、配線６０－１と配線６０－２の中間電位を基準電圧Ｖｒｅｆに固定するような差動増幅信号を出力する。 The reference voltage Vref is applied to the non-inverting input terminal of the differential amplifier 69. An intermediate potential between the wiring 60-1 and the wiring 60-2 appears at the common connection point on the other electrode side of the common mode input capacitors 67 and 68. Therefore, the differential amplifier 69 outputs a differential amplification signal that fixes the intermediate potential between the wiring 60-1 and the wiring 60-2 to the reference voltage Vref.
　コモンモード出力コンデンサ６５、６６は、一方の電極が共通接続されていて、共通接続点に差動増幅器６９の出力端子が接続されている。コモンモード出力コンデンサ６５、６６の他方の電極は対応する配線６０－１、６０－２にそれぞれ接続されている。各コモンモード出力コンデンサ６５、６６にはスイッチ６１，６２が並列に接続されている。 The common mode output capacitors 65 and 66 have one electrode connected in common, and the output terminal of the differential amplifier 69 is connected to the common connection point. The other electrodes of the common mode output capacitors 65 and 66 are connected to corresponding wirings 60-1 and 60-2, respectively. Switches 61 and 62 are connected in parallel to the common mode output capacitors 65 and 66, respectively.
　なお、差動増幅器６９の出力と配線６０－１、６０－２とを分離するタイミングが必要な場合には、その経路にアナログスイッチを設けてもよい。 In addition, when the timing which isolate | separates the output of the differential amplifier 69 and wiring 60-1, 60-2 is required, you may provide an analog switch in the path | route.
　次に、以上のように構成された本実施の形態の動作について説明する。
　共通接続された被検出容量４２、４３の一方の電極に駆動信号源４１から駆動パルスが印加され、駆動パルスの変化点（立上がり／立下り）で配線６０－１，６０－２間に被検出容量４２、４３の静電容量差に応じた電位差が生じる。配線６０－１，６０－２間に生じた被検出容量４２、４３の静電容量差に応じた電荷は経路切り替えスイッチ４６を介してストレート経路又はクロス経路にて全差動増幅器４９に移動して積分コンデンサ４８ａ，４８ｂに蓄積される。全差動増幅器４９では積分コンデンサ４８ａ，４８ｂとリセットスイッチ４７ａ，４７ｂによりリセット動作と積分動作を繰り返し、被検出容量の静電容量差に応じた差動電圧（Ｖｏｕｔ－、Ｖｏｕｔ＋）を出力する。 Next, the operation of the present embodiment configured as described above will be described.
A drive pulse is applied from the drive signal source 41 to one electrode of the commonly connected detected capacitors 42 and 43, and the detected signal is detected between the wirings 60-1 and 60-2 at the change point (rising / falling) of the driving pulse. A potential difference corresponding to the capacitance difference between the capacitors 42 and 43 is generated. The electric charge corresponding to the capacitance difference between the detected capacitors 42 and 43 generated between the wirings 60-1 and 60-2 moves to the fully-differential amplifier 49 via the path switching switch 46 through a straight path or a cross path. Are accumulated in the integrating capacitors 48a and 48b. The fully differential amplifier 49 repeats the reset operation and the integration operation by the integrating capacitors 48a and 48b and the reset switches 47a and 47b, and outputs a differential voltage (Vout−, Vout +) corresponding to the capacitance difference of the detected capacitance.
　以上のように被検出容量４２、４３の静電容量差に応じた電荷が積分コンデンサ４８ａ，４８ｂへ転送される過程で、入力コモンモードフィードバック回路４５によるコモンモード成分のキャンセル操作が行われる。 As described above, the common mode component canceling operation is performed by the input common mode feedback circuit 45 in the process in which the electric charge according to the capacitance difference between the detected capacitors 42 and 43 is transferred to the integrating capacitors 48a and 48b.
　入力コモンモードフィードバック回路４５の動作原理について説明する。先ず、被検出容量４２，４３の充電電圧と配線６０－１、６０－２の電圧波形との関係を説明するため、図４に示すように全差動増幅器４９がない回路モデル（フィードバック無し）を想定する。図４に示す被検出容量１０５，１０６は図１に示す被検出容量４２，４３、配線１０２，１０３は配線６０－１、６０－２にそれぞれ相当する。 The operation principle of the input common mode feedback circuit 45 will be described. First, in order to explain the relationship between the charging voltage of the capacitors 42 and 43 to be detected and the voltage waveform of the wirings 60-1 and 60-2, a circuit model without the fully differential amplifier 49 as shown in FIG. 4 (no feedback) Is assumed. The detected capacitors 105 and 106 shown in FIG. 4 correspond to the detected capacitors 42 and 43 shown in FIG. 1, and the wirings 102 and 103 correspond to the wirings 60-1 and 60-2, respectively.
　図５（ａ）（ｂ）に示すように、入力コモンモードフィードバック回路を動作させない状態では、駆動パルス１０４を被検出容量１０５，１０６に印加すると、駆動パルス１０４の立ち上がりで被検出容量１０５，１０６が充電され、被検出容量１０５，１０６の充電電位に対応した電圧波形が配線１０２、１０３に現れる。被検出容量１０５と被検出容量１０６の電位差Ｖａ（被検出容量１０５＞被検出容量１０６）を全差動増幅器４９で検出することになる。 As shown in FIGS. 5A and 5B, in a state where the input common mode feedback circuit is not operated, when the drive pulse 104 is applied to the detected capacitors 105 and 106, the detected capacitors 105 and 106 are detected at the rising edge of the drive pulse 104. Is charged, and voltage waveforms corresponding to the charged potentials of the detected capacitors 105 and 106 appear on the wirings 102 and 103. The potential difference Va between the detected capacitor 105 and the detected capacitor 106 (detected capacitor 105> detected capacitor 106) is detected by the fully differential amplifier 49.
　ところが、図４に示すように配線１０２，１０３には必ず寄生容量１０１が存在する。配線１０２，１０３の寄生容量１０１は、各配線１０２、１０３に発生した電位変化Ｖｂに応じて充電される。電位変化Ｖｂによって配線１０２，１０３の寄生容量１０１が充電される現象は、センシング対象である電位差Ｖａを小さくする方向に作用し、センサとしての感度が低下することを意味する。寄生容量１０１が充電される現象は、配線１０２、１０３に電位変化Ｖｂが生じることになるので、本実施の形態は入力コモンモードフィードバック回路４５によって配線１０２と配線１０３の中間電位を基準電圧Ｖｒｅｆに固定することで、駆動パルス立ち上がり（及び立下り）での寄生容量１０１への充電を防止することとした。 However, as shown in FIG. 4, the parasitic capacitance 101 always exists in the wirings 102 and 103. The parasitic capacitance 101 of the wirings 102 and 103 is charged according to the potential change Vb generated in each of the wirings 102 and 103. The phenomenon that the parasitic capacitance 101 of the wirings 102 and 103 is charged by the potential change Vb acts in the direction of decreasing the potential difference Va that is a sensing target, and means that the sensitivity as a sensor is lowered. Since the phenomenon in which the parasitic capacitance 101 is charged results in a potential change Vb in the wirings 102 and 103, the present embodiment changes the intermediate potential between the wiring 102 and the wiring 103 to the reference voltage Vref by the input common mode feedback circuit 45. By fixing, charging of the parasitic capacitance 101 at the rising edge (and falling edge) of the driving pulse is prevented.
　図５（ｃ）は図４に示す回路モデルにおいて入力コモンモードフィードバック回路４５を動作させた場合における駆動パルス立ち上がり時点での配線１０２及び１０３の電圧波形を示している。入力コモンモードフィードバック回路４５が配線１０２と配線１０３の中間電位を基準電圧Ｖｒｅｆに固定するようにフィードバック制御しているため、被検出容量１０５と被検出容量１０６の電位差Ｖａ’は配線１０２及び１０３に生じるが、各配線１０２及び１０３には寄生容量１０１を充電するような電位変化（Ｖｂ）は生じない。したがって、配線１０２及び１０３から入力コモンモード成分だけをキャンセルし、被検出容量１０５と被検出容量１０６の電位差Ｖａ’に対応した電荷だけを全差動増幅器４９へ転送することができる。 FIG. 5 (c) shows voltage waveforms of the wirings 102 and 103 at the time of driving pulse rise when the input common mode feedback circuit 45 is operated in the circuit model shown in FIG. Since the input common mode feedback circuit 45 performs feedback control so that the intermediate potential between the wiring 102 and the wiring 103 is fixed to the reference voltage Vref, the potential difference Va ′ between the detected capacitor 105 and the detected capacitor 106 is applied to the wirings 102 and 103. However, a potential change (Vb) that charges the parasitic capacitance 101 does not occur in the wirings 102 and 103. Therefore, it is possible to cancel only the input common mode component from the wirings 102 and 103 and transfer only the charge corresponding to the potential difference Va ′ between the detected capacitor 105 and the detected capacitor 106 to the fully differential amplifier 49.
　図５の電圧波形を理論的に説明するため、被検出容量１０５の容量が１０．１ｐＦ、被検出容量１０６の容量が１０ｐＦとして、静電容量差が０．１ｐＦの場合を想定する。配線１０２、１０３に形成される寄生容量１０１をそれぞれ１０ｐＦとした場合、駆動パルスの振幅が２Ｖで基準電圧Ｖｒｅｆが１Ｖの時、図５のＶａ（Ｖａ´）は、被検出容量１０５の電位をＶ１０５、被検出容量１０６の電位をＶ１０６とすると、以下のように計算できる。 In order to theoretically explain the voltage waveform of FIG. 5, it is assumed that the capacitance of the detected capacitor 105 is 10.1 pF, the capacitance of the detected capacitor 106 is 10 pF, and the capacitance difference is 0.1 pF. When the parasitic capacitance 101 formed in each of the wirings 102 and 103 is 10 pF, when the drive pulse amplitude is 2 V and the reference voltage Vref is 1 V, Va (Va ′) in FIG. Assuming that V105 and the potential of the detected capacitor 106 are V106, the calculation can be performed as follows.
（入力コモンモードフィードバック回路がない場合）
　（Ｖ１０５－２Ｖ）×１０ｐＦ＋Ｖ１０５×１０ｐＦ＝（１０ｐＦ＋１０ｐＦ）×１Ｖ
右辺は被検出容量１０５側に接続された配線の初期電荷量である。
よって、Ｖ１０５＝２Ｖ
　（Ｖ１０６－２Ｖ）×１０．１ｐＦ＋Ｖ１０６×１０ｐＦ＝（１０．１ｐＦ＋１０ｐＦ）×１Ｖ
右辺は被検出容量１０６側に接続された配線の初期電荷量である。
よって、Ｖ１０６＝２．００５Ｖ
故に、Ｖａ＝Ｖ１０６－Ｖ１０５＝０．００５Ｖ、となる。
この差分から全差動増幅器が読み取とる電荷量は多くても、
　０．００５Ｖ×（１０ｐＦ＋１０．１ｐＦ）＝０．１ｐＣ
となる。 (When there is no input common mode feedback circuit)
(V105-2V) × 10 pF + V105 × 10 pF = (10 pF + 10 pF) × 1V
The right side is the initial charge amount of the wiring connected to the detected capacitor 105 side.
Therefore, V105 = 2V
(V106-2V) × 10.1 pF + V106 × 10 pF = (10.1 pF + 10 pF) × 1V
The right side is the initial charge amount of the wiring connected to the detected capacitor 106 side.
Therefore, V106 = 2.005V
Therefore, Va = V106−V105 = 0.005V.
From this difference, the total differential amplifier can read a large amount of charge,
0.005 V × (10 pF + 10.1 pF) = 0.1 pC
It becomes.
（入力コモンモードフィードバック回路がある場合）
寄生容量１０１への電荷の充放電がないので、
　２Ｖ×（１０．１ｐＦ－１０ｐＦ）＝０．２ｐＣ、となる。 (When there is an input common mode feedback circuit)
Since there is no charge charge / discharge to the parasitic capacitance 101,
2V × (10.1 pF−10 pF) = 0.2 pC.
　以上の計算例から判るように、被検出容量の静電容量とその配線に形成される寄生容量がほぼ同じ大きさの場合は、読み取れる電荷量は２倍に増加させることができる。 As can be seen from the above calculation examples, when the capacitance of the detected capacitance and the parasitic capacitance formed on the wiring are approximately the same size, the amount of charge that can be read can be doubled.
　次に、本実施の形態に係る静電容量検出回路の動作の流れを図６のタイミングチャートを使って説明する。 Next, the operation flow of the capacitance detection circuit according to the present embodiment will be described with reference to the timing chart of FIG.
　経路切替えスイッチ４６では、駆動信号源４１から出力される駆動パルスの立ち上がり、立下りで、スイッチφ１とスイッチφ２が相補的にオン／オフされる。φ１がＨｉｇｈ（閉）のとき経路切替えスイッチ４６がストレート経路（φ１オン）、φ２がＨｉｇｈ（閉）のときクロス経路（φ２オン）となる。 In the path changeover switch 46, the switches φ1 and φ2 are complementarily turned on / off at the rise and fall of the drive pulse output from the drive signal source 41. When φ1 is High (closed), the path switch 46 is a straight path (φ1 on), and when φ2 is High (closed), it is a cross path (φ2 on).
　まず、積分動作の初期化を行うために、図６のＴ１のタイミングでＲＳＴ－Ｃの信号が立ち上がり、積分コンデンサ４８ａ，４８ｂに設けられたスイッチ４７ａ，４７ｂが閉じて積分コンデンサ４８ａ，４８ｂの電荷をリセットする。それと同時にＲＳＴ－Ｉが立ち上がり、これにより入力コモンモードフィードバック回路４５のスイッチ６１～６４がすべて閉じられ、差動増幅器６９はボルテージフォロワー構成となる。従って、被検出容量４２，４３と全差動増幅器４９を結ぶ配線６０－１、６０－２が基準電圧Ｖｒｅｆに設定されるとともに、コモンモード出力コンデンサ６５、６６とコモンモード入力コンデンサ６７、６８の電荷がリセットされる。 First, in order to initialize the integration operation, the RST-C signal rises at the timing T1 in FIG. 6, the switches 47a and 47b provided in the integration capacitors 48a and 48b are closed, and the charges of the integration capacitors 48a and 48b are closed. To reset. At the same time, RST-I rises, whereby all the switches 61 to 64 of the input common mode feedback circuit 45 are closed, and the differential amplifier 69 has a voltage follower configuration. Accordingly, the wirings 60-1 and 60-2 connecting the detected capacitors 42 and 43 and the fully differential amplifier 49 are set to the reference voltage Vref, and the common mode output capacitors 65 and 66 and the common mode input capacitors 67 and 68 are connected to each other. The charge is reset.
　次に、ＲＳＴ－Ｃ及びＲＳＴ－Ｉがともに立下り、リセット動作が解除され、経路切替えスイッチ４６は、φ１がＨｉｇｈとなりストレート経路（φ１オン）に設定される。 Next, both RST-C and RST-I fall, the reset operation is canceled, and the path changeover switch 46 is set to the straight path (φ1 on) with φ1 being High.
　Ｔ２のタイミングで、被検出容量４２、４３が駆動パルスの立ち上がり波形で駆動される。このとき入力コモンモードフィードバック回路４５は、配線６０－１、６０－２の同相電圧を検出する。具体的には、等しい大きさの容量で構成されたコモンモード入力コンデンサ６７、６８によって検出された配線６０－１と６０－２の中間電位を、差動増幅器６９の反転入力端子に与える。差動増幅器６９は基準電圧Ｖｒｅｆと反転入力端子入力（中間電位）との差を増幅して出力する。このときの出力電圧はコモンモード出力コンデンサ６５、６６を介して配線６０－１、６０－２にフィードバックされるが、コモンモード出力コンデンサ６５、６６は等しい大きさの容量で構成しているので、配線６０－１と６０－２の電圧の同相電圧を与えることになる。このフィードバック制御により、被検出容量４２、４３（センサ容量）から出力される信号を伝える配線６０－１、６０－２の同相電圧を、基準電圧Ｖｒｅｆに保つように動作する。 At the timing of T2, the detected capacitors 42 and 43 are driven with the rising waveform of the drive pulse. At this time, the input common mode feedback circuit 45 detects the common-mode voltage of the wirings 60-1 and 60-2. Specifically, an intermediate potential of the wirings 60-1 and 60-2 detected by the common mode input capacitors 67 and 68 configured with equal capacity is applied to the inverting input terminal of the differential amplifier 69. The differential amplifier 69 amplifies and outputs the difference between the reference voltage Vref and the inverting input terminal input (intermediate potential). The output voltage at this time is fed back to the wirings 60-1 and 60-2 via the common mode output capacitors 65 and 66, but the common mode output capacitors 65 and 66 are configured with equal capacity. A common-mode voltage of the voltages of the wirings 60-1 and 60-2 is given. By this feedback control, the common-mode voltage of the wirings 60-1 and 60-2 for transmitting signals output from the detected capacitors 42 and 43 (sensor capacitors) is operated to keep the reference voltage Vref.
　全差動増幅器４９は、正側差動入力端子と負側差動入力端子との間の電圧差を０にすべく、負側出力端子及び正側出力端子の出力から積分コンデンサ４８ａ，４８ｂを介してフィードバック動作を行う。その結果として、全差動増幅器４９は被検出容量４２、４３の容量差に対応する電圧を出力することになる。このとき出力される電圧は被検出容量４２、４３の容量差を△Ｃ、積分容量をそれぞれＣｉとし、駆動パルスの波高値をＶｉとすると
　　　Ｖｏｕｔ＋　－　Ｖｏｕｔ－　＝△Ｃ×Ｖｉ/Ｃｉ
となる。積分容量Ｃｉの大きさを適当に決めることで、出力電圧のレベルを設定可能である。 The fully differential amplifier 49 includes integrating capacitors 48a and 48b from the outputs of the negative output terminal and the positive output terminal so that the voltage difference between the positive differential input terminal and the negative differential input terminal is zero. To perform feedback operation. As a result, the fully differential amplifier 49 outputs a voltage corresponding to the capacitance difference between the detected capacitors 42 and 43. The voltage output at this time is defined as: ΔC is the capacitance difference between the detected capacitors 42 and 43, Ci is the integration capacitance, and Vi is the peak value of the drive pulse. Vout + −Vout− = ΔC × Vi / Ci
It becomes. The level of the output voltage can be set by appropriately determining the size of the integration capacitor Ci.
　以上で一回分の積分動作が完了する。一回分の積分動作で得られる出力電圧には制限があるので、所望の出力電圧が得られるまで、積分動作を繰り返すことが有効である。その為に、Ｔ３のタイミングでＲＳＴ－Ｉをアクティブにし、コモンモード入力コンデンサ６７、６８およびコモンモード出力コンデンサ６６、６７をリセットし、配線６０－１、６０－１をＶｒｅｆに設定しなおす。これにより、コンデンサ６５～６８でのリークの影響を一端リセットし、後続する繰り返し動作における影響を最小限にすることができる。 This completes one integration operation. Since the output voltage obtained by one integration operation is limited, it is effective to repeat the integration operation until a desired output voltage is obtained. Therefore, RST-I is made active at the timing of T3, the common mode input capacitors 67 and 68 and the common mode output capacitors 66 and 67 are reset, and the wirings 60-1 and 60-1 are reset to Vref. As a result, the influence of leakage in the capacitors 65 to 68 can be reset once, and the influence in the subsequent repetitive operation can be minimized.
　このとき、ＲＳＴ－Ｃはアクティブにせず積分容量の電荷はそのままになるようにする。その後、ＲＳＴ－Ｉは立ち下がり、経路切替えスイッチ４６でφ２をアクティブにすることで配線をクロス経路（φ２オン）にする。これにより、駆動信号源４１から出力される駆動パルスの立下り（T4）において、被検出容量４２，４３の差分に対応する信号が全差動増幅器４９の積分容量４８ａ，４８ｂに加算される方向で蓄積することができる。図７は全差動増幅器４９の電圧出力波形である。被検出容量４２，４３の差分が全差動増幅器４９の積分容量４８に積分回数分加算され、基準電圧Ｖｒｅｆを中心にして正側出力Ｖｏｕｔ＋、負側出力Ｖｕｏｔ－が階段状に大きくなっている。 At this time, the RST-C is not activated and the charge of the integration capacitor remains unchanged. Thereafter, RST-I falls, and the path changeover switch 46 activates φ2 to set the wiring to the cross path (φ2 on). Thereby, at the falling edge (T4) of the driving pulse output from the driving signal source 41, a signal corresponding to the difference between the detected capacitors 42 and 43 is added to the integrating capacitors 48a and 48b of the fully differential amplifier 49. Can be accumulated. FIG. 7 shows a voltage output waveform of the fully differential amplifier 49. The difference between the detected capacitors 42 and 43 is added to the integration capacitor 48 of the fully differential amplifier 49 by the number of integrations, and the positive side output Vout + and the negative side output Vut− increase stepwise with the reference voltage Vref as the center. .
　この様にして積分動作を繰り返すことで、必要な信号レベルまで被検出容量の差分に対応する信号を増幅することができる。 In this way, by repeating the integration operation, it is possible to amplify the signal corresponding to the difference in the detected capacitance up to the required signal level.
　以上の動作の中で全差動増幅器４９は被検出容量４２，４３の差分に対応する電荷量のみが入力され増幅できることにより無駄なバイアス電流を流す必要がなくなり、Ｓ／Ｎが向上する。 In the above operation, the fully differential amplifier 49 can input and amplify only the amount of charge corresponding to the difference between the detected capacitors 42 and 43, so that it is not necessary to pass a wasteful bias current, and the S / N is improved.
　次に、入力コモンモード容量アレイ４４の機能について説明する。
　入力コモンモードフィードバック回路４５のコモンモード出力コンデンサ６５、６６は、差動増幅器６９の出力電圧を配線６０－１，６０－２へ出力するために設けられており、コモンモード出力コンデンサ６５、６６の容量を小さくした場合、配線６０－１と配線６０－２との中間電位と基準電圧Ｖｒｅｆとの差をなくすように動作する差動増幅器６９に大きな電源電圧を供給して出力振幅を大きくする必要がある。差動増幅器６９の出力振幅（電源電圧）を抑えるためには、コモンモード出力コンデンサ６５、６６の容量を大きくする必要があるので、容量面積の拡大が必要となる。コモンモード出力コンデンサ６５、６６の面積拡大も実装面積を圧迫するために望ましくない。 Next, the function of the input common mode capacitor array 44 will be described.
The common mode output capacitors 65 and 66 of the input common mode feedback circuit 45 are provided to output the output voltage of the differential amplifier 69 to the wirings 60-1 and 60-2. When the capacitance is reduced, it is necessary to increase the output amplitude by supplying a large power supply voltage to the differential amplifier 69 that operates so as to eliminate the difference between the intermediate potential between the wiring 60-1 and the wiring 60-2 and the reference voltage Vref. There is. In order to suppress the output amplitude (power supply voltage) of the differential amplifier 69, it is necessary to increase the capacitances of the common mode output capacitors 65 and 66. Therefore, it is necessary to increase the capacitance area. An increase in the area of the common mode output capacitors 65 and 66 is also undesirable because it reduces the mounting area.
　そこで、入力コモンモード容量アレイ４４により、配線６０－１，６０－２に接続されたコンデンサ群に駆動パルスの逆相の反転パルスを印加することで、コモンモードの電荷量を相殺することとした。 Therefore, the common-mode charge amount is canceled by applying an inversion pulse having a phase opposite to that of the drive pulse to the capacitors connected to the wirings 60-1 and 60-2 by the input common-mode capacitance array 44. .
　図２において、コンデンサ群５１ａ，５１ｂは、各コンデンサの配線側の電極が被検出容量４２及び４３に対応した各配線６０－１，６０－２にそれぞれ接続される一方、各コンデンサの反対側の電極がスイッチ群５２を介して駆動パルスの逆相の反転パルス供給端に接続される。各容量は適当な値もしくは重み付けされた大きさをとり被検出容量４２、４３の平均的な値になるようにＳＥＬ－Ｃ信号によりスイッチ群を設定する。このことにより被検出容量４２、４３の大部分のコモンモードの電荷量をコンデンサ群５１ａ，５１ｂの電荷量で被検出容量４２、４３のコモンモードに対応する電荷量を相殺することが可能となり、入力コモンモードフィードバック回路４５のコモンモード出力コンデンサ６５、６６の大きさを削減できるとともに、差動増幅器６９の駆動能力を抑制できて、回路規模、消費電力を削減できる。 In FIG. 2, capacitor groups 51a and 51b are configured such that the electrodes on the wiring side of the capacitors are connected to the wirings 60-1 and 60-2 corresponding to the detected capacitors 42 and 43, respectively. The electrode is connected to an inversion pulse supply terminal having a phase opposite to that of the drive pulse through the switch group 52. Each capacitor takes an appropriate value or a weighted size, and a switch group is set by the SEL-C signal so that it becomes an average value of the detected capacitors 42 and 43. As a result, the charge amount corresponding to the common mode of the detected capacitors 42 and 43 can be offset by the charge amount of the capacitor groups 51a and 51b from the charge amount of the common mode of the detected capacitors 42 and 43. The size of the common mode output capacitors 65 and 66 of the input common mode feedback circuit 45 can be reduced, and the driving capability of the differential amplifier 69 can be suppressed, so that the circuit scale and power consumption can be reduced.
　図８に入力コモンモードフィードバック回路の変形例を示している。この入力コモンモードフィードバック回路の動作は、図３に示す入力コモンモードフィードバック回路４５と基本的に同様であるが、差動増幅器６９の代わりに演算相互コンダクタンス増幅器（ＯＴＡ：Operational Transconductance Amplifier）７０を用いている。演算相互コンダクタンス増幅器７０には出力を２つ設け、それぞれは全く同じ電流出力にすることにより、図３のコモンモード出力コンデンサ６５、６６を省略することができる。 Fig. 8 shows a modification of the input common mode feedback circuit. The operation of this input common mode feedback circuit is basically the same as that of the input common mode feedback circuit 45 shown in FIG. 3 except that an operational transconductance amplifier (OTA) 70 is used instead of the differential amplifier 69. ing. The common mode output capacitors 65 and 66 shown in FIG. 3 can be omitted by providing two outputs to the operational transconductance amplifier 70, each of which has the same current output.
　本出願は、２００９年５月１２日出願の特願２００９－１１５２０２に基づく。この内容は、全てここに含めておく。 This application is based on Japanese Patent Application No. 2009-115202 filed on May 12, 2009. All this content is included here.

Claims (6)

  1. 　駆動パルスが印加される一方端子が共通接続された第１及び第２の被検出容量と、
    　前記第１の被検出容量の他方端子に一端が接続された第１の配線と、
    　前記第２の被検出容量の他方端子に一端が接続された第２の配線と、
    　前記第１及び第２の配線が差動入力端子に接続され、前記第１及び第２の被検出容量に生じた容量差に対応して前記第１及び第２の配線上を移動する電荷を検出し、検出した電荷量を出力端子から差動電圧形式で出力する全差動増幅器と、
    　前記第１及び第２の配線の同相電圧を検出し、検出した同相電圧と基準電位とを等しくする出力電圧を、当該第１及び第２の配線へフィードバックするコモンモードフィードバック回路と、
    を具備したことを特徴とする静電容量検出回路。     A first and a second detected capacitance in which one terminal to which a drive pulse is applied is connected in common;
    A first wiring having one end connected to the other terminal of the first detected capacitor;
    A second wiring having one end connected to the other terminal of the second detected capacitor;
    The first and second wirings are connected to a differential input terminal, and charges that move on the first and second wirings corresponding to a capacitance difference generated in the first and second detected capacitors. A fully differential amplifier that detects and outputs the detected charge amount from the output terminal in a differential voltage format;
    A common mode feedback circuit that detects the common-mode voltage of the first and second wirings, and feeds back the output voltage that makes the detected common-mode voltage equal to the reference potential to the first and second wirings;
    A capacitance detection circuit comprising:
  2. 　前記コモンモードフィードバック回路は、前記第１の配線に一方端子が接続された第１の入力コンデンサと、前記第２の配線に一方端子が接続され前記第１の入力コンデンサと等しい容量を有する第２の入力コンデンサと、前記第１及び第２の入力コンデンサの他方端子の共通接続点が反転入力端子に接続され非反転入力端子に基準電圧が印加され前記第１及び第２の配線へフィードバックする出力電圧を出力するシングル出力の差動増幅器と、を具備したことを特徴とする請求項１記載の静電容量検出回路。 The common mode feedback circuit includes a first input capacitor having one terminal connected to the first wiring, and a second input capacitor connected to the second wiring and having a capacity equal to that of the first input capacitor. The common connection point between the other input capacitor and the other terminal of the first and second input capacitors is connected to the inverting input terminal, and a reference voltage is applied to the non-inverting input terminal to feed back to the first and second wirings. The capacitance detection circuit according to claim 1, further comprising a single output differential amplifier that outputs a voltage.
  3. 　前記コモンモードフィードバック回路は、一方端子が前記差動増幅器の出力端に接続され他方端子が前記第１の配線に接続された第１の出力コンデンサと、一方端子が前記差動増幅器の出力端に接続され他方端子が前記第２の配線に接続され前記第１の出力コンデンサと等しい容量を有する第２の出力コンデンサと、前記第１及び第２の入力コンデンサ並びに前記第１及び第２の出力コンデンサに対して並列に設けられ前記第１及び第２の被検出容量に駆動パルスを印加する直前に一端閉じて各々対応するコンデンサをリセットさせる複数のスイッチと、を具備したことを特徴とする請求項２記載の静電容量検出回路。 The common mode feedback circuit includes a first output capacitor having one terminal connected to the output terminal of the differential amplifier and the other terminal connected to the first wiring, and one terminal connected to the output terminal of the differential amplifier. A second output capacitor connected at the other terminal to the second wiring and having a capacity equal to that of the first output capacitor; the first and second input capacitors; and the first and second output capacitors And a plurality of switches that are provided in parallel to each other and close one end immediately before applying a drive pulse to the first and second capacitances to be detected, respectively, to reset the corresponding capacitors. 3. The capacitance detection circuit according to 2.
  4. 　前記第１の配線を前記全差動増幅器の一方の差動入力端子に接続すると共に前記第２の配線を前記全差動増幅器の他方の差動入力端子に接続する第１経路と、前記第１の配線を前記全差動増幅器の他方の差動入力端子に接続すると共に前記第２の配線を前記全差動増幅器の一方の差動入力端子に接続する第２経路と、に切替え可能な経路切替スイッチを備え、
    　前記全差動増幅器は、前記出力端子から極性の異なる差動入力端子へ差動電圧をそれぞれフィードバックする各フィードバック経路にそれぞれ設けられ当該差動電圧に応じた電荷量を蓄積する積分コンデンサと、前記各積分コンデンサに対して並列に設けられたリセットスイッチと備え、
    　前記経路切替スイッチは、駆動パルスの立ち上がりでは第１経路を選択し、当該駆動パルスの立ち下がりでは第２経路を選択するように経路切替えを行い、
    　前記全差動増幅器は、駆動パルスの立ち上がりと立下りの両方で前記積分コンデンサに電荷を蓄積し、積分回数が所定回数となったところで前記リセットスイッチを閉じて積分コンデンサをリセットすることを特徴とする請求項１記載の静電容量検出回路。     A first path connecting the first wiring to one differential input terminal of the fully-differential amplifier and connecting the second wiring to the other differential input terminal of the fully-differential amplifier; One wiring is connectable to the other differential input terminal of the fully-differential amplifier, and the second wiring can be switched to a second path that connects to one differential input terminal of the fully-differential amplifier. With a path switch,
    The total differential amplifier is provided in each feedback path that feeds back a differential voltage from the output terminal to a differential input terminal having a different polarity, respectively, and an integrating capacitor that accumulates a charge amount according to the differential voltage; With a reset switch provided in parallel to each integrating capacitor,
    The path changeover switch performs path switching so that the first path is selected at the rising edge of the drive pulse and the second path is selected at the falling edge of the drive pulse,
    The fully-differential amplifier accumulates electric charge in the integration capacitor both at the rising edge and the falling edge of the drive pulse, and closes the reset switch when the number of integration times reaches a predetermined number to reset the integration capacitor. The capacitance detection circuit according to claim 1.
  5. 　前記第１及び第２の配線に接続され、前記第１及び第２の被検出容量のコモンモード成分を相殺するコモンモード容量アレイを備えたことを特徴とする請求項１記載の静電容量検出回路。 2. The capacitance detection according to claim 1, further comprising a common mode capacitance array connected to the first and second wirings and canceling a common mode component of the first and second detected capacitances. circuit.
  6. 　前記コモンモード容量アレイは、前記第１又は第２の配線に一方端子がそれぞれ接続された複数のコンデンサからなるコンデンサ群と、前記コンデンサ群を構成する各コンデンサの他方端子にそれぞれ接続された複数のスイッチからなるスイッチ群とを備え、
    　前記スイッチ群を用いて前記第１及び第２の被検出容量のコモンモード成分に相当するキャンセル容量となる複数コンデンサを選択し、前記駆動パルスを反転させた反転パルスを前記スイッチ群を介して前記コンデンサ群の他方端子に印加することを特徴とする請求項５記載の静電容量検出回路。
     
          The common mode capacitor array includes a capacitor group composed of a plurality of capacitors each having one terminal connected to the first or second wiring, and a plurality of capacitors connected to the other terminal of each capacitor constituting the capacitor group. A switch group consisting of switches,
    Using the switch group, a plurality of capacitors having a canceling capacity corresponding to a common mode component of the first and second detected capacitors is selected, and an inverted pulse obtained by inverting the drive pulse is transmitted through the switch group. 6. The capacitance detection circuit according to claim 5, wherein the capacitance detection circuit is applied to the other terminal of the capacitor group.

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JP2015064899A (en) * 2011-07-12 2015-04-09 シャープ株式会社 Touch panel system and electronic apparatus
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