JP5842468B2 - Switched capacitor integration circuit, filter circuit, multi-output filter circuit, physical quantity measuring device, and electronic device - Google Patents

Description

The present invention relates to a switched capacitor integrating circuit, a filter circuit, a multi-output filter circuit, a physical quantity measuring device, an electronic device, and the like.

Conventionally, sensor circuits that measure physical quantities such as angular velocities (physical quantity measuring devices in a broad sense) have been used for camera shake correction, position information detection such as navigation and dead reckoning, and body movement detection such as motion analyzers. Used. In such a sensor circuit, for example, a filter circuit having a very low cut-off frequency is incorporated. For example, Patent Documents 1 to 3 include a switched capacitor (hereinafter referred to as SC).
A filter circuit comprising a circuit and having a very low cut-off frequency is disclosed. According to the filter circuits disclosed in Patent Documents 1 to 3, a filter circuit having an extremely low cutoff frequency can be realized with high accuracy without increasing the ratio between the input capacitance and the integration capacitance of the operational amplifier. .

By the way, the application of this type of sensor circuit is widened, and the sensor circuit is required to cope with fast movement and slow movement. Therefore, it is desired to output a plurality of detection signals having different gains and detection ranges to the sensor circuit. In view of this, it is conceivable to use a plurality of filter circuits disclosed in Patent Documents 1 to 3 so that multiple outputs are possible. However, when a plurality of filter circuits disclosed in Patent Documents 1 to 3 are used,
This causes problems such as an increase in area and current consumption due to integration, and a deviation in offset of operational amplifiers constituting each filter circuit.

In addition, this type of sensor circuit is required to reduce noise particularly in a low frequency band from the viewpoint of further high accuracy and high stability. For example, Non-Patent Document 1 and Non-Patent Document 2 disclose SC circuits that can reduce noise. Non-Patent Document 1 discloses a so-called correlated double-sampling (CDS) integrator. Non-Patent Document 2 discloses a so-called Capacitive-Reset Gain circuit.

JP 2009-200618 A JP 2010-177734 A JP 2010-177771 A

K.NAGARAJ, TRVISWANATHAN, K.SINGHAL, and J.VLACH, "Switched-Capacitor Circuits with ReducedSensitivity to Amplifier Gain", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL.CAS-34, No.5, pp.571-574 , May, 1987 H.MATSUMOTO, and W.WATANABE, "SPIKE-FREESWITCHED-CAPACITOR CIRCUITS", ELECTRONICS LETTERS, Vol.23, No.8, pp.428-429, 9th April, 1987

However, in the filter circuits disclosed in Patent Documents 1 to 3, Non-Patent Document 1
Even if the SC circuit disclosed in Non-Patent Document 2 is simply applied, there is a problem that the influence of noise in the low frequency band cannot be sufficiently reduced.

The present invention has been made in view of the above technical problems. According to some aspects of the present invention, there are provided a switched capacitor integration circuit, a filter circuit, a multi-output filter circuit, a physical quantity measurement device, an electronic device, and the like that can further reduce the influence of noise in a low frequency band. be able to.

(1) In the first aspect of the present invention, the switched capacitor integrating circuit includes a first capacitor and a second capacitor.
And a charge integration circuit that integrates the charge charged in the first capacitor, and the voltage charge conversion circuit is connected to the first capacitor in a first period. The charged charge is transferred, the charge corresponding to the input signal is charged in the second capacitor, and a part of the charge charged in the second capacitor is transferred to the first capacitor in the second period. And charging the first capacitor with a charge corresponding to the input signal, and the charge integrating circuit comprises:
An operational amplifier, an offset cancel capacitor having one end connected to the first input terminal of the operational amplifier, and the other end of the offset cancel capacitor and one end of the first capacitor are electrically connected in a third period And a second switch for connecting the other end of the offset cancel capacitor to the ground potential in the fourth period.

In this embodiment, an offset cancel capacitor is connected to the first input terminal of the operational amplifier, and the other end of the offset cancel capacitor is connected to one end of the first capacitor or grounded by the first switch and the second switch. It is designed to be electrically connected to the potential. That is, it is configured to be electrically cut off during a non-transfer period of charge from the voltage charge conversion circuit and to connect the other end of the offset cancel capacitor to the ground potential. As a result, the other end of the offset cancel capacitor can contribute to the integration operation even in the non-transfer period of charge, and the target charge can be charged in the offset cancel capacitor in the non-transfer period. As a result, it is possible to provide a switched capacitor integrating circuit that can realize a configuration that reliably cancels low-frequency component noise and that can further reduce the influence of low-frequency band noise.

(2) In the switched capacitor integrating circuit according to the second aspect of the present invention, in the first aspect, the charge integrating circuit includes an integrating capacitor having one end connected to the output terminal of the operational amplifier, and the third capacitor A third switch that electrically connects the other end of the integration capacitor and the first input terminal in a period; and a second switch of the integration capacitor and the other end of the offset cancellation capacitor in the fourth period. And a fourth switch that is electrically connected.

According to this aspect, by adding the switch and the fourth switch to the third, the influence of the noise in the low frequency band can be further reduced in the integration operation using the operational amplifier and the integration capacitor. Become.

(3) In the switched capacitor integration circuit according to the third aspect of the present invention, in the first aspect or the second aspect, the first period and the third period are defined based on a first clock. The second period and the fourth period are defined based on a second clock having a phase opposite to that of the first clock.

According to this aspect, it is possible to provide a switched-capacitor integrating circuit using a switch that is controlled to be turned on / off by one of two-phase clocks. As a result, it is possible to provide a switched capacitor integrating circuit capable of further reducing the influence of noise in the low frequency band with very simple control and configuration.

(4) In the third aspect, the switched capacitor integration circuit according to the fourth aspect of the present invention outputs an output signal of the charge integration circuit as an output of the switched capacitor integration circuit in the first period. Includes 5 switches.

According to this aspect, since the propagation of the output signal of the charge integration circuit in the second period can be suppressed, it is possible to provide a switched capacitor integration circuit that can further reduce the influence of noise in the low frequency band. It becomes like this.

(5) According to a fifth aspect of the present invention, the filter circuit includes a first switched capacitor integrating circuit and a second switched capacitor integrating circuit connected to the front side or the rear side of the first switched capacitor integrating circuit. A first feedback capacitor inserted into a feedback path of a switched capacitor integrating circuit on the front stage side from a switched capacitor integrating circuit on the rear stage side of the first switched capacitor integrating circuit and the second switched capacitor integrating circuit; It is initialized in the second period, and a second feedback capacitor provided in parallel with the first feedback capacitor in the first period, the first switched capacitor integrator circuit and the second At least one of the switched capacitor integrating circuits is a switched capacitor product according to the third aspect. It is a circuit.

According to this aspect, the function of the low-pass filter can be realized using the switched capacitor integration circuit having a configuration that reliably cancels the noise of the low-frequency component. This makes it possible to provide a filter circuit that can further reduce the influence of noise in the low frequency band.

(6) A filter circuit according to a sixth aspect of the present invention, in the fifth aspect, is inserted into a feedback path through the first feedback capacitor, and is conducted in the first period, and the second circuit And a fifth switch that is cut off during the period.

In this aspect, in the first period, the output signal of the switched capacitor integrating circuit on the rear stage side can be fed back to the front stage side via the first feedback capacitor. This makes it possible to provide a filter circuit that can further reduce the influence of noise in the low frequency band.

(7) A filter circuit according to a seventh aspect of the present invention includes the switched capacitor integrating circuit according to any one of the first to fourth aspects.

According to this aspect, it is possible to provide a filter circuit that can further reduce the influence of noise in the low frequency band.

(8) According to an eighth aspect of the present invention, the filter circuit includes a first switched capacitor integrating circuit and a correlated double sampling integrator, and is disposed on the subsequent stage side of the first switched capacitor integrating circuit. A switched capacitor integrating circuit for integrating charge in a first period; a feedback capacitor inserted between an output of the switched capacitor integrating circuit and a given node of the first switched capacitor integrating circuit; And a switch for electrically connecting the output of the switched capacitor integrating circuit and one end of the feedback capacitor.

In this aspect, the function of a low-pass filter can be realized by using a switched capacitor integration circuit having a configuration in which low-frequency component noise is canceled by a correlated double sampling integrator. Further, since only the output signal having a small noise component can be fed back by the switch, the influence of noise in the low frequency band can be further reduced. This makes it possible to provide a filter circuit that can further reduce the influence of noise in the low frequency band.

(9) According to a ninth aspect of the present invention, the filter circuit includes a first switched capacitor integrating circuit and a correlated double sampling integrator, and is disposed on the rear stage side of the first switched capacitor integrating circuit. A switched capacitor integrating circuit for integrating charge in a first period; a feedback capacitor inserted between an output of the switched capacitor integrating circuit and a given node of the first switched capacitor integrating circuit; And a switch for electrically connecting the node and one end of the feedback capacitor.

In this aspect, the function of a low-pass filter can be realized by using a switched capacitor integration circuit having a configuration in which low-frequency component noise is canceled by a correlated double sampling integrator. Further, since only the output signal having a small noise component can be fed back by the switch, the influence of noise in the low frequency band can be further reduced. This makes it possible to provide a filter circuit that can further reduce the influence of noise in the low frequency band.

(10) A filter circuit according to a tenth aspect of the present invention is a high-order filter circuit including the filter circuit according to any one of the fifth to ninth aspects.

According to this aspect, it is possible to provide a high-order filter circuit that can further reduce the influence of noise in the low frequency band.

(11) According to an eleventh aspect of the present invention, a multi-output filter circuit is connected to the filter circuit according to any one of the fifth to tenth aspects and the output of the filter circuit, and the output of the filter circuit And an attenuation circuit for attenuating.

According to this aspect, it is possible to provide a multi-output filter circuit that can further reduce the influence of noise in the low frequency band and can output a plurality of outputs with different gains.

(12) In a multi-output filter circuit according to a twelfth aspect of the present invention, in the eleventh aspect, the attenuation circuit includes an operational amplifier and one end electrically connected to an inverting input terminal of the operational amplifier. An input capacitor having one end, a first integration capacitor having one end electrically connected to the inverting input terminal of the operational amplifier, and a second integration capacitor having one end electrically connected to the output terminal of the operational amplifier. The other end of the first input capacitor is electrically connected to the output of the filter circuit in the first period, and the other end is electrically connected to the ground potential in the second period.
The other end of the first integration capacitor is electrically connected to a ground potential in the first period, and is electrically connected to an output terminal of the operational amplifier in the second period. The other end of the capacitor is electrically connected to the inverting input terminal in the first period, and the other end is electrically connected to the ground potential in the second period.

According to this aspect, it is possible to provide a multi-output filter circuit capable of suppressing output of noise from the operational amplifier in the attenuation circuit and capable of output that further reduces the influence of noise in a low frequency band.

(13) In a thirteenth aspect of the present invention, the physical quantity measurement device includes a vibrator, a drive circuit that forms an oscillation loop with the vibrator, and excites drive vibration in the vibrator; And a detection circuit that outputs a first detection signal and a second detection signal in accordance with a drive vibration excited by the vibrator and a physical quantity to be measured. the detection circuit outputs the output of the full I Luther circuit as said first detection signal, and outputs the output of the damping circuit as the second detection signal.

According to this aspect, it is possible to provide a physical quantity measuring device that outputs a plurality of detection signals having different gains and detection ranges while further reducing the influence of noise in a low frequency band.

(14) In a fourteenth aspect of the present invention, the electronic device includes the switched capacitor integrating circuit according to any one of the first to fourth aspects.

According to this aspect, it is possible to provide an electronic apparatus to which a switched capacitor integration circuit that further reduces the influence of noise in a low frequency band is applied.

(15) In a fifteenth aspect of the present invention, the electronic device includes the physical quantity measuring device according to the thirteenth aspect.

According to this aspect, it is possible to provide an electronic device capable of sensing based on outputs of a plurality of detection signals having different gains and detection ranges while further reducing the influence of noise in the low frequency band. .

The circuit diagram of the example of composition of the SC integration circuit concerning one embodiment of the present invention. FIG. 2A is an operation explanatory diagram of the SC integration circuit of FIG. 1 in the first period. FIG. 2B is an operation explanatory diagram of the SC integration circuit of FIG. 1 in the second period. The circuit diagram of the structural example of the SC integration circuit in the comparative example of this embodiment. The figure which shows an example of the calculation result and simulation result of NTF of the SC integration circuit 10 of FIG. 1 and the SC integration circuit of FIG. The circuit diagram of the example of composition of the secondary LPF to which the SC integration circuit of this embodiment is applied. The circuit diagram of the structural example of the secondary LPF in the comparative example of this embodiment. FIG. 7A is a diagram illustrating an example of a simulation result of noise transfer characteristics from the operational amplifier AMP1. FIG. 7B is a diagram illustrating an example of a simulation result of noise transfer characteristics from the operational amplifier AMP2. The circuit diagram of the example of composition of the multiple output filter circuit in this embodiment. FIG. 9 is a circuit diagram of a configuration example of the attenuation circuit in FIG. 8. FIG. 10A is an operation explanatory diagram of the attenuation circuit in the first period. FIG. 10B is an operation explanatory diagram of the attenuation circuit in the second period. FIG. 11A is a diagram illustrating an example of a simulation result of noise transfer characteristics from the operational amplifier AMP1. FIG. 11B is a diagram illustrating an example of a simulation result of noise transfer characteristics from the operational amplifier AMP2. FIG. 11C is a diagram illustrating an example of a simulation result of noise transfer characteristics from the operational amplifier AMP3. The circuit diagram of the example of composition of the secondary LPF in the 1st modification of this embodiment. The circuit diagram of the example of composition of the secondary LPF in the 2nd modification of this embodiment. FIG. 14A is a diagram illustrating an example of noise transfer characteristics from the operational amplifier AMP1. FIG. 14B is a diagram showing an example of noise transfer characteristics from the operational amplifier AMP2. The circuit diagram of the example of composition of the secondary LPF in the 3rd modification of this embodiment. The circuit diagram of the example of composition of the secondary LPF in the 4th modification of this embodiment. FIG. 17A shows an example of noise transfer characteristics from the operational amplifier AMP1. FIG. 14B is a diagram showing an example of noise transfer characteristics from the operational amplifier AMP2. The circuit diagram of the example of composition of the secondary LPF in the 5th modification of this embodiment. FIG. 19A is a diagram illustrating an example of noise transfer characteristics from the operational amplifier AMP1. FIG. 19B is a diagram showing an example of noise transfer characteristics from the operational amplifier AMP2. The circuit diagram of the example of composition of the secondary LPF in the 6th modification of this embodiment. FIG. 21A shows an example of noise transfer characteristics from the operational amplifier AMP1. FIG. 21B is a diagram illustrating an example of noise transfer characteristics from the operational amplifier AMP2. The figure which shows the structural example of the sensor circuit which has the multiple output filter circuit to which LPF in this embodiment or its modification was applied. 1 is a block diagram of a hardware configuration example of an electronic device according to an embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, all of the configurations described below are not necessarily indispensable configuration requirements for solving the problems of the present invention.

[SC integration circuit]
FIG. 1 shows a circuit diagram of a configuration example of an SC integration circuit according to an embodiment of the present invention.
The SC integration circuit 10 in this embodiment includes a voltage / charge conversion circuit 20 and a charge integration circuit 30.
And. The SC integration circuit 10 can include an output switch SWz. An input voltage Vin as an input signal is input to the voltage charge conversion circuit 20, and the input voltage V
Convert to charge corresponding to in. The charge integration circuit 30 integrates the charge converted by the voltage charge conversion circuit 20. When the output switch SWz is controlled to be on, the charge integrating circuit 3
The output signal of 0 is output as the output voltage Vout that is the output of the SC integration circuit 10. The output switch SWz electrically cuts off the output of the charge integration circuit 30 and the output of the SC integration circuit 10 when controlled to be off.

The voltage to charge conversion circuit 20 includes a first input capacitor C ₁ (first capacitor) and a second input capacitor C _2.
(Second capacity). In the first period T1, the voltage-charge conversion circuit 20 transfers the charge charged in the _first input capacitor C1 to the charge integration circuit 30, and at the same time the input voltage Vi.
charging a charge corresponding to n to a second input capacitance C _2. The voltage charge conversion circuit 20 includes a second
In the period T2, the input capacitance C ₁ part a first charge which is charged to the second input capacitance C ₂
Which charges a to charge the electric charge corresponding to the input voltage Vin to the first input capacitance C _1. Here, the second period T2 is a period following the first period T1.

The charge integrating circuit 30 includes an operational amplifier AMP and one end of the inverting input terminal (
Offset cancel capacitor Coff connected to the first input terminal) and the first switch S
W1 and a second switch SW2 are provided. In the charge integration circuit 30, in the third period T3, the first switch SW1 is connected to the other end of the offset cancel capacitor Coff (node N
D) and electrically connects the first end of the input capacitor C _1. In the fourth period T4, the second switch SW2 electrically connects the other end of the offset cancel capacitor Coff to the ground potential. Here, the third period T3 is a period following the second period T2, and the fourth period T4 is a period following the third period T3.

The output switch SWz (fifth switch) is inserted between the output terminal of the operational amplifier AMP and the output terminal of the SC integration circuit 10. The output switch SWz electrically connects the output terminal of the operational amplifier AMP to the output terminal of the SC integration circuit 10 in the third period T3.

Such voltage charge conversion circuit 20 may comprise a first input capacitance _{C 1} and the second addition to the switch SWa~SWf input capacitance _{C 2.} Switch SWa~SWf switches the first input capacitance _{C 1} and the second connection of the input capacitance _{C 2.} The switches SWa to SWf are each turned on / off by one of the two-phase clocks. There are two types of switches constituting the voltage-charge conversion circuit 20 of FIG. 1, a switch denoted by “1” and a switch denoted by “2”. The switch denoted by “1” is a switch (first phase switch) that operates when the first clock CLK1 is at the H level (first period). “2
Is a switch (second phase switch) that operates when the second clock CLK2 having a phase opposite to that of the first clock CLK1 is at the H level (second period).

In FIG. 1, the switch SWa is inserted between the input terminal to which the input voltage Vin is input and the other end of the _first input capacitor C1. Switch SWb is inserted between the first and the other end to the ground potential of the input capacitance C ₁ (ground point). The switch SWc has an input terminal and a second input capacitance C
Between one end of the _two . Switch SWd is inserted between the second end and the ground potential of the input capacitance C _2. The switch SWe includes one end of the _first input capacitor C1 and the second input capacitor C1.
₂ is inserted between the other end. Switch SWf is inserted between the second and the other end to the ground potential of the input capacitance C _2.

In addition to the operational amplifier AMP, the offset cancellation capacitor Coff, the first switch SW1, and the second switch SW2, the charge integration circuit 30 includes an integration capacitor Cs and a third switch S.
W3 and a fourth switch SW4 can be provided. One end of the integration capacitor Cs is connected to the output terminal of the operational amplifier AMP. The third switch SW3 electrically connects the other end of the integration capacitor Cs and the other end of the offset cancellation capacitor Coff in the third period T3.
The fourth switch SW4 includes the other end of the integration capacitor Cs and the operational amplifier AM in the fourth period T4.
Electrically connected to the inverting input terminal of P.

The first switch SW1 to the fourth switch SW4 are on / off controlled by either one of the two-phase clocks. Each switch constituting the charge integration circuit 30 of FIG.
There are two types of switches, “switch” and “4”. The switch denoted by “3” is a switch (third phase switch) that operates when the third clock CLK3 is at the H level (third period). The switch denoted by “4” is a switch (fourth phase switch) that operates when the fourth clock CLK4 having a phase opposite to that of the third clock CLK3 is at the H level (fourth period). The third period T3 is a period in which the first clock CLK1 is at an H level, and the fourth period T4 is a period in which the second clock CLK2 is at an H level, so that the first clock CLK1 and the second clock SC integration operation can be realized only with CLK2. Therefore, in the following description, T1 = T3 and T2 = T4 will be described.

2A and 2B are diagrams for explaining the operation of the SC integration circuit 10 shown in FIG. FIG. 2 (A)
Represents an outline of the configuration of the SC integration circuit in the first period T1. FIG. 2B shows an outline of the configuration of the SC integration circuit in the second period T2. In FIGS. 2A and 2B,
The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

Voltage charge conversion circuit 20, as shown in FIG. 2 (A), in the first period T1, and transfers the electric charge charged in the first input capacitor C ₁ to charge the integrating circuit 30 at that time. At this time,
The second input capacitance _{C 2} input voltage Vin is applied, the input voltage Vi to the second input capacitance _{C 2}
Charge corresponding to n is charged. Then, in the second period T2, as shown in FIG. 2 (B), the input capacitance C ₂ of the first input capacitor C ₁ and the second are connected in series, it is charged to the second input capacitance C ₂ part of the charge has to be charged to the first input capacitance C _1. At this time, the first input capacitance C
Also _1, the charge corresponding to the input voltage Vin is charged to the first input capacitance C _1. Thereafter, again, the configuration shown in FIG. 2A is obtained, and the charge charged in the _first input capacitor C ₁ is transferred to the charge integration circuit 30.

In this way, the voltage charge conversion circuit 20 transfers only a part of the charge charged in the input capacitor, and keeps the remaining charge in the voltage charge conversion circuit 20. As a result, the amount of charge transferred to the charge integration circuit 30 is reduced. As a result, this corresponds to the reduction of the amount of charge passing through the voltage charge conversion circuit 20, and the capacity can be made smaller when the voltage charge conversion circuit 20 is considered as a whole.
Therefore, apparently smaller capacity can be realized with high accuracy by using a capacity with a margin without using an extremely small size capacitor. Therefore, according to the SC integrating circuit 10, to very low cut-off frequency, the ratio of the integration capacitance Cs of the first input capacitor C ₁ and the second input capacitor C ₂ and an operational amplifier AMP the (element coefficient) It can be realized with high accuracy without increasing the size.

In the charge integration circuit 30, the voltage V1 applied across the offset cancellation capacitor Coff does not change during the transition from the second period T2 to the first period T1. That is,
Similar to the CDS integration circuit disclosed in Non-Patent Document 1, the charge integration circuit 30 first charges the offset cancellation capacitor Coff with the noise charge corresponding to the offset voltage and noise of the operational amplifier AMP in the second period T2. . Thereafter, the charge integration circuit 30 performs the first period T1.
The voltage corresponding to the noise charge is canceled during the integration operation. Thus, the influence of the offset voltage of the operational amplifier AMP can be eliminated in the integration operation by the charge integration circuit 30.

Further, the charge integration circuit 30 includes a first switch SW1 and a second switch SW2,
In the non-transfer period of charge from the voltage charge conversion circuit 20, it is electrically cut off, and the other end (node ND) of the offset cancel capacitor Coff is connected to the ground potential. As a result, in the CDS integrating circuit disclosed in Non-Patent Document 1, the node ND for simply repeating charge transfer and grounding can contribute to the integration operation even during the charge non-transfer period. Furthermore, the target charge can be charged in the offset cancel capacitor Coff during the non-transfer period. As a result, it is possible to realize a configuration that reliably cancels low-frequency component noise.

Here, the transfer function of the SC integration circuit 10 in FIG. 1 will be described with reference to a comparative example of the present embodiment. In the following, for convenience of explanation, the capacitance value of the second input capacitance C ₂ is assumed equal to the first capacitance value of the input capacitance C _1.

FIG. 3 shows a circuit diagram of a configuration example of the SC integration circuit in the comparative example of the present embodiment. FIG.
1 is a circuit diagram of an SC integration circuit having a configuration in which an offset cancel capacitor Coff and the like are omitted in the SC integration circuit 10 of FIG. In FIG. 3, the same parts as those in FIG.

The configuration of the SC integration circuit 10a in this comparative example is different from the configuration of the SC integration circuit 10 shown in FIG. 1 in that the switches SW1 to SW4, the offset cancellation capacitor Coff, and the output switch SWz are omitted, and the switch SWg is added. Is a point. The signal transfer function (Signal Transfer Functi) to the output of the input voltage Vin of the SC integration circuit 10a having such a configuration.
on: STF) and the noise transfer function (Noise Tr) to the noise output by the operational amplifier AMP
ansfer Function: NTF) is given by the following equation.

On the other hand, the STF to the output of the input voltage Vin of the SC integration circuit 10 shown in FIG. 1 and the NTF to the noise output by the operational amplifier AMP are given by the following equations. In addition, Formula (2
) Represents STF and NTF in the first period T1. As described above, the charge integration circuit 30 includes the offset cancel capacitor Co in the second period T2 (fourth period T4).
The noise charge is charged to ff, and the voltage corresponding to the noise charge is canceled in the first period T1 (third period T3). For this reason, the voltage corresponding to the noise charge can be canceled only in the first period T1 (third period T3). Therefore, Expression (2) represents only the STF and NTF in the first period T1 (third period T3), and the STF and NTF in the second period T2 (fourth period T4) in which a correct output cannot be obtained. Is not considered.

Comparing Equation (1) and Equation (2), the smaller the Coff / Cs in Equation (2), the more noise transmission can be reduced, and (1-z ^−1/2 ) is 0 in the lower frequency band. Represents approaching. That is, according to the charge integration circuit 30, it is possible to reduce the low-frequency component of noise generated in the operational amplifier AMP, and to integrate the capacitance C of the offset cancellation capacitance Coff.
The influence of noise can be further reduced by increasing the capacitance value of s.

FIG. 4 shows an example of NTF calculation results and simulation results of the SC integration circuit 10 of FIG. 1 and the SC integration circuit 10a of FIG. In FIG. 4, the horizontal axis represents frequency and the vertical axis represents noise level.
4, the NTF calculation result (S1 in FIG. 4) of the SC integration circuit 10 in FIG. 1 is represented by a solid line, and the simulation result is represented by a point. In FIG. 4, the SC integration circuit 10 of FIG.
The NTF calculation result (S2 in FIG. 4) of a is represented by a broken line, and the simulation result is represented by a point.

4, the capacitance value of the first input capacitance C ₁ in FIG. 1 or FIG. 3 is 0.1 pF, the capacitance value of the second input capacitance C ₂ is 0.1 pF, and the capacitance value of the offset cancellation capacitance Coff is 0. 1
The capacitance value of pF and integral capacitance Cs is calculated as 4.014 pF. As shown in FIG.
S1 has a lower noise level in the lower frequency band. According to the SC integration circuit 10 in FIG.
Low frequency components of noise generated by the operational amplifier AMP can be reduced.

[Second-order low-pass filter]
By applying the SC integration circuit 10 of the present embodiment, a second-order low-pass filter (hereinafter referred to as “low pass filter”) that can further reduce the influence of noise particularly in the low frequency band.
LPF) can be provided.

FIG. 5 shows a circuit diagram of a configuration example of a secondary LPF to which the SC integration circuit 10 of the present embodiment is applied.
The LPF 100 includes a first SC integration circuit 110, a second SC integration circuit 120, a first feedback capacitor CR1, and a second feedback capacitor CR2. Each of the first SC integration circuit 110 and the second SC integration circuit 120 has the same configuration as the SC integration circuit 10 of FIG. 1 (however, the configuration in which the output switch SWz is omitted), and the first SC integration circuit 110 The integration circuit 110 performs an integration operation in a phase opposite to that of the second SC integration circuit 120. That is, the LPF 100 includes a first SC integration circuit,
A second SC integration circuit, a feedback capacitor, and an output switch can be provided. Here, the second SC integration circuit has a CDS integrator and is arranged on the rear stage side of the first SC integration circuit.
The charge is integrated over the period of. The feedback capacitor is inserted between the output of the second SC integrator and a given node of the first SC integrator. The output switch electrically connects the output of the second SC integration circuit and one end of the feedback capacitor in the first period.

Specifically, the switches SWa1 and SWa2 correspond to the switch SWa. Switch S
Wb1 and SWb2 correspond to the switch SWb. The switches SWc1 and SWc2 correspond to the switch SWc. The switches SWd1 and SWd2 correspond to the switch SWd. The switches SWe1 and SWe2 correspond to the switch SWe. Switch SWf1, SWf2
Corresponds to the switch SWf. The first input capacitances C ₁ 1 and C ₁ 2 are the first input capacitances C ₁
Corresponding to The capacitance value of the first input capacitor C ₁₁ is kG (k is a gain). The capacitance value of the first input capacitance C ₁₂ is A. The second input capacitance C ₂ 1, C ₂ 2 is the second input capacitance C 2
Corresponds to ₂ . The capacitance value of the second input capacitor C ₂ 1 is kG. The second capacitance value of the input capacitance _{C 2} 2, is A. The switches SW11 and SW12 correspond to the switch SW1. The switches SW21 and SW22 correspond to the switch SW2. The switches SW31 and SW32 correspond to the switch SW3. The switches SW41 and SW42 correspond to the switch SW4. The integration capacitors Cs1 and Cs2 correspond to the integration capacitor Cs. The capacitance value of the integration capacitor Cs1 is
D. The capacitance value of the integration capacitor Cs2 is B. The operational amplifiers AMP1 and AMP2 correspond to the operational amplifier AMP.

The first feedback capacitor CR1 has a capacitance value E, and one end is connected to the output terminal of the operational amplifier AMP2 constituting the second SC integration circuit 120 via the output switch SWz (fifth switch). . The other end of the first feedback capacitor CR1 is connected to one end of an integration capacitor Cs1 constituting the first SC integration circuit 110. The output switch SWz is turned on in the first period T1, and is turned off in the second period T2. That is, the output switch SWz is in the first period T
1, the output terminal of the second SC integrating circuit 120 is electrically connected to one end of the first feedback capacitor CR1. Further, the output switch SWz electrically cuts off one end of the first feedback capacitor CR1 and the output terminal of the second SC integration circuit 120 in the second period T2.

The second feedback capacitor CR2 has a capacitance value C, the charge amount is initialized in the second period T2, and is provided in parallel with the first feedback capacitor CR1 in the first period T1. Therefore, L
The PF 100 includes one end of the second feedback capacitor CR2 and the operational amplifier AM in the first period T1.
A switch that electrically connects the output terminal of P2 and a switch that electrically connects one end of the second feedback capacitor CR2 and the ground potential in the second period T2 are provided. LPF
The switch 100 electrically connects the other end of the second feedback capacitor CR2 and one end of the integration capacitor Cs1 in the first period T1, and the other end of the second feedback capacitor CR2 in the second period T2. And a switch for electrically connecting to the ground potential.

  Here, the LPF 100 of FIG. 5 will be described with reference to a comparative example of the present embodiment.

FIG. 6 shows a circuit diagram of a configuration example of the secondary LPF in the comparative example of the present embodiment. FIG.
First SC integration circuit 110 and second SC integration circuit 120 constituting LPF 100 of FIG.
Each represents an LPF constituted by the SC integration circuit 10a of FIG. In FIG. 6, the corresponding capacity in FIG. 5 is assumed to have the same capacity value.

The S to the output of the input voltage Vin of the LPF 190 in this comparative example having the configuration shown in FIG.
TF is the same as STF to the output of the input voltage Vin of the LPF 100 shown in FIG. 5, and is given by the following equation.

On the other hand, the noise transfer characteristic from each operational amplifier constituting the LPF changes as follows.

7A and 7B show examples of simulation results of the LPF 100 in FIG. 5 and the LPF 190 in FIG. FIG. 7A shows an example of the simulation result of the noise transfer characteristic from the operational amplifier AMP1. FIG. 7B shows an example of the simulation result of the noise transfer characteristic from the operational amplifier AMP2. 7A and 7B, the horizontal axis represents frequency, and the vertical axis represents noise level. 7A and 7B, the simulation result (S3) of the LPF 100 of FIG. 5 is represented by a solid line, and the simulation result of the LPF 190 of FIG. 6 (S4).
Is represented by a broken line. 7A and 7B, A = C−G = in FIGS. 5 and 6.
0.1 pF, B = D = 4.014 pF, E = 5.067 pF, k = 4.52 (= 13.1
dB), T = 1 / 50000s , cut-off frequency fc = 200 ^Hz, is calculated as ^{Q = 2 -1/2.}

As shown in FIG. 7A, the noise from the operational amplifier AMP1 to which the signal fed back from the operational amplifier AMP2 and the noise included in the input voltage Vin are input is reduced in the low frequency band. Further, as shown in FIG. 7B, the noise from the operational amplifier AMP2 decreases in the low frequency band. Therefore, according to the LPF 100 of FIG. 5, it is possible to reduce the low frequency component of the noise generated in each operational amplifier constituting the secondary LPF. Thereby, it becomes possible to contribute to higher accuracy and higher stability of the LPF.

[Multi-output filter circuit]
In a sensor circuit to which the above-described filter circuit such as LPF is applied, a plurality of detection signals having different gains and detection ranges can be output without causing an increase in area and current consumption, a difference in offset between a plurality of operational amplifiers, and the like. Is desired. Therefore, in the present embodiment, by using the filter circuit (SC integration circuit) described above, a multi-output filter circuit is configured as follows.
A plurality of detection signals having different gains and detection ranges are output. As a result, it is possible to provide a multi-output filter circuit that outputs a plurality of detection signals without causing an increase in area or current consumption, a difference in offset between a plurality of operational amplifiers, or the like. Hereinafter, an example in which two types of detection signals are output will be described, but the same applies to the case where three or more types of detection signals are output.

FIG. 8 shows a circuit diagram of a configuration example of the multi-output filter circuit in the present embodiment. 8, parts similar to those in FIG. 5 are given the same reference numerals, and description thereof will be omitted as appropriate.

The multi-output filter circuit 200 in the present embodiment includes the LPF 100 of FIG. The input of the attenuation circuit 300 is the output terminal (OUT1) of the LPF 100.
To attenuate the output of the LPF 100. This multi-output filter circuit 200 includes 1
Two types of first detection signal Vout1 and second detection signal Vout2 are output in response to the type of input signal (Vin). Specifically, the multi-output filter circuit 200 includes an LPF 100.
Is output as the first detection signal Vout1, and the output voltage of the attenuation circuit 300 having the first detection signal Vout1 as an input is output as the second detection signal Vout2.

By configuring the attenuation circuit 300 with the following Capacitive-Reset Gain circuit, noise transmission from the operational amplifier constituting the attenuation circuit 300 can be suppressed. In particular, noise transmission to the output terminal that is output as the second detection signal Vout2 in the low frequency band can be significantly suppressed. In FIG. 8, for example, Capacitive-Reset Gain in the second period T2.
The circuit outputs with reduced noise. Therefore, the multi-output filter circuit 200 includes an attenuation circuit 3
00 output to the output capacitance Cou via the switch SWx1 as the second phase switch
One end of t is connected to hold the potential of the second detection signal Vout2.

FIG. 9 shows a circuit diagram of a configuration example of the attenuation circuit 300 of FIG. In FIG. 9, the switches are represented in the same manner as in FIG.

The attenuation circuit 300 includes an operational amplifier AMP3, an input capacitor Cg1 (first input capacitor), an integration capacitor Cg2 (first integration capacitor), and Cg3 (second integration capacitor).
et Gain circuit. One end of the input capacitor Cg1 is electrically connected to the inverting input terminal of the operational amplifier AMP3. The other end of the input capacitor Cg1 is electrically connected to the output of the LPF 100 in the first period T1, and is electrically connected to the ground potential in the second period T2. One end of the integration capacitor Cg2 is electrically connected to the inverting input terminal of the operational amplifier AMP3. The other end of the integration capacitor Cg2 is electrically connected to the ground potential in the first period T1, and the second period T2
Are electrically connected to the output terminal of the operational amplifier AMP3. One end of the integration capacitor Cg3 is electrically connected to the output terminal of the operational amplifier AMP3. The other end of the integration capacitor Cg3 is the first
Is electrically connected to the inverting input terminal of the operational amplifier AMP3 in the period T1, and is electrically connected to the ground potential in the second period T2. The attenuation circuit 300 shown in FIG.
The switches SWr1 to SWr6 are provided so that the charging and discharging of the charges to the g1 and the integrating capacitors Cg2 and Cg3 are performed as described above, and each switch operates as a phase switch as shown in FIG.

FIGS. 10A and 10B are diagrams for explaining the operation of the attenuation circuit 300 in FIG. FIG.
A) shows an outline of the configuration of the attenuation circuit 300 in the first period T1. FIG. 10 (B)
An outline of the configuration of the attenuation circuit 300 in the second period T2 is shown. FIG. 10A and FIG.
In B), it is assumed that a noise source that generates the noise voltage Vn of the operational amplifier AMP3 is connected to the non-inverting input terminal of the operational amplifier AMP3, and the same parts as in FIG. To do.

In the attenuation circuit 300, as shown in FIG. 10A, the charge corresponding to the noise voltage Vn is charged in the input capacitor Cg1 in the first period T1. The amount of charge charged in the input capacitor Cg1 does not change even in the second period T2 shown in FIG. Accordingly, the voltage at the other end of the integrating capacitor Cg2 whose one end is connected to the input capacitor Cg1 (the inverting input terminal of the operational amplifier AMP3) is lowered by the noise voltage Vn. In the second period T2, since the other end of the integration capacitor Cg2 is connected to the output terminal of the operational amplifier AMP3, the output voltage of the operational amplifier AMP3 is lowered by the noise voltage Vn, and the influence of the noise voltage is not reflected on the output.

The STF of the attenuating circuit 300 is configured such that the voltage at the output terminal OUT1 of the LPF 100 (the input terminal of the attenuating circuit 300) OUT1 is Vout1, and the voltage at the output terminal OUT2 of the attenuating circuit 300 is Vo.
Assuming ut2, the following equation is obtained.

On the other hand, NTF is expressed as follows.

In Equation (5), z ^−1/2 approaches 1 in the low frequency band, and therefore, noise transmission from the operational amplifier constituting the attenuation circuit 300 is suppressed in the low frequency band, and the output terminal OUT
It shows that noise transmission to 2 can be greatly suppressed.

FIGS. 11A, 11B, and 11C show examples of simulation results of the multi-output filter circuit 200 of FIG. FIG. 11A shows an example of the simulation result of the noise transfer characteristic from the operational amplifier AMP1 constituting the multi-output filter circuit 200. FIG. FIG. 11B shows an example of a simulation result of noise transfer characteristics from the operational amplifier AMP2 constituting the multi-output filter circuit 200. FIG. 11C shows a multi-output filter circuit 2
An example of the simulation result of the noise transfer characteristic from the operational amplifier AMP3 constituting 00 is shown. 11A to 11C, the horizontal axis represents frequency and the vertical axis represents noise level.

11A and 11B, the noise transfer characteristic (S
5) is represented by a solid line, and the noise transfer characteristic (S6) at the output terminal OUT2 is represented by a broken line. FIG.
1 (C), the output terminal OU when the attenuation circuit 300 is realized by a known resistance dividing circuit.
The noise transfer characteristic (S8) at T2 is indicated by a broken line, and the noise transfer characteristic (S7) at the output terminal OUT2 when the attenuation circuit 300 is realized by the configuration of FIG. 9 is indicated by a solid line. In FIGS. 11A to 11C, the value of each element is the same as in FIGS. 7A and 7B.
The input capacitance Cg1 and the integration capacitance Cg3 in the attenuation circuit 300 so as to be −13.1 dB.
It is assumed that the value of is adjusted.

As shown in FIGS. 11A to 11C, the first detection signal Vout1 and the second detection signal Vout2 output from the output terminals OUT1 and OUT2 are at least operational amplifiers AMP2, as the frequency becomes lower. The noise component from AMP3 is reduced. Therefore, when outputting a plurality of detection signals having different gains, the influence of noise in the low frequency band can be further reduced without causing an increase in area or current consumption, a difference in offset between a plurality of operational amplifiers, or the like. A multi-output filter circuit capable of being provided can be provided.

[First Modification]
In the LPF 100 and the multi-output filter circuit 200 of the present embodiment, the output switch SWz is inserted at the position shown in FIG. 5, but the present embodiment is not limited to the insertion position of the output switch SWz.

FIG. 12 shows a circuit diagram of a configuration example of the secondary LPF in the first modification of the present embodiment.
12, parts similar to those in FIG. 5 are given the same reference numerals, and description thereof will be omitted as appropriate.

The LPF 100a in the first modification is different from the LPF 100 shown in FIG. 5 in the insertion position of the output switch as the fifth switch. In the first period T1, the LPF 100a includes one end of the integration capacitor Cs1 constituting the first SC integration circuit 110 and the first feedback capacitor C.
An output switch SWza (fifth) for electrically connecting the other end of R1 together with the switch SW41.
Switch). The output switch SWza electrically cuts off the other end of the first feedback capacitor CR1 and one end of the integration capacitor Cs1 in the second period T2. That is, the LPF 100a can include a first SC integration circuit, a second SC integration circuit, a feedback capacitor, and an output switch. Here, the second SC integration circuit has a CDS integrator and is arranged on the rear stage side of the first SC integration circuit, and integrates the charge in the first period. The feedback capacitor is inserted between the output of the second SC integrator and a given node of the first SC integrator. The output switch electrically connects the node and one end of the feedback capacitor in the first period.

When the values of the respective elements are set in the same manner as the LPF 100, the LPF 100a in the first modification example.
The simulation results are the same as those in FIGS. 7A and 7B. Therefore, also in the first modification, the noise from the operational amplifier AMP1 to which the signal fed back from the operational amplifier AMP2 or the noise included in the input voltage Vin is input is reduced in the low frequency band.
Further, the noise from the operational amplifier AMP2 decreases in the low frequency band. Therefore,
According to the LPF 100a in the first modified example, it is possible to reduce the low-frequency component of the noise generated by the operational amplifier constituting the secondary LPF. Thereby, it becomes possible to contribute to higher accuracy and higher stability of the LPF.

[Second Modification]
In the LPF 100 of the present embodiment or the LPF 100a of the second modification, the output switch SW
z or the output switch SWza is provided, and the output of the second SC integration circuit 120 is fed back to the first SC integration circuit 110 only in the first period T1. However, the present embodiment is not limited to this.

FIG. 13 shows a circuit diagram of a configuration example of the secondary LPF in the second modification of the present embodiment.
In FIG. 13, the same parts as those in FIG.

The LPF 100b in the second modification is different from the LPF 100 shown in FIG. 5 in that the output switch as the fifth switch is omitted. That is, in the LPF 100b, one end of the integration capacitor Cs1 and the other end of the first feedback capacitor CR1 are electrically connected, and one end of the first feedback capacitor CR1 and the output terminal of the operational amplifier AMP2 are electrically connected. The

FIG. 14A and FIG. 14B show an example of the simulation result of the LPF 100b in the second modification. FIG. 14A shows an example of a noise transfer characteristic from the operational amplifier AMP1 when the value of each element is set similarly to the LPF 100a. FIG. 14B shows an example of the noise transfer characteristic from the operational amplifier AMP2 when the value of each element is set in the same manner as the LPF 100a. 14A and 14B, the horizontal axis represents frequency, and the vertical axis represents noise level.

In FIG. 14A, the noise transfer characteristic (S10) from the operational amplifier AMP1 in the LPF 100a is represented by a broken line, and the noise transfer characteristic (S9) from the operational amplifier AMP1 in the LPF 100b is represented by a solid line. In FIG. 14B, the noise transfer characteristic from the operational amplifier AMP2 in the LPF 100a is represented by a broken line, and the noise transfer characteristic from the operational amplifier AMP2 in the LPF 100b is represented by a solid line. As shown in FIGS. 14A and 14B, the noise component is reduced in the low frequency band even when the configuration in which the output switch is omitted is employed (see FIG. 14B). This indicates that the effect obtained only by applying the SC integration circuit 10 of FIG. 1 to each SC integration circuit, and the LPF 100 in the second modification example.
According to b, it is possible to reduce the low-frequency component of the noise generated by the operational amplifier constituting the secondary LPF. Thereby, it becomes possible to contribute to higher accuracy and higher stability of the LPF.

[Third Modification]
In the LPF 100 of the present embodiment, the first SC integration circuit 110 and the second SC integration circuit 1
Although the SC integration circuit of FIG. 1 is applied to both of the number 20, the present embodiment is not limited to this.

FIG. 15 shows a circuit diagram of a configuration example of the secondary LPF in the third modification of the present embodiment.
In FIG. 15, the same parts as those in FIG.

The point that the LPF 100c in the third modification differs from the LPF 100 of the present embodiment is that the first
This is the configuration of the SC integration circuit. Specifically, the LPF 100c includes the first SC integration circuit 11
Instead of 0, a first SC integrator 110 having the same configuration as the SC integrator 10a of FIG.
a. That is, the LPF 100c includes the SC integration circuit 10a of FIG. 3 as the SC integration circuit on the front stage side, and the SC integration circuit 10 of FIG. The LPF 100c includes a first feedback capacitor CR1 and a second feedback capacitor CR2 like the LPF 100.

When the values of the respective elements are set in the same manner as the LPF 100, the LPF 100c in the third modification example is set.
As a result of the simulation, the noise transfer characteristic from the operational amplifier AMP1 is LPF19 in FIG.
The noise transfer characteristic from the operational amplifier AMP2 is the same as that in FIG. 7B. Therefore, also in the third modification, the noise from the operational amplifier AMP2 decreases in the low frequency band. Therefore, according to the LPF 100c in the third modification, the second-order LPF
It is possible to reduce the low frequency component of noise generated by the operational amplifier constituting the circuit.
Thereby, it becomes possible to contribute to higher accuracy and higher stability of the LPF.

[Fourth Modification]
In the LPF 100c according to the third modification of the present embodiment, the output switch SWz is inserted at the position shown in FIG. 15, but the present invention is not limited to the insertion position of the output switch SWz.

FIG. 16 shows a circuit diagram of a configuration example of the secondary LPF in the fourth modification example of the present embodiment.
In FIG. 16, the same parts as those in FIG. 15 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

The LPF 100d in the fifth modification differs from the LPF 100c shown in FIG. 15 in the insertion position of the output switch as the fifth switch. The LPF 100d has a first period T
1 includes an output switch SWza (fifth switch) for electrically connecting one end of the integration capacitor Cs1 constituting the first SC integration circuit 110a and the other end of the first feedback capacitor CR1. The output switch SWza electrically cuts off the other end of the first feedback capacitor CR1 and one end of the integration capacitor Cs1 in the second period T2.

FIGS. 17A and 17B show an example of a simulation result of the LPF 100d in the fourth modification. FIG. 17A shows an example of noise transfer characteristics from the operational amplifier AMP1 when the values of the respective elements are set in the same manner as the LPF 190 shown in FIG. FIG. 17 (B)
An example of the noise transfer characteristic from the operational amplifier AMP2 when the value of each element is set in the same manner as the LPF 190 of FIG. In FIGS. 17A and 17B, the horizontal axis represents frequency, and the vertical axis represents noise level.

In FIG. 17A, the noise transfer characteristic (S12) from the operational amplifier AMP1 in the LPF 190 is represented by a broken line, and the noise transfer characteristic (S11) from the operational amplifier AMP1 in the LPF 100d is represented by a solid line. Thus, the operational amplifier AMP in the LPF 190
1 and the noise transfer characteristic from the operational amplifier AMP1 in the LPF 100d coincide with each other. On the other hand, in FIG. 17B, the operational amplifier AMP in the LPF 190.
2 represents a noise transfer characteristic from the operational amplifier AMP2 in the LPF 100d by a solid line. As shown in FIG. 17B, according to the LPF 100d, the noise component is reduced particularly in the low frequency band, and the low frequency component of the noise generated in the operational amplifier constituting the secondary LPF can be reduced. Thereby, it becomes possible to contribute to higher accuracy and higher stability of the LPF.

As another modification of the present embodiment, a configuration in which the output switch SWz is omitted in FIG. 15 or a configuration in which the output switch SWza is omitted in FIG. 16 may be adopted.

[Fifth Modification]
In the LPF 100c in the third modification of the present embodiment, the SC integration circuit of FIG. 1 is applied to the second SC integration circuit 120, but the present embodiment is not limited to this.

FIG. 18 shows a circuit diagram of a configuration example of the secondary LPF in the fifth modification of the present embodiment.
18, parts that are the same as those in FIG. 5 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

The LPF 100e in the fifth modification is different from the LPF 100 of the present embodiment in that the second
This is the configuration of the SC integration circuit. Specifically, the LPF 100e includes the second SC integration circuit 12
Instead of 0, the second SC integration circuit 120 having the same configuration as the SC integration circuit 10a of FIG.
e. That is, the LPF 100e includes the SC integration circuit 10 in FIG. 1 as the SC integration circuit on the front stage side, and the SC integration circuit 10a in FIG. 3 as the rear stage SC integration circuit, and performs an integration operation in mutually opposite phases. Note that the LPF 100e includes a first feedback capacitor CR1 and a second feedback capacitor CR2 in the same manner as the LPF 100.

FIGS. 19A and 19B show examples of simulation results of the LPF 100e in the fifth modification. FIG. 19A shows an example of noise transfer characteristics from the operational amplifier AMP1 when the values of the respective elements are set in the same manner as the LPF 190 shown in FIG. FIG. 19 (B)
An example of the noise transfer characteristic from the operational amplifier AMP2 when the value of each element is set in the same manner as the LPF 190 of FIG. 19A and 19B, the horizontal axis represents frequency and the vertical axis represents noise level.

In FIG. 19A, the noise transfer characteristic (S14) from the operational amplifier AMP1 in the LPF 190 is represented by a broken line, and the noise transfer characteristic (S13) from the operational amplifier AMP1 in the LPF 100e is represented by a solid line. Thus, the operational amplifier AMP in the LPF 190
In contrast to the noise transfer characteristic from 1, the noise transfer characteristic from the operational amplifier AMP1 in the LPF 100e is reduced particularly in the low frequency band. On the other hand, in FIG. 19B, the noise transfer characteristic from the operational amplifier AMP2 in the LPF 190 is represented by a broken line, and LPF1
The noise transfer characteristic from the operational amplifier AMP2 at 00e is indicated by a solid line. FIG. 19 (B
), The noise transfer characteristic from the operational amplifier AMP1 in the LPF 190 is LPF100.
This coincides with the noise transfer characteristic from the operational amplifier AMP1 at e. Therefore, LPF100e
Accordingly, the noise component is reduced particularly in the low frequency band, and the low frequency component of the noise generated in the operational amplifier constituting the secondary LPF can be reduced. Thereby, it becomes possible to contribute to higher accuracy and higher stability of the LPF.

[Sixth Modification]
In the LPF 100e in the fifth modification example of the present embodiment, the output switch is inserted, but the present embodiment is not limited to this.

FIG. 20 shows a circuit diagram of a configuration example of the secondary LPF in the sixth modification of the present embodiment.
20, parts that are the same as those in FIG. 18 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

The difference between the LPF 100f in the sixth modification and the LPF 100e in the fifth modification is that the output switch SWz is omitted. That is, in the LPF 100f, one end of the integration capacitor Cs1 and the other end of the first feedback capacitor CR1 are electrically connected, and the first feedback capacitor CR1.
1 and one end of the integration capacitor Cs1 are electrically connected.

FIGS. 21A and 21B show examples of simulation results of the LPF 100f in the sixth modification. FIG. 21A shows an example of the noise transfer characteristic from the operational amplifier AMP1 when the values of the respective elements are set in the same manner as the LPF 190 shown in FIG. FIG. 21 (B)
An example of the noise transfer characteristic from the operational amplifier AMP2 when the value of each element is set in the same manner as the LPF 190 of FIG. 21A and 21B, the horizontal axis represents frequency and the vertical axis represents noise level.

In FIG. 21A, the noise transfer characteristic (S17) from the operational amplifier AMP1 in the LPF 190 is represented by a broken line, and the noise transfer characteristic from the operational amplifier AMP1 in the LPF 100e is represented by a one-dot chain line (S16). In FIG. 21A, the noise transfer characteristic (S15) from the operational amplifier AMP1 in the LPF 100f is represented by a solid line. In this way, the LPF 100 is compared with the noise transfer characteristic from the operational amplifier AMP1 in the LPF 190.
The noise transfer characteristic from the operational amplifier AMP1 at f has a reduced noise component, particularly in the low frequency band. On the other hand, in FIG. 21B, the operational amplifier AMP2 in the LPF 190
The noise transfer characteristic from the operational amplifier AMP2 in the LPF 100e is represented by a dashed line. In FIG. 21B, the noise transfer characteristic from the operational amplifier AMP2 in the LPF 100f is indicated by a solid line. In FIG. 21B, L
The noise transfer characteristic from the operational amplifier AMP1 in the PF 190 matches the noise transfer characteristic from the operational amplifier AMP1 in the LPF 100f. Therefore, according to LPF100f,
In particular, the noise component is reduced in the low frequency band, and the low frequency component of the noise generated by the operational amplifier constituting the secondary LPF can be reduced. Thereby, it becomes possible to contribute to higher accuracy and higher stability of the LPF.

As described above, the second-order LPF as the filter circuit in the present embodiment or its modification is the first SC integration circuit and the second stage connected to the front stage side or the rear stage side of the first SC integration circuit. SC integration circuit, a first feedback capacitor, and a second feedback capacitor.
The first feedback capacitor is inserted from the switched capacitor integrating circuit on the rear stage side into the feedback path of the SC integrating circuit on the front stage side among the first SC integrating circuit and the second SC integrating circuit. The second feedback capacitor is initialized in the second period, and is provided in parallel with the first feedback capacitor in the first period. At least one of the first SC integration circuit and the second SC integration circuit is constituted by the SC integration circuit 10 of FIG. At this time, it is desirable that the output switch is inserted into the feedback path via the first feedback capacitor, is turned on in the first period, and is cut off in the second period. Note that a configuration including the above-described second-order LPF (filter circuit) may be employed as the higher-order filter circuit.

[Physical quantity measuring device]
The LPF in any modification of the present embodiment can be employed as the LPF 100 constituting the multi-output filter circuit 200 in place of the LPF 100 in FIG. By applying such a multi-output filter circuit 200 to a sensor circuit, it is possible to provide a physical quantity measuring device that performs sensing with high accuracy and outputs a plurality of detection signals having different gains and detection ranges. .

FIG. 22 shows a configuration example of a sensor circuit having a multi-output filter circuit to which the LPF according to the present embodiment or its modification is applied. Note that this circuit configuration is an example, and for example, the detailed configuration of the circuit may be modified.

The sensor circuit 400 is a physical quantity measuring device that uses an angular velocity as a physical quantity to be measured. The sensor circuit 400 includes a drive circuit (drive device) 500 and a detection circuit (detection device) 600. The sensor circuit 400 includes a vibration piece (vibrator, piezoelectric element in a broad sense) 510 that is formed of a piezoelectric material and includes a drive vibration piece and a detection vibration piece.

The drive circuit 500 provides a drive vibration piece in an oscillation loop via drive electrodes 512a and 512b provided on the drive vibration piece, and excites the drive vibration piece (vibrator in a broad sense). Drive circuit 5
00 is a current-voltage converter 520, an auto gain control (hereinafter referred to as AGC) circuit 530, and a high pass filter (hereinafter referred to as HPF) 540.
It has. Furthermore, the drive circuit 500 includes a gain control amplifier (Gain Control Amp).
lifier: GCA) 550 and a binarization circuit 560 are provided.

The drive electrode 512a of the drive vibration piece is electrically connected to the input of the current-voltage converter 520,
The output of the current / voltage converter 520 is input to the AGC circuit 530 and the HPF 540. HP
F540 functions as a phase adjustment circuit of the oscillation signal in the oscillation loop, and the output of the HPF 540 is input to the GCA 550 and the binarization circuit 560. The AGC circuit 530 controls the gain of the GCA 550 based on the output of the current / voltage converter 520. The output of the GCA 550 is electrically connected to the drive electrode 512b of the drive vibration piece. The binarization circuit 560 binarizes the oscillation signal in the oscillation loop and outputs it to the detection circuit 600 as a reference signal. In FIG. 22, the description has been given assuming that the drive vibration piece of the vibration piece 510 is provided inside the drive circuit 500.
A driving vibrating piece of the vibrating piece 510 may be provided outside the driving circuit 500.

The detection circuit 600 includes an AC amplification circuit 610, a synchronous detection circuit 620, and a DC amplifier 630.
And a multi-output filter circuit 200. The multi-output filter circuit 200 is shown in FIG.
In place of the LPF 100 in the configuration of FIG. 8 or the LPF 100 in the configuration of FIG. 8. The AC amplifier circuit 610 includes the first current-voltage converter 6
12, a second current-voltage converter 614, an AC amplifier 616, and an HPF 618.

The drive circuit 500 starts oscillating in a state where the gain in the oscillation loop configured as described above is larger than “1”. At this time, the only input to the drive vibrating piece is noise,
It includes waves with a wide frequency range including the natural resonance frequency of the target drive vibration. Due to the frequency filter action of the drive vibration piece of the vibration piece 510, a signal including a lot of waves of the target natural resonance frequency is output, and this signal is converted into a voltage value by the current-voltage converter 520. AG
The C circuit 530 controls the oscillation amplitude in the oscillation loop by controlling the gain of the GCA 550 based on this voltage value. By repeating such an operation in the oscillation loop, the ratio of the signal having the target natural resonance frequency is increased. Then, by the gain control of the GCA 550, the gain (loop gain) during which the signal gradually goes through the oscillation loop gradually becomes “1”.
In this state, the drive vibrating piece oscillates stably.

When the driving vibration piece is excited to be in a stable oscillation state and the vibration piece 510 is rotated in a given direction, Coriolis force acts on the vibration piece 510 and the detection vibration piece is flexibly vibrated. Detection electrodes 514a, 514b, 516a, and 516b are provided on the detection vibrating piece. Detection electrodes 514b and 51
The analog ground potential is supplied to 6b, and the detection electrodes 514a and 516a are connected to the AC amplifier circuit 6b.
Ten first current-voltage converters 612 and second current-voltage converters 614 are connected. The detection circuit 600 AC-amplifies detection signals having different polarities from the detection electrodes 514a and 516a, performs synchronous detection using the reference signal from the drive circuit 500, and performs the first detection with the multi-output filter circuit 200. The signal Vout1 and the second detection signal Vout2 are output. Here, the first detection signal Vout1 and the second detection signal Vout2 are detection signals having different gains and detection ranges.

As described above, the sensor circuit 400 can include the resonator element 510, the drive circuit 500, and the detection circuit 600. The drive circuit 500 forms an oscillation loop with the vibration piece 510 and excites drive vibration in the vibration piece. The detection circuit 600 includes any one of the filter circuits described above, and outputs a plurality of detection signals having different gains and detection ranges according to the drive vibration excited by the vibrating piece 510 and the physical quantity to be measured.

〔Electronics〕
The sensor circuit described above can be mounted on the following electronic equipment. According to such an electronic device, the influence of noise in the low frequency band can be further reduced, and high-precision sensing can be easily realized.

  FIG. 23 shows a block diagram of a hardware configuration example of the electronic device according to the present embodiment.

The electronic device 700 includes a sensor circuit 400, an A / D conversion circuit 710, a clock generation circuit 720, a processing unit 730 such as a central processing unit, a memory 740, an operation unit 750, and a display unit 760. ing. Each part which comprises the electronic device 700 is mutually connected by the bus | bath (BUS). Note that the A / D conversion circuit 710 may be incorporated in the processing unit 730.

For example, the processing unit 730 executes processing according to a program read from the memory 740, and uses the digital value converted by the A / D conversion circuit 710 according to the amplitude or sensitivity of the detection signal detected by the sensor circuit 400. Perform integration. By doing so, the angular velocity and the rotation angle are calculated. At this time, the processing unit 730 can calculate the angular velocity and the rotation angle corresponding to the fast motion and the slow motion with high accuracy according to the first detection signal or the second detection signal. Then, the processing unit 730 executes processing corresponding to the calculated angular velocity or rotation angle, generates display data corresponding to the processing, and causes the display unit 760 to display the display data.

The SC integration circuit, the filter circuit, the multi-output filter circuit, the physical quantity measuring device, the electronic device, and the like according to the present invention have been described based on the above embodiment or its modifications. It is not limited to the modification. The present invention can be implemented in various modes without departing from the gist thereof, and for example, the following modifications are possible.

(1) In the above embodiment, the configuration shown in FIG. 1 is described as an example of the SC integration circuit, but the present invention is not limited to this. The SC integration circuit according to the present invention may have a configuration including, for example, three or more input capacitors.

(2) In the above embodiment or its modification, the filter circuit is shown in FIGS.
3, FIG. 15, FIG. 16, FIG. 18 or FIG. 20 has been described as an example, but the present invention is not limited thereto. As a filter circuit according to the present invention, n (n is an integer of 3 or more)
The next LPF may be used.

(3) In the above embodiment, the multi-output filter circuit has been described with an example of a configuration that performs two outputs as shown in FIG. 8, but the present invention is not limited to this. The multi-output filter circuit according to the present invention may perform three or more outputs.

(4) In the above embodiment, the configuration in which the physical quantity measuring device includes the multi-output filter circuit has been described as an example, but the present invention is not limited to this. The physical quantity measuring device according to the present invention may have a configuration in which, for example, the LPF in the present embodiment or a modification thereof is provided for each output.

(5) In the above embodiment, the example in which the electronic apparatus includes the above-described multi-output filter circuit has been described. However, the present invention is not limited to this. The electronic apparatus according to the present invention is the above S
You may have the structure provided with C integration circuit or the filter circuit.

DESCRIPTION OF SYMBOLS 10, 10a ... SC integration circuit, 20 ... Voltage charge conversion circuit, 30 ... Charge integration circuit,
100, 100a to 100f ... LPF, 110, 110a ... first SC integration circuit,
120, 120e ... second SC integration circuit, 200 ... multi-output filter circuit,
300 ... Attenuation circuit, 400 ... Sensor circuit, 500 ... Drive circuit,
510 ... Vibrating piece (vibrator), 512a, 512b ... Drive electrode,
514a, 514b, 516a, 516b ... detection electrode, 520 ... current-voltage converter,
530 ... AGC circuit, 540, 618 ... HPF, 550 ... GCA,
560: binarization circuit, 600: detection circuit, 610: AC amplification circuit,
612 ... 1st current voltage converter, 614 ... 2nd current voltage converter,
616: AC amplifier, 620: Synchronous detection circuit, 630: DC amplifier,
700 ... Electronic equipment, 710 ... A / D conversion circuit, 720 ... Clock generation circuit,
730 ... Processing unit, 740 ... Memory, 750 ... Operation unit, 760 ... Display unit,
AMP, AMP1, AMP2 ... operational amplifier, C ₁ ... first input capacitance (first capacitance),
C ₂ ... second input capacitance (second capacitance), Cg 1 ... input capacitance,
CR1 ... first feedback capacity, CR2 ... second feedback capacity,
Coff ... offset canceling capacity, Cout ... output capacity,
Cg2, Cg3, Cs, Cs1, Cs2 ... integral capacity,
SW1, SW11, SW12 ... switch (first switch),
SW2, SW21, SW22 ... switch (second switch),
SW3, SW31, SW32 ... switch (third switch),
SW4, SW41, SW42 ... switch (fourth switch),
SWa-SWg, SWa1-SWg1, SWa2-SWg2, SWr1-SWr6, SW
x1 ... switch, SWz, SWza ... output switch (fifth switch),
Vin: input voltage, Vout: output voltage

Claims (15)

A voltage-to-charge converter circuit having a first capacitor and a second capacitor;
A charge integrating circuit for integrating the charge charged in the first capacitor,
The voltage to charge conversion circuit is
In the first period, the charge charged in the first capacitor is transferred, and the charge corresponding to the input signal is charged in the second capacitor.
In the second period, a part of the charge charged in the second capacitor is charged in the first capacitor, and the charge corresponding to the input signal is charged in the first capacitor.
The charge integration circuit includes:
An operational amplifier;
An offset cancellation capacitor having one end connected to the first input terminal of the operational amplifier;
A first switch that electrically connects the other end of the offset cancellation capacitor and one end of the first capacitor in the first period;
A second switch for connecting the other end of the offset cancel capacitor to a ground potential in the second period ;
An integration capacitor having one end connected to the output terminal of the operational amplifier;
A third switch that electrically connects the other end of the integration capacitor and the other end of the offset canceling capacitor in the first period;
A switched capacitor integrating circuit comprising: a fourth switch for electrically connecting the other end of the integrating capacitor and the first input terminal in the second period . In claim 1 ,
Wherein between the first period is a period defined on the basis of the first clock,
Wherein between the second period, the switched capacitor integrator circuit, characterized in that said a first time period that is defined on the basis of the second clock of the clock and reverse phase. In claim 1 or 2 ,
A switched capacitor integrating circuit comprising a fifth switch for outputting an output signal of the charge integrating circuit as an output of the switched capacitor integrating circuit in the first period. A first switched capacitor integrating circuit;
A second switched capacitor integrating circuit connected to the front side or the rear side of the first switched capacitor integrating circuit;
A first feedback capacitor inserted into a feedback path of a switched capacitor integrating circuit on the preceding stage from a switched capacitor integrating circuit on the preceding stage of the first switched capacitor integrating circuit and the second switched capacitor integrating circuit;
A second feedback capacitor that is initialized in the second period and provided in parallel with the first feedback capacitor in the first period;
Wherein at least one of the first switched capacitor integrator circuit and the second switched capacitor integrator circuit, filter circuit, which is a switched capacitor integrator circuit according to claim 2, wherein. In claim 4 ,
And a fifth switch inserted in a feedback path through the first feedback capacitor, conducting in the first period, and interrupted in the second period. A first switched capacitor integrating circuit;
A second switched capacitor integrating circuit connected to the front side or the rear side of the first switched capacitor integrating circuit;
A first feedback capacitor inserted into a feedback path of a switched capacitor integrating circuit on the preceding stage from a switched capacitor integrating circuit on the preceding stage of the first switched capacitor integrating circuit and the second switched capacitor integrating circuit;
Is initialized, the second feedback capacitor provided in parallel with the first feedback capacitor in the first period and the second period,
A fifth switch inserted in a feedback path through the first feedback capacitor, conducting in the first period, and interrupted in the second period ;
At least one of the first switched capacitor integrator circuit and the second switched capacitor integrator circuit,
A voltage-to-charge converter circuit having a first capacitor and a second capacitor;
A charge integrating circuit for integrating the charge charged in the first capacitor,
The voltage to charge conversion circuit is
Transferring the charge charged in the first capacitor in the first period, and charging the second capacitor with a charge corresponding to an input signal;
In the second period, a part of the charge charged in the second capacitor is charged in the first capacitor, and a charge corresponding to the input signal is charged in the first capacitor.
The charge integration circuit includes:
An operational amplifier;
An offset cancellation capacitor having one end connected to the first input terminal of the operational amplifier;
A first switch that electrically connects the other end of the offset cancellation capacitor and one end of the first capacitor in the first period;
A second switch for connecting the other end of the offset cancel capacitor to a ground potential in the second period;
The first period is a period defined based on a first clock;
The second period is defined based on a second clock having a phase opposite to that of the first clock.
A filter circuit characterized by a period . Filter circuit comprising a switched capacitor integrator circuit according to any one of claims 1 to 3. Order filter circuit which comprises a filter circuit according to any one of claims 4 to 7. A filter circuit according to any one of claims 4 to 8 ,
A multi-output filter circuit comprising: an attenuation circuit connected to the output of the filter circuit and attenuating the output of the filter circuit. In claim 9 ,
The attenuation circuit is
An operational amplifier;
A first input capacitor having one end electrically connected to the inverting input terminal of the operational amplifier;
A first integration capacitor having one end electrically connected to the inverting input terminal of the operational amplifier;
A second integration capacitor having one end electrically connected to the output terminal of the operational amplifier;
The other end of the first input capacitor is electrically connected to the output of the filter circuit in the first period, and the other end is electrically connected to the ground potential in the second period.
The other end of the first integration capacitor is electrically connected to a ground potential in the first period, and is electrically connected to an output terminal of the operational amplifier in the second period.
In the second integration capacitor, the other end is electrically connected to the inverting input terminal in the first period, and the other end is electrically connected to a ground potential in the second period. Multi-output filter circuit. A filter circuit including a switched capacitor integrating circuit;
An attenuation circuit connected to the output of the filter circuit and attenuating the output of the filter circuit;
The switched capacitor integrating circuit is:
A voltage-to-charge converter circuit having a first capacitor and a second capacitor;
A charge integrating circuit for integrating the charge charged in the first capacitor,
The voltage to charge conversion circuit is
In the first period, the charge charged in the first capacitor is transferred, and the charge corresponding to the input signal is charged in the second capacitor.
In the second period, a part of the charge charged in the second capacitor is charged in the first capacitor, and the charge corresponding to the input signal is charged in the first capacitor.
The charge integration circuit includes:
An operational amplifier;
An offset cancellation capacitor having one end connected to the first input terminal of the operational amplifier;
A first switch that electrically connects the other end of the offset cancellation capacitor and one end of the first capacitor in the first period;
A second switch for connecting the other end of the offset cancel capacitor to a ground potential in the second period;
The attenuation circuit is
An operational amplifier;
A first input capacitor having one end electrically connected to the inverting input terminal of the operational amplifier;
A first integration capacitor having one end electrically connected to the inverting input terminal of the operational amplifier;
A second integration capacitor having one end electrically connected to the output terminal of the operational amplifier;
The other end of the first input capacitor is electrically connected to the output of the filter circuit in the first period, and the other end is electrically connected to the ground potential in the second period.
The other end of the first integration capacitor is electrically connected to a ground potential in the first period, and is electrically connected to an output terminal of the operational amplifier in the second period.
In the second integration capacitor, the other end is electrically connected to the inverting input terminal in the first period, and the other end is electrically connected to a ground potential in the second period. Multi-output filter circuit. A vibrator,
A drive circuit that forms an oscillation loop with the vibrator and excites drive vibration in the vibrator;
12. A detection comprising the multi-output filter circuit according to claim 9 and outputting a first detection signal and a second detection signal in accordance with a drive vibration excited by the vibrator and a physical quantity to be measured. Circuit and
The detection circuit includes:
The off I output Luther circuit outputs as said first detection signal, the physical quantity measuring device and outputs a second detection signal the output of the damping circuit. A vibrator,
A drive circuit that forms an oscillation loop with the vibrator and excites drive vibration in the vibrator;
A detection circuit that has a multi- output filter circuit, and outputs a first detection signal and a second detection signal according to the driving vibration excited by the vibrator and the physical quantity to be measured;
The multi-output filter circuit is
A filter circuit including a switched capacitor integrating circuit;
An attenuation circuit connected to the output of the filter circuit and attenuating the output of the filter circuit;
The switched capacitor integrating circuit is:
A voltage-to-charge converter circuit having a first capacitor and a second capacitor;
A charge integrating circuit for integrating the charge charged in the first capacitor,
The voltage to charge conversion circuit is
In the first period, the charge charged in the first capacitor is transferred, and the charge corresponding to the input signal is charged in the second capacitor.
In the second period, a part of the charge charged in the second capacitor is charged in the first capacitor, and the charge corresponding to the input signal is charged in the first capacitor.
The charge integration circuit includes:
An operational amplifier;
An offset cancellation capacitor having one end connected to the first input terminal of the operational amplifier;
A first switch that electrically connects the other end of the offset cancellation capacitor and one end of the first capacitor in the first period;
A second switch for connecting the other end of the offset cancel capacitor to a ground potential in the second period;
The detection circuit includes:
The off I output Luther circuit outputs as said first detection signal, the physical quantity measuring device and outputs a second detection signal the output of the damping circuit. An electronic apparatus comprising a switched capacitor integrator circuit according to any one of claims 1 to 3. An electronic apparatus comprising the physical quantity measuring device according to claim 12 .

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