JP2004340673A - Signal processing circuit and dynamic amount sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing circuit and a dynamic quantity sensor capable of obtaining an output which does not contain noises caused by the offset voltage of an operational amplifier. <P>SOLUTION: Electric charges (3C, Voff) which are based on the offset voltage and generated when charges are transferred from switched capacitors SC1, SC2 to a switched capacitor SC3, are accumulated in a switched capacitor SC4 by charging. Consequently, an influence of the offset voltage Voff is removed from an output voltage Vout which is determined by charges accumulated in the switched capacitors SC3 by charging. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal processing circuit for detecting a small signal, and a dynamic quantity sensor using the signal processing circuit.
[0002]
[Prior art]
Conventionally, as one of the physical quantity sensors, a capacitive acceleration sensor generally used as a vehicle-mounted sensor has been known.
As shown in FIG. 3, the capacitive acceleration sensor 101 includes a sensor element 102, a detection circuit 103, and a control circuit 106. The sensor element 102 includes a beam structure formed on a substrate and displaced with respect to the substrate when a mechanical amount such as acceleration is applied. The movable electrode 2a formed integrally with the beam structure, and the fixed electrodes 2b and 2c fixed on the substrate on both sides of the movable electrode 2a are configured to form differential capacitors 21 and 22. ing.
[0003]
That is, when the beam structure is displaced in accordance with the magnitude of the acceleration applied to the object to which the sensor element 102 is attached, the movable electrode 2a is displaced accordingly, so that the differential capacitor is displaced in accordance with the magnitude of the displacement. The capacitances C1 and C2 of the capacitors 21 and 22 are configured to change complementarily.
[0004]
The detection circuit 103 samples and holds an output voltage (Vcout) of the CV conversion circuit 104 and a CV conversion circuit 104 that converts a change in the capacitances C1 and C2 of the differential capacitors 21 and 22 into a voltage. A sample and hold (S / H) circuit 105 for amplifying the voltage to a predetermined sensitivity.
[0005]
Among them, the CV conversion circuit 104 has an operational amplifier 41 in which the movable electrode 2a is connected to the inverting input terminal and the reference voltage Vref (here, 1/2 of the power supply voltage VDD) is applied to the non-inverting input terminal, and this operational amplifier 41 It comprises a capacitor 42 (capacitance Cf) and a switch 43 connected in parallel between the inverting input terminal and the output terminal of the amplifier 41.
[0006]
That is, the CV conversion circuit 104 holds the movable electrode 2 a at the reference voltage Vref, and charges the capacitor 42 with the charge supplied from the sensor element 102 by opening the switch 43, and closes the switch 43. Thus, both ends of the capacitor 42 are set to the same potential (Vref = VDD / 2), and the electric charge accumulated in the capacitor 42 can be discharged.
[0007]
Then, the control circuit 106 sets FE1 = VDD and FE2 = 0, as shown in FIG. 4, assuming that the voltage applied to the fixed electrode 2b and the voltage applied to the fixed electrode 2c of the sensor element 102 are FE1 and FE2, respectively. The voltages FE1 and FE2 applied to the sensor element 102 are controlled so that the section D1 and the section D2 where FE1 = 0 and FE2 = VDD are alternately repeated. At the same time, the capacitor 43 is discharged by closing the switch 43 once during the section D1 according to the control signal Xc, and then the switch 43 is opened.
[0008]
By performing such control, the offset voltage Vs1 of the CV conversion circuit 104 is output from the CV conversion circuit 104 during the section D1 (after the switch 43 is opened), and the differential capacitor 21, The voltage Vs2 corresponding to the change of the capacitance 22 is output.
[0009]
On the other hand, the S / H circuit 105 mainly includes an operational amplifier 51 whose non-inverting input terminal is connected to a reference power supply that supplies a reference voltage Vref, and the inverting input terminal of the operational amplifier 51 has a CV conversion circuit 104. Is connected, and a charge holding unit 52 composed of a pair of switched capacitors SC1 and SC2 for sampling the output of the sampling capacitor and outputting the charges held by the sampling is connected. In addition, between the inverting input terminal and the output terminal of the operational amplifier 51, an integrated charge holding unit 53 including a switched capacitor SC3 that integrates and holds the charges held in the switched capacitors SC1 and SC2, and together with the switched capacitor SC3. A capacitor 54 forming a low-pass filter is connected in parallel (for example, see Patent Document 1).
[0010]
Each of the switched capacitors SC1 to SC3 has the same configuration, and includes a capacitor C, a switch unit S1 for connecting one end of the capacitor to either a signal input terminal or a reference power supply, and a switch C1 for connecting the other end of the capacitor to a signal. And a switch section S2 connected to one of the output terminal of the reference power supply and the reference power supply. The switches S1 and S2 operate according to the control signals X1 and X2 from the control circuit 106, and the control signal X1 is turned on for a predetermined period during a period after the switch 43 is turned off in the section D1, and The control signal X2 is turned on for a predetermined period during the section D2.
[0011]
When the control signal X1 is turned on, both ends of the capacitor C are connected to a signal input terminal and an output terminal, respectively. When the control signal X2 is turned on, both ends of the capacitor C are connected to the switched capacitors SC1 and SC3. Connected to power supply. In other cases, the switch units S1 and S2 are not connected to any of them. Such an operation is hereinafter referred to as a “first operation”.
[0012]
When the control signal X2 is turned on, the switched capacitor SC2 is in a first state in which one end of the capacitor C is connected to the reference power supply and the other end is connected to the output terminal. When the control signal X1 is turned on, one end of the capacitor is turned off. The input terminal and the other end are connected to a reference power supply. In other cases, the switch units S1 and S2 are not connected to any of them. Such an operation is hereinafter referred to as a “second operation”.
[0013]
That is, when the control signal X1 is turned on, the connection state shown in FIG. 5A is obtained, and when the control signal X2 is turned on, the connection state shown in FIG. 5B is obtained.
Then, in the switched capacitor SC1 controlled to perform the first operation, in section D1, charging of the capacitor and supply of charge to the switched capacitor SC3 (charge to be charged with the same polarity as the own capacitor) are performed. Are performed at the same time, and only the electric charge accumulated in the capacitor is discharged in the section D2. In the section D1, the switched capacitor SC2 controlled to perform the second operation discharges the charge accumulated in the capacitor and charges the switched capacitor SC3 (to charge the switched capacitor SC3 with a polarity opposite to that of its own capacitor). Are supplied at the same time, and only the capacitor is charged in the section D2.
[0014]
However, the polarity of the charge is determined by the input voltage to the S / H circuit 105, that is, the magnitude relation between the offset voltage Vs1 and the detection voltage Vs2 of the CV conversion circuit 104 and the reference voltage Vref.
Therefore, the switched capacitor SC3 integrates the charges charged in the switched capacitors SC1 and SC2 during the section D1 (when the control signal X1 is on) (that is, the input voltages Vs1 and Vs2 of the S / H circuit 5). As a result, the output voltage Vout of the S / H circuit 105 has a magnitude corresponding to the charge of the switched capacitor SC3, that is, the output voltage Vs1, Vs2 of the CV conversion circuit 104. The size according to the difference is obtained.
[0015]
[Patent Document 1]
JP-A-6-224696 (FIG. 1)
[0016]
[Problems to be solved by the invention]
However, the output voltage Vout of the S / H circuit 105 configured as described above has a problem that an error based on the offset voltage Voff generated between the inverting input terminal and the non-inverting input terminal of the operational amplifier 51 is superimposed. was there.
[0017]
That is, in the switched capacitor SCi (i = 1 to 3), the charge Qi1 stored in the capacitor C during the section D1 and the charge Qi2 stored in the capacitor C during the section D2 are expressed by the following equations (1) to (6). Indicated by
Q11 = C {Vs1- (Vref + Voff)} (1)
Q12 = C (Vref-Vref) = 0 (2)
Q21 = C {Vref- (Vref + Voff)} (3)
Q22 = C (Vs2-Vref) (4)
Q31 = C ｛(Vref + Voff) -Vout] (5)
Q32 = C (Vref-Vref) = 0 (6)
Then, in the section D1, the charges Q1, Q2 supplied to the switched capacitor SC3 from the switched capacitors SC1, SC2 and the charge Q3 charged to the switched capacitor SC3 are represented by the equations (7) to (9). .
[0018]
Q1 = Q11-Q12 = C (Vs1-Vref-Voff) (7)
Q2 = Q21−Q22 = C (−Vs2 + Vref−Voff) (8)
Q3 = Q31-Q32 = C (Vref + Voff-Vout) (9)
Note that the output voltage Vout is expressed by equation (10) from the relationship of Q1 + Q2 = Q3.
[0019]
Vout = Vref + (Vs2−Vs1) + 3 · Voff (10)
That is, an error of 3 · Voff is superimposed on the output voltage Vout of the S / H circuit 105.
Therefore, an object of the present invention is to provide a signal processing circuit and a dynamic quantity sensor capable of obtaining an output from which noise due to an offset voltage of an operational amplifier has been removed, in order to solve the above problems.
[0020]
[Means for Solving the Problems]
In the signal processing circuit of the present invention made to achieve the above object, the first switching capacitor samples the first input signal, and supplies the charge held by the sampling to the inverting input terminal of the operational amplifier. The second switching capacitor samples the second input signal and supplies the charge held by the sampling to the inverting input terminal of the operational amplifier.
[0021]
Then, the third switching capacitor connected between the inverting input terminal and the output terminal of the operational amplifier integrally holds the charges supplied from the first and second charge holding units, and An output voltage is generated according to a difference between the first input signal and the second input signal.
[0022]
At this time, the first and second switched capacitors have a capacity equal to the total capacity of the first to third switched capacitors, and when the first and second switched capacitors supply charges to the third switched capacitor, one end is inverted by the operational amplifier. A fourth switched capacitor connected to the input terminal is charged with an offset voltage generated between the inverting input terminal and the non-inverting input terminal of the operational amplifier.
[0023]
That is, before the charge is supplied from the first and second switched capacitors to the third switched capacitor, the charges charged in the first to third switched capacitors each include a charge component based on the offset voltage. It has become something. When supplying charges from the first and second switched capacitors to the third switched capacitor, the charge component based on the offset voltage among the charges held in the first to third switched capacitors becomes the fourth component. Since it is used for charging the switched capacitor, the charge charged to the third switched capacitor does not include the charge based on the offset voltage.
[0024]
Therefore, according to the signal processing circuit of the present invention, it is possible to obtain an output from which noise due to the offset voltage of the operational amplifier has been removed.
Incidentally, the first and second input signals may be configured to be supplied via separate signal lines, but may be configured to be supplied alternately in a time-division manner via a single signal line. You may.
[0025]
The above-described signal processing circuit can be suitably used, for example, when configuring a physical quantity sensor. In this case, the CV conversion circuit converts a change in the capacitance of the variable capacitor whose capacitance value changes according to the applied mechanical quantity into a voltage signal. The signal processing circuit may be configured so that a signal indicating the offset level of the CV conversion circuit is used as the first input signal, and a signal indicating the voltage level converted by the CV conversion circuit is used as the second input signal.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating the configuration of the capacitive acceleration sensor according to the embodiment.
As shown in FIG. 1, the acceleration sensor 1 according to the present embodiment includes a sensor element 2, a detection circuit 3, and a control circuit 6, and the detection circuit 3 includes a CV conversion circuit 4, a sample hold (S / H) circuit. Consists of five.
[0027]
Among them, the sensor element 2 and the CV conversion circuit 4 are configured in exactly the same manner as the sensor element 102 and the CV conversion circuit 104 of the conventional device, and therefore, the description is omitted here.
The S / H circuit 5 is also configured in exactly the same way as the S / H circuit 105 of the conventional device, except that the offset correction unit 55 composed of the switched capacitor SC4 is connected to the inverting input terminal of the operational amplifier 51. I have.
[0028]
Each of the switched capacitors SC1 to SC3 has the same configuration, and includes a capacitor (capacitance C), a switch unit S1 for connecting one end of the capacitor to either a signal input terminal or a reference power supply, and a second end of the capacitor. And a switch section S2 connected to either a signal output terminal or a reference power supply.
[0029]
One end of the switched capacitor SC4 is connected to the reference power supply, and a capacitor (capacitance 3C) having a capacitance equal to the total capacitance of the capacitors constituting the switched capacitors SC1 to SC3, and a signal output terminal ( And a switch unit S2 connected to either the inverting input terminal of the operational amplifier 51) or the reference power supply.
[0030]
Each of the switch units S1 and S2 is configured to operate according to control signals X1 and X2 from the control circuit 6.
Specifically, when the control signal X1 is turned on, both ends of the capacitor C are connected to the signal input terminal and the output terminal, respectively. When the control signal X2 is turned on, the switched capacitors SC1 and SC3 are connected to both ends of the capacitor C. Both are connected to the reference power source, and are not connected otherwise.
[0031]
When the control signal X1 is turned on, one end of the capacitor C is connected to the reference power supply, and the other end is connected to the output terminal. When the control signal X2 is turned on, the switched capacitor SC2 has one end connected to the input terminal and the other end connected to the reference terminal. Connected to power supply, otherwise unconnected.
[0032]
When the control signal X1 is turned on, one end of the capacitor C is connected to the reference power supply and the other end is connected to the output terminal. When the control signal X2 is turned on, both ends of the capacitor are connected to the reference power supply. Is not connected.
That is, the switched capacitors SC1 to SC4 that operate according to the control signals X1 and X2 have the connection state shown in FIG. 2A when the control signal X1 is turned on, and the connection state shown in FIG. 2B when the control signal X2 is turned on. It becomes.
[0033]
Since the control circuit 6 operates in exactly the same manner as the control circuit 106 of the conventional device, the description is omitted here.
In the acceleration sensor 1 of the present embodiment configured as described above, the offset voltage Vs1 of the CV conversion circuit 4 is output from the CV conversion circuit 4 during the section D1 (after the switch 43 is opened), and during the section D2. A voltage Vs2 corresponding to the change in the capacitance of the differential capacitors 21 and 22 is output to the output terminal.
[0034]
In the S / H circuit 5, the capacitor (capacitance C) of the switched capacitor SC1 is charged by the input voltage Vs1 during the section D1, and the capacitor (capacitance C) of the switched capacitor SC2 is charged by the input voltage Vs2 during the section D2. Charged.
[0035]
In the section D1, the charges charged in the capacitors of the switched capacitors SC1 and SC2 are supplied to the switched capacitors SC3 and SC4. With this charge, the capacitor (capacitance C3) of the switched capacitor SC4 is charged by the offset voltage.
[0036]
For this reason, the electric charge charged to the capacitor (capacitance C) of the switched capacitor SC3 does not include the electric charge based on the offset voltage, but becomes only the electric charge according to the difference between the input voltages Vs1 and Vs2 to the S / H circuit 5.
That is, in the switched capacitor SCi (i = 1 to 3), the charge Qi1 stored in the capacitor (capacitance C) in the section D1 and the charge Qi2 stored in the capacitor in the section D2 are (1) to (1) described above. It is shown by equation (6).
[0037]
In the switched capacitor SC4, the electric charge Q41 stored in the capacitor (capacitance 3C) in the section D1 and the electric charge Q42 stored in the capacitor in the section D2 are expressed by the equations (11) to (12).
Q41 = 3C (Vref- (Vref + Voff)) (11)
Q42 = 3C (Vref-Vref) = 0 (12)
In the section D1, the charges Q1 and Q2 supplied to the switched capacitors SC3 and SC4 and the charge Q3 charged to the switched capacitor SC3 from each of the switched capacitors SC1 and SC2 are as described in (7) to (9) above. The charge Q4 charged in the switched capacitor SC4 as shown in the equation is shown in the equation (13).
[0038]
Q4 = Q41−Q42 = −3C × Voff (13)
Note that the output voltage Vout is expressed by equation (14) from the relationship of Q1 + Q2 = Q3 + Q4.
Vout = Vref + (Vs2-Vs1) (10)
As described above, according to the acceleration sensor 1 of the present embodiment, the charge (3C · Voff) based on the offset voltage generated when the charge is transferred from the switched capacitors SC1 and SC2 to the switched capacitor SC3 is converted to the switched capacitor SC4. , The influence of the offset voltage Voff is removed from the output voltage Vout determined by the charge of the switched capacitor SC3. Therefore, it is possible to obtain the output voltage Vout from which the noise caused by the offset voltage Voff has been removed, and it is possible to obtain a highly accurate acceleration measurement result.
[0039]
In this embodiment, the sensor element 2 corresponds to a variable capacitor, the S / H circuit 5 corresponds to a signal processing circuit, the control circuit 6 corresponds to a control unit, and the output Vs1 of the CV conversion circuit 4 during a period D1 is a first input signal. The output Vs2 in the period D2 corresponds to the second input signal.
[0040]
In the above embodiment, the switched capacitors SC1 to SC3 all have the same capacitance, but the switched capacitors SC3 and the switched capacitors SC1 and SC2 may have different capacitances. . In this case, the amplification ratio can be adjusted by appropriately adjusting the capacitance ratio between the two.
[0041]
Further, in the above embodiment, the example in which the present invention is applied to the acceleration sensor has been described. However, the detection target of the sensor element 2 is not limited to the acceleration, and may be any mechanical quantity that can change the capacitance of the variable capacitor. Good.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a configuration of an acceleration sensor according to an embodiment.
FIG. 2 is an explanatory diagram illustrating an operation of a sample and hold circuit.
FIG. 3 is a circuit diagram showing a configuration of a conventional acceleration sensor.
FIG. 4 is a timing chart for explaining an operation of the conventional acceleration sensor and a problem.
FIG. 5 is an explanatory diagram showing an operation of a sample and hold circuit in a conventional acceleration sensor.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Acceleration sensor, 2 ... Sensor element, 2a ... Movable electrode, 2b, 2c ... Fixed electrode, 3 ... Detection circuit, 4 ... CV conversion circuit, 5 ... Sample hold (S / H) circuit, 6 ... Control circuit, 21 .., Differential capacitors, 41, 51, operational amplifiers, 42, 54, capacitors, 43, switches, 52, charge holding units, 53, integrated charge holding units, 55, offset correction units, SC1 to SC4, switched capacitors.

Claims (3)

A signal processing circuit that generates an output voltage according to a difference between a first input signal and a second input signal,
An operational amplifier to which a reference voltage is applied to a non-inverting input terminal and outputs the output voltage from an output terminal;
A first switched capacitor that samples the first input signal and supplies the charge held by the sampling to the inverting input terminal of the operational amplifier while maintaining the same polarity as the polarity of the first input signal with respect to the reference voltage;
A second switched capacitor that samples the second input signal and supplies the charge held by the sampling to the inverting input terminal of the operational amplifier by inverting the polarity of the second input signal with respect to the reference voltage; When,
A third switched capacitor that is connected between the inverting input terminal and the output terminal of the operational amplifier and that integrally holds the charges supplied from the first and second charge holding units;
The first and second switched capacitors have a capacitance equal to the total capacitance of the first to third switched capacitors, and have one end connected to the operational amplifier when the first and second switched capacitors supply charges to the third switched capacitor. A fourth switched capacitor connected to an input terminal and charged with an offset voltage generated between an inverting input terminal and a non-inverting input terminal of the operational amplifier;
A signal processing circuit comprising: The signal processing circuit according to claim 1, wherein the first and second input signals are alternately supplied in a time-division manner via a single signal line. A variable capacitance whose capacitance value changes according to the applied mechanical quantity;
A CV conversion circuit for converting a change in the capacitance of the variable capacitor into a voltage signal;
A signal processing circuit according to claim 1 or 2,
Wherein the signal processing circuit uses a signal indicating an offset level of the CV conversion circuit as the first input signal, and a signal indicating a voltage level converted by the CV conversion circuit as the second input signal. The physical quantity sensor characterized by the above.

Images