WO2010131640A1 - Circuit de détection d'une capacité électrostatique - Google Patents

Circuit de détection d'une capacité électrostatique Download PDF

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Publication number
WO2010131640A1
WO2010131640A1 PCT/JP2010/057937 JP2010057937W WO2010131640A1 WO 2010131640 A1 WO2010131640 A1 WO 2010131640A1 JP 2010057937 W JP2010057937 W JP 2010057937W WO 2010131640 A1 WO2010131640 A1 WO 2010131640A1
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capacitor
terminal
detected
capacitors
wiring
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PCT/JP2010/057937
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English (en)
Japanese (ja)
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達巳 藤由
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アルプス電気株式会社
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance

Definitions

  • the present invention relates to a capacitance detection circuit that detects a differential capacitance value in a capacitance sensor including a pair of capacitance elements.
  • FIG. 9 is a configuration diagram of a capacitance detection circuit described in Patent Document 1.
  • One ends of the detected capacitor 11 and the reference capacitor 12 are connected in common, and the common connection terminal is connected to the inverting input terminal ( ⁇ ) of the operational amplifier 15.
  • the constant voltage source 16 is connected to the non-inverting input terminal (+) of the operational amplifier 15, the output terminal of the operational amplifier 15 is connected to the inverting input terminal via the integration capacitor 13, and the switch is connected in parallel to the integration capacitor 13. 14 is connected.
  • the capacitance detection circuit by driving the detected capacitor 11 and the reference capacitor 12 with pulses of opposite phases, charges corresponding to these capacitance differences are taken out from the common connection terminal. At that time, since the reference voltage (fixed potential) is input to the Vin + from the constant voltage source 16, the output of the operational amplifier 15 is integrated with the integrating capacitor 13 so that the inverting input terminal of Vin ⁇ and the non-inverting input terminal of Vin + have the same voltage. Is fed back through.
  • the detected capacitor 11 and the reference capacitor 12 connected to the inverting input terminal of the operational amplifier depend on the type of sensor, a capacitance of the order of pF or less is detected in a MEMS sensor or an electrostatic touch panel, and the resolution is as follows. The fF order or less is required.
  • the electrostatic coupling of the operational amplifier inverting input terminal with the noise source may be in the order of pF in terms of level, and degradation of the S / N ratio due to noise mixing becomes a serious problem.
  • a shield with a conductor can be considered as a countermeasure against noise mixing into the inverting input terminal of the operational amplifier.
  • a shield with a conductor can be considered as a countermeasure against noise mixing into the inverting input terminal of the operational amplifier.
  • the present invention has been made in view of such a point, and an object thereof is to provide a capacitance detection circuit that is excellent in noise resistance, can suppress current consumption, and can efficiently secure a dynamic range of a signal.
  • one end is connected to the first and second detected capacitors to which one terminal to which a driving pulse is applied is commonly connected, and the other terminal of the first detected capacitor.
  • a fully differential amplifier that detects charges moving on the first and second wirings in response to a capacitance difference generated between two detected capacitors and outputs the detected charge amount in the form of a differential voltage from an output terminal.
  • a common mode feedback circuit that detects the common-mode voltage of the first and second wirings and feeds back the output voltage that makes the detected common-mode voltage equal to the reference potential to the first and second wirings. It is characterized by that.
  • the common mode feedback circuit detects the common-mode voltage of the first and second wirings, and feeds back the output voltage that makes the detected common-mode voltage equal to the reference potential to the first and second wirings. Therefore, even if the first and second detected capacitors are driven by the drive pulse, the common-mode voltage of the first and second wirings is fixed to the reference potential, so that the parasitic capacitances of the first and second wirings Can be prevented from charging. As a result, only the electric charge corresponding to the capacitance difference between the first and second detected capacitors is transferred to the fully differential amplifier and differentially amplified. Improvement and low power consumption can be achieved.
  • the fully differential amplifier since the fully differential amplifier is used to detect the capacitance difference between the first and second detected capacitors, the common mode noise in the input stage of the fully differential amplifier can be canceled and removed. Common mode noise superimposed on the output stage side of the amplifier can be easily canceled.
  • the common mode feedback circuit includes a first input capacitor having one terminal connected to the first wiring, and a first input capacitor having one terminal connected to the second wiring.
  • a common connection point between the second input capacitor having the same capacity and the other terminals of the first and second input capacitors is connected to the inverting input terminal, and a reference voltage is applied to the non-inverting input terminal, whereby the first and second input capacitors are connected.
  • a single output differential amplifier that outputs an output voltage fed back to the wiring.
  • the intermediate potential of the first and second wirings appears at the common connection point on the differential amplifier side of the first and second input capacitors so that the intermediate amplifier and the reference voltage are equal to each other.
  • the first and second wirings are not affected by the parasitic capacitance formed in the first and second wirings. Only the electric charge corresponding to the capacitance difference between the first and second detected capacitors can be transferred to the fully differential amplifier. Further, by using a single output differential amplifier, the circuit can be reduced in size as compared with a differential amplifier having a plurality of outputs.
  • the common mode feedback circuit includes a first output capacitor having one terminal connected to the output terminal of the differential amplifier and the other terminal connected to the first wiring, and one terminal connected to the difference.
  • a second output capacitor connected to the output terminal of the dynamic amplifier and having the other terminal connected to the second wiring and having a capacity equal to that of the first output capacitor; the first and second input capacitors; and the first And a plurality of switches that are provided in parallel with the second output capacitor and close one end immediately before applying a drive pulse to the first and second detected capacitors to reset the corresponding capacitors, respectively. It is also good.
  • the switch provided in parallel with the first and second input capacitors and the first and second output capacitors is connected to the first and second detected capacitors immediately before applying a drive pulse. Closed and each corresponding capacitor can be reset, allowing high-precision common mode feedback.
  • the first wiring is connected to one differential input terminal of the fully differential amplifier
  • the second wiring is connected to the other differential input terminal of the fully differential amplifier.
  • One path and a second path connecting the first wiring to the other differential input terminal of the fully-differential amplifier and connecting the second wiring to one differential input terminal of the fully-differential amplifier
  • the fully-differential amplifier is provided in each feedback path that feeds back a differential voltage from the output terminal to a differential input terminal having a different polarity.
  • An integration capacitor for accumulating a corresponding amount of charge, and a reset switch provided in parallel with each of the integration capacitors. The path switch selects the first path at the rising edge of the drive pulse.
  • the path is switched so that the second path is selected at the fall of the drive pulse, and the fully differential amplifier accumulates electric charge in the integration capacitor at both the rise and fall of the drive pulse, and the number of integrations
  • the reset switch is closed to reset the integrating capacitor.
  • the path changeover switch selects the first path at the rising edge of the driving pulse, selects the second path at the falling edge of the driving pulse, and charges the integration capacitor at both the rising and falling edges of the driving pulse. Therefore, the integration operation can be repeated continuously until a necessary signal level is obtained.
  • the present invention may also include a common mode capacitor array connected to the first and second wirings and canceling the common mode component of the first and second detected capacitors.
  • the common mode capacitor array since the common mode capacitor array is provided, the common mode components of the first and second detected capacitors can be canceled out, and the first and second power supply voltages of the differential amplifier of the common mode feedback circuit are not increased.
  • the capacity of the input capacitor 2 can be reduced, and the circuit scale and power consumption can be reduced.
  • the common mode capacitor array may include a capacitor group including a plurality of capacitors each having one terminal connected to the first or second wiring, and the other terminal of each capacitor constituting the capacitor group.
  • a switch group including a plurality of switches connected to each other, and using the switch group, a plurality of capacitors having a canceling capacity corresponding to a common mode component of the first and second detected capacitors are selected, and the driving An inversion pulse obtained by inverting the pulse can be applied to the other terminal of the capacitor group via the switch group.
  • the present invention it is possible to realize a capacitance detection circuit that is excellent in noise resistance, can suppress current consumption, and can efficiently secure a dynamic range of signals.
  • FIG. 4A is a waveform diagram of a drive pulse applied to the detected capacitance of FIG. 4
  • FIG. 4B is a voltage waveform diagram when there is no input common mode feedback circuit
  • FIG. 4C is a voltage waveform diagram when there is an input common mode feedback circuit. It is. It is a timing chart for demonstrating the flow of operation
  • FIG. 1 is a configuration diagram of a capacitance detection circuit according to an embodiment of the present invention.
  • the drive pulse DRV supplied from the drive signal source 41 serves as one terminal of the detected capacitor 42 and the detected capacitor (or reference capacitor) 43 constituting the capacitance sensor. Applied to the electrodes.
  • One detected capacitor 42 has the other electrode connected to a differential input terminal (a positive terminal in the case of a straight path to be described later) of the fully differential amplifier 49 via the wiring 60-1, and the other detected capacitor 43 Similarly, the other electrode is connected to the other differential input terminal (negative terminal in the case of a straight path) of the fully differential amplifier 49 via the wiring 60-2.
  • An input common mode cancellation capacitor array 44 and an input common mode feedback circuit 45 are connected to the wirings 60-1 and 60-2.
  • a path changeover switch 46 is provided in the wirings 60-1 and 60-2. The path changeover switch 46 connects the electrode of the detected capacitor 42 to the differential input terminal (positive side) of the fully-differential amplifier 49 via the wiring 60-1, and connects the electrode of the detected capacitor 43 to the wiring 60-2.
  • the straight path connected to the differential input terminal (negative side) of the fully-differential amplifier 49 via the wire and the electrode of the capacitor 42 to be detected are connected to the differential input terminal (negative-side) of the fully-differential amplifier 49 via the wiring 60-1.
  • the switch ⁇ 1 is closed and the switch ⁇ 2 is opened, and in the cross path, the switch ⁇ 1 is opened and the switch ⁇ 2 is closed.
  • the fully differential amplifier 49 has a negative output terminal and a positive output terminal so that the difference between the input Vin + and Vin ⁇ input to the positive differential input terminal and the negative differential input terminal is zero.
  • the differential output (Vout ⁇ , Vout +) is controlled.
  • a reset switch 47a and an integrating capacitor 48a are connected in parallel between the negative output terminal and the positive differential input terminal of the fully differential amplifier 49, and between the positive output terminal and the negative differential input terminal.
  • the reset switch 47b and the integrating capacitor 48b are connected in parallel.
  • FIG. 2 is a configuration diagram of the input common mode canceling capacitor array 44.
  • the input common mode cancellation capacitor array 44 includes a capacitor group 51 composed of a plurality of capacitors arranged in parallel and a switch group composed of a plurality of switches provided for the individual capacitors constituting the capacitor group 51. 52.
  • the capacitor group 51 includes a first capacitor group 51a in which each capacitor is connected to one wiring 60-1, and a second capacitor group 51b in which each capacitor is connected to the other wiring 60-2. It consists of
  • the switch group 52 is configured to be on / off controlled by selector signals SEL-C0... Individually applied to individual switches.
  • the capacitors 51a and 51b are set to have the same capacitance.
  • a reverse-phase pulse obtained by inverting the drive pulse is applied to the capacitor via a switch selected (on-controlled) by the selector signal SEL-C0.
  • the same charge amount corresponding to the number of selection switches (capacitors) can be canceled.
  • FIG. 3 is a block diagram of the input common mode feedback circuit 45.
  • the input common mode feedback circuit 45 is connected to the wirings 60-1 and 60-2 and connected to the wirings 60-1 and 60-2.
  • Common mode input capacitors 67 and 68 set to values and a single output differential amplifier 69 are provided.
  • the common mode input capacitors 67 and 68 have one electrode connected to the corresponding wiring 60-1 and 60-2, respectively, and the other electrode connected in common is connected to the inverting input terminal of the differential amplifier 69. Further, switches 63 and 64 are connected in parallel to the two common mode input capacitors 67 and 68.
  • the reference voltage Vref is applied to the non-inverting input terminal of the differential amplifier 69.
  • An intermediate potential between the wiring 60-1 and the wiring 60-2 appears at the common connection point on the other electrode side of the common mode input capacitors 67 and 68. Therefore, the differential amplifier 69 outputs a differential amplification signal that fixes the intermediate potential between the wiring 60-1 and the wiring 60-2 to the reference voltage Vref.
  • the common mode output capacitors 65 and 66 have one electrode connected in common, and the output terminal of the differential amplifier 69 is connected to the common connection point.
  • the other electrodes of the common mode output capacitors 65 and 66 are connected to corresponding wirings 60-1 and 60-2, respectively.
  • Switches 61 and 62 are connected in parallel to the common mode output capacitors 65 and 66, respectively.
  • a drive pulse is applied from the drive signal source 41 to one electrode of the commonly connected detected capacitors 42 and 43, and the detected signal is detected between the wirings 60-1 and 60-2 at the change point (rising / falling) of the driving pulse.
  • a potential difference corresponding to the capacitance difference between the capacitors 42 and 43 is generated.
  • the electric charge corresponding to the capacitance difference between the detected capacitors 42 and 43 generated between the wirings 60-1 and 60-2 moves to the fully-differential amplifier 49 via the path switching switch 46 through a straight path or a cross path. Are accumulated in the integrating capacitors 48a and 48b.
  • the fully differential amplifier 49 repeats the reset operation and the integration operation by the integrating capacitors 48a and 48b and the reset switches 47a and 47b, and outputs a differential voltage (Vout ⁇ , Vout +) corresponding to the capacitance difference of the detected capacitance.
  • the common mode component canceling operation is performed by the input common mode feedback circuit 45 in the process in which the electric charge according to the capacitance difference between the detected capacitors 42 and 43 is transferred to the integrating capacitors 48a and 48b.
  • the operation principle of the input common mode feedback circuit 45 will be described. First, in order to explain the relationship between the charging voltage of the capacitors 42 and 43 to be detected and the voltage waveform of the wirings 60-1 and 60-2, a circuit model without the fully differential amplifier 49 as shown in FIG. 4 (no feedback) Is assumed.
  • the detected capacitors 105 and 106 shown in FIG. 4 correspond to the detected capacitors 42 and 43 shown in FIG. 1, and the wirings 102 and 103 correspond to the wirings 60-1 and 60-2, respectively.
  • the detected capacitors 105 and 106 are detected at the rising edge of the drive pulse 104. Is charged, and voltage waveforms corresponding to the charged potentials of the detected capacitors 105 and 106 appear on the wirings 102 and 103.
  • the potential difference Va between the detected capacitor 105 and the detected capacitor 106 is detected by the fully differential amplifier 49.
  • the parasitic capacitance 101 always exists in the wirings 102 and 103.
  • the parasitic capacitance 101 of the wirings 102 and 103 is charged according to the potential change Vb generated in each of the wirings 102 and 103.
  • the phenomenon that the parasitic capacitance 101 of the wirings 102 and 103 is charged by the potential change Vb acts in the direction of decreasing the potential difference Va that is a sensing target, and means that the sensitivity as a sensor is lowered. Since the phenomenon in which the parasitic capacitance 101 is charged results in a potential change Vb in the wirings 102 and 103, the present embodiment changes the intermediate potential between the wiring 102 and the wiring 103 to the reference voltage Vref by the input common mode feedback circuit 45. By fixing, charging of the parasitic capacitance 101 at the rising edge (and falling edge) of the driving pulse is prevented.
  • FIG. 5 (c) shows voltage waveforms of the wirings 102 and 103 at the time of driving pulse rise when the input common mode feedback circuit 45 is operated in the circuit model shown in FIG. Since the input common mode feedback circuit 45 performs feedback control so that the intermediate potential between the wiring 102 and the wiring 103 is fixed to the reference voltage Vref, the potential difference Va ′ between the detected capacitor 105 and the detected capacitor 106 is applied to the wirings 102 and 103. However, a potential change (Vb) that charges the parasitic capacitance 101 does not occur in the wirings 102 and 103. Therefore, it is possible to cancel only the input common mode component from the wirings 102 and 103 and transfer only the charge corresponding to the potential difference Va ′ between the detected capacitor 105 and the detected capacitor 106 to the fully differential amplifier 49.
  • Vb potential change
  • the switches ⁇ 1 and ⁇ 2 are complementarily turned on / off at the rise and fall of the drive pulse output from the drive signal source 41.
  • the path switch 46 is a straight path ( ⁇ 1 on), and when ⁇ 2 is High (closed), it is a cross path ( ⁇ 2 on).
  • the RST-C signal rises at the timing T1 in FIG. 6, the switches 47a and 47b provided in the integration capacitors 48a and 48b are closed, and the charges of the integration capacitors 48a and 48b are closed.
  • RST-I rises, whereby all the switches 61 to 64 of the input common mode feedback circuit 45 are closed, and the differential amplifier 69 has a voltage follower configuration. Accordingly, the wirings 60-1 and 60-2 connecting the detected capacitors 42 and 43 and the fully differential amplifier 49 are set to the reference voltage Vref, and the common mode output capacitors 65 and 66 and the common mode input capacitors 67 and 68 are connected to each other. The charge is reset.
  • the detected capacitors 42 and 43 are driven with the rising waveform of the drive pulse.
  • the input common mode feedback circuit 45 detects the common-mode voltage of the wirings 60-1 and 60-2. Specifically, an intermediate potential of the wirings 60-1 and 60-2 detected by the common mode input capacitors 67 and 68 configured with equal capacity is applied to the inverting input terminal of the differential amplifier 69.
  • the differential amplifier 69 amplifies and outputs the difference between the reference voltage Vref and the inverting input terminal input (intermediate potential). The output voltage at this time is fed back to the wirings 60-1 and 60-2 via the common mode output capacitors 65 and 66, but the common mode output capacitors 65 and 66 are configured with equal capacity.
  • a common-mode voltage of the voltages of the wirings 60-1 and 60-2 is given.
  • the common-mode voltage of the wirings 60-1 and 60-2 for transmitting signals output from the detected capacitors 42 and 43 (sensor capacitors) is operated to keep the reference voltage Vref.
  • the fully differential amplifier 49 includes integrating capacitors 48a and 48b from the outputs of the negative output terminal and the positive output terminal so that the voltage difference between the positive differential input terminal and the negative differential input terminal is zero. To perform feedback operation. As a result, the fully differential amplifier 49 outputs a voltage corresponding to the capacitance difference between the detected capacitors 42 and 43.
  • the voltage output at this time is defined as: ⁇ C is the capacitance difference between the detected capacitors 42 and 43, Ci is the integration capacitance, and Vi is the peak value of the drive pulse.
  • Vout + ⁇ Vout ⁇ ⁇ C ⁇ Vi / Ci It becomes.
  • the level of the output voltage can be set by appropriately determining the size of the integration capacitor Ci.
  • FIG. 7 shows a voltage output waveform of the fully differential amplifier 49.
  • the difference between the detected capacitors 42 and 43 is added to the integration capacitor 48 of the fully differential amplifier 49 by the number of integrations, and the positive side output Vout + and the negative side output Vut ⁇ increase stepwise with the reference voltage Vref as the center. .
  • the fully differential amplifier 49 can input and amplify only the amount of charge corresponding to the difference between the detected capacitors 42 and 43, so that it is not necessary to pass a wasteful bias current, and the S / N is improved.
  • the common mode output capacitors 65 and 66 of the input common mode feedback circuit 45 are provided to output the output voltage of the differential amplifier 69 to the wirings 60-1 and 60-2.
  • the capacitance is reduced, it is necessary to increase the output amplitude by supplying a large power supply voltage to the differential amplifier 69 that operates so as to eliminate the difference between the intermediate potential between the wiring 60-1 and the wiring 60-2 and the reference voltage Vref. There is.
  • the capacitances of the common mode output capacitors 65 and 66 it is necessary to increase the capacitances of the common mode output capacitors 65 and 66. Therefore, it is necessary to increase the capacitance area. An increase in the area of the common mode output capacitors 65 and 66 is also undesirable because it reduces the mounting area.
  • the common-mode charge amount is canceled by applying an inversion pulse having a phase opposite to that of the drive pulse to the capacitors connected to the wirings 60-1 and 60-2 by the input common-mode capacitance array 44. .
  • capacitor groups 51a and 51b are configured such that the electrodes on the wiring side of the capacitors are connected to the wirings 60-1 and 60-2 corresponding to the detected capacitors 42 and 43, respectively.
  • the electrode is connected to an inversion pulse supply terminal having a phase opposite to that of the drive pulse through the switch group 52.
  • Each capacitor takes an appropriate value or a weighted size, and a switch group is set by the SEL-C signal so that it becomes an average value of the detected capacitors 42 and 43.
  • the charge amount corresponding to the common mode of the detected capacitors 42 and 43 can be offset by the charge amount of the capacitor groups 51a and 51b from the charge amount of the common mode of the detected capacitors 42 and 43.
  • the size of the common mode output capacitors 65 and 66 of the input common mode feedback circuit 45 can be reduced, and the driving capability of the differential amplifier 69 can be suppressed, so that the circuit scale and power consumption can be reduced.
  • Fig. 8 shows a modification of the input common mode feedback circuit.
  • the operation of this input common mode feedback circuit is basically the same as that of the input common mode feedback circuit 45 shown in FIG. 3 except that an operational transconductance amplifier (OTA) 70 is used instead of the differential amplifier 69. ing.
  • OTA operational transconductance amplifier
  • the common mode output capacitors 65 and 66 shown in FIG. 3 can be omitted by providing two outputs to the operational transconductance amplifier 70, each of which has the same current output.

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Abstract

La présente invention concerne un circuit de détection d'une capacité électrostatique. Ledit circuit possède d'excellentes caractéristiques de résistance au bruit, est capable de limiter la consommation de courant et de garantir efficacement des plages dynamiques pour des signaux. Ce circuit de détection de capacité électrostatique est équipé des éléments suivants : une première capacité détectée (42) et une seconde capacité détectée (43) à chacune desquelles est connectée de manière jointe une borne soumise à une impression d'impulsions de commande ; un premier câble (60-1) dont une extrémité est connectée à l'autre borne pour la première capacité détectée susmentionnée (42) ; un second câble (60-2) dont une extrémité est connectée à l'autre borne pour la seconde capacité détectée susmentionnée (43) ; un amplificateur totalement différentiel (49) dans lequel des charges électriques se déplaçant sur les premier et second câbles susmentionnés (60-1) et (60-2) correspondant à la différence de capacité générée dans les première et seconde capacités détectées susmentionnées (42) et (43) sont détectées et sont émises sous forme de tension différentielle ; et un circuit de rétroaction de mode commun (45) dans lequel des tensions de sortie, par lesquelles des tensions de mode commun des premier et second câbles susmentionnés (60-1) et (60-2) sont rendues égales à la tension de référence, sont réalimentées dans les premier et second câbles.
PCT/JP2010/057937 2009-05-12 2010-05-11 Circuit de détection d'une capacité électrostatique WO2010131640A1 (fr)

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Cited By (7)

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Publication number Priority date Publication date Assignee Title
JP2013024565A (ja) * 2011-07-14 2013-02-04 Sharp Corp イオンセンシング装置およびイオン発生器
EP2653846A1 (fr) * 2012-04-18 2013-10-23 Nxp B.V. Circuit de capteur et procédé d'étalonnage
US20140327455A1 (en) * 2013-05-03 2014-11-06 Sensirion Ag Sensor circuit arrangement
JP2015064899A (ja) * 2011-07-12 2015-04-09 シャープ株式会社 タッチパネルシステムおよび電子機器
US9307319B2 (en) 2012-04-18 2016-04-05 Nxp, B.V. Sensor circuit and calibration method
CN107167673A (zh) * 2017-05-10 2017-09-15 南京大学 一种可探测电荷变化特征的传感器
JP2018179614A (ja) * 2017-04-06 2018-11-15 日立オートモティブシステムズ株式会社 角速度検出装置

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JPH06242159A (ja) * 1993-02-19 1994-09-02 New Japan Radio Co Ltd 静電容量測定装置
JP2003004482A (ja) * 2001-06-19 2003-01-08 Yamatake Corp センサ信号処理の同期検波回路
US6970126B1 (en) * 2004-06-25 2005-11-29 Analog Devices, Inc. Variable capacitance switched capacitor input system and method
JP2007171171A (ja) * 2005-11-29 2007-07-05 St Microelectronics Srl 検出回路、インターフェース回路、電子機器、差動容量性センサー読み取り方法
JP2008102091A (ja) * 2006-10-20 2008-05-01 Toyota Motor Corp 容量型検出回路

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Publication number Priority date Publication date Assignee Title
JPH06242159A (ja) * 1993-02-19 1994-09-02 New Japan Radio Co Ltd 静電容量測定装置
JP2003004482A (ja) * 2001-06-19 2003-01-08 Yamatake Corp センサ信号処理の同期検波回路
US6970126B1 (en) * 2004-06-25 2005-11-29 Analog Devices, Inc. Variable capacitance switched capacitor input system and method
JP2007171171A (ja) * 2005-11-29 2007-07-05 St Microelectronics Srl 検出回路、インターフェース回路、電子機器、差動容量性センサー読み取り方法
JP2008102091A (ja) * 2006-10-20 2008-05-01 Toyota Motor Corp 容量型検出回路

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015064899A (ja) * 2011-07-12 2015-04-09 シャープ株式会社 タッチパネルシステムおよび電子機器
JP2013024565A (ja) * 2011-07-14 2013-02-04 Sharp Corp イオンセンシング装置およびイオン発生器
EP2653846A1 (fr) * 2012-04-18 2013-10-23 Nxp B.V. Circuit de capteur et procédé d'étalonnage
US9307319B2 (en) 2012-04-18 2016-04-05 Nxp, B.V. Sensor circuit and calibration method
US20140327455A1 (en) * 2013-05-03 2014-11-06 Sensirion Ag Sensor circuit arrangement
JP2018179614A (ja) * 2017-04-06 2018-11-15 日立オートモティブシステムズ株式会社 角速度検出装置
CN107167673A (zh) * 2017-05-10 2017-09-15 南京大学 一种可探测电荷变化特征的传感器

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