JPH0128323B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a capacitive displacement converting device that converts physical displacement based on changes in physical quantities such as pressure and tension into electrical signals.

Such displacement converters are used to detect flow rates or pressures in various processes, convert them into electrical signals, and transmit the detection results to a remote receiver, etc., and simplify the circuit configuration. In order to reduce manufacturing costs, a "displacement converting device" (Japanese Patent Application No. 1982-29246) has been proposed, which was filed separately by the present applicant.

However, in commonly used capacitive sensors, there is a distributed capacitance as an invariant component that exists between the fixed electrode and the movable electrode, and a distributed capacitance that exists between the fixed electrode, the movable electrode, and the case. , these distributed capacitances cause a problem in which the conversion characteristics become non-linear.

The present invention has the purpose of fundamentally solving such problems in the conventional art, and has a simple circuit configuration.
The present invention provides a highly effective capacitive displacement transducer that can eliminate all conceivable distributed capacitance effects.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to figures showing examples, but first, the premises of the present invention will be described.

FIG. 1 is a sectional view showing an example of a single capacitance type sensor, in which a fixed electrode SP and a movable electrode MP are housed in a case F, and a mechanical When the displacement force P is applied, the movable electrode MP moves, so both electrodes SP,
The capacitance C ₁ between MPs is changed.

Figure 2 is an equivalent circuit of Figure 1 taking into consideration the existence of distributed capacitance, and shows the distributed capacitance C S1 between the fixed electrode SP and case F, and the distributed capacitance C _{S1 between the fixed electrode SP and case F, and the distributed capacitance C S1} between the fixed electrode SP and case F.
There is a distributed capacitance C _S2 between the two, and it is shown that it is necessary to configure the conversion device by taking this existence into consideration.

FIG. 3 is a circuit diagram showing an embodiment of the first invention, which is applied to the single capacitance type sensor of the equivalent circuit shown in FIG.

In other words, FET (Field Effect Transistor)
CMOS configured by Q ₁ ~ Q ₄
(Complementary Metal Oxide
The first and second Semiconductor type inverters G ₁ and G ₂ are cascade-connected to each other, and
A single capacitance type sensor as a capacitance between the output of the second inverter G ₂ and the input of the first inverter G ₁
CS is inserted in series, and the first inverter G ₁
A constant value current limit circuit CC is connected between the input and output of.

The first and second inverters connected in cascade here
G ₁ and G ₂ form an amplification means and are connected to an inverter.
The connection from the output of G ₂ to the capacitance is connected to the inverter.
A feedback means is formed to feed back the output of the amplifying means that is in phase with the signal at the input point of _G1 .

Further, the constant value current limiting circuit is required to be connected between the input point and the output of the amplifying means having a phase opposite to that of the signal at the input point of _G1 .

Therefore, an operational amplifier or a non-inverting amplifier such as a Schmitt trigger is used as _G1 , and its output is fed back to the capacitance, and the amplifier output is received by an inverter, and the inverter output and _{G1 are}
It is also possible to provide a configuration in which a constant value current limiting circuit is provided between the input point and the input point.

Figure 4 is a circuit diagram showing an example of a constant value current limiting circuit CC, in which the drains and sources of FETs Q ₅ and Q ₆ are connected in series, and the current flowing through resistors R ₁ and R ₂ is The resulting terminal voltages of the resistors R ₁ and R ₂ are fed to the gate as negative feedback to form a bidirectional constant value current limiting circuit.

In addition to the configuration described above, the constant value current limiting circuit may also have a configuration in which a pair of unidirectional constant value current limiting circuits are connected in antiparallel, or only one direction may be configured with a constant value current limiting circuit and the other direction may be configured with a switching element such as a diode. It is also possible to configure

Furthermore, by using CMOS type inverters, each inverter G ₁ and G ₂ produces an output with a peak value that is almost equal to the power supply voltage E, and the capacitance C ₁ of the single capacitance type sensor CS The oscillation operation is performed at a corresponding period.

That is, as shown in FIG. 5, which shows the waveforms of each _part in FIG. ₁ and the distributed capacitance C _S2 is rapidly charged and the distributed capacitance
As the terminal voltage of C _S2 suddenly reaches a constant voltage, it rises almost vertically as shown in Figure 5B.

Note that in the charging operation at this time, since the output impedance of the second inverter _G2 is extremely small, the existence of the distributed capacitance C _S1 becomes irrelevant.

Also, at this time, the output C of the first inverter _G1 whose input is connected to the terminal C is "L" (low level), and the constant current limiter CC is connected between the input and output of the first inverter _G1 . is connected, so
The charge in the distributed capacitor C _S2 immediately starts discharging via the constant value current limiting circuit CC and the output impedance of the first inverter _G1 , but this discharge current is regulated to a constant current value by the constant value current limiting circuit CC. As a result, the output B decreases linearly.

When the output B decreases to the threshold level V _TH at which the output of the first inverter G ₁ is inverted, the output C of the first inverter G ₁ changes to “H”, thereby causing the output of the second inverter G ₂ to change to “H”. Since A becomes “L”, the residual charge of the distributed capacitance C _S2 becomes the capacitance C ₁
After the output B drops vertically due to rapid discharge through the
The distributed capacitance C _S2 is charged by the constant current passing through CC, and the output B increases linearly.

When the output B reaches the threshold level _VTH , the output C of the first inverter _G1 changes to "L",
As a result, the output A of the second inverter _G2 becomes "H".
Therefore, charging is performed again from the second inverter _G2 , and the above operation is repeated.

Here, the terminal voltage change e ₁ of the distributed capacitance C _S2 with reference to the threshold level V _TH is as follows:
Since the output peak value E of the second inverter G ₂ is divided by the impedance ratio between the capacitance C ₁ and the distributed capacitance C _S2 , it is expressed by the following equation.

e ₁ = C ₁ / C ₁ + C _S2・E (1) Also, the terminal voltage change e ₁ is the threshold level
The time t ₁ required for the voltage to decrease to V _TH is expressed by the following equation, where i is the constant value of the discharge current regulated by the constant value current limiting circuit CC.

i・t ₁ = e ₁ (C ₁ + C _S2 ) ………(2) Calculating t ₁ from equations (1) and (2), t ₁ = C ₁・E/i ………(3) , during repeated charging and discharging, the distributed capacitance C _S2
, a charge corresponding to the threshold level V _TH is determined as the reference potential, and charging and discharging are performed around this, so the terminal voltage change e ₁ on the charging side and the terminal voltage change e ₂ on the discharging side are By charging this terminal voltage change e _{for 2} minutes with a constant current i from the constant current limiting circuit CC,
The required charging time t ₂ is also equal to t ₁ and the following equation holds true.

t ₁ =t ₂ (4) Therefore, the oscillation frequency f is expressed by the following equation.

f = 1/t ₁ + t ₂ = i/2・C ₁・E ………(5) Also, if K is a constant determined by the current i, power supply voltage E, etc., then f=1/C ₁・K … ...(6) Since the oscillation frequency f corresponds to the capacitance C ₁ , the influence of the distributed capacitances C _S1 and C _S2 is eliminated.

Note that if there is a distributed capacitance C _S3 in parallel with the capacitance C ₁ , charging can be achieved by connecting a compensating capacitor C _cp with the same capacitance in parallel with the constant current limiter CC. Since compensatory charging for the distributed capacitance C _S3 is sometimes performed by the capacitor C _cp , the influence of the distributed capacitance C _S3 is also eliminated as described later.

FIG. 6 is a conceptual diagram of a differential capacitance type sensor that is the premise of the second and third inventions, and shows a fixed electrode
Since the movable electrode MP provided between SP ₁ and SP ₂ moves between the fixed electrodes SP ₁ and SP ₂ according to the mechanical displacement corresponding to the physical displacement to be detected, the First and second capacitance C ₁ , C ₂
is now changing differentially.

Figure 7 is an equivalent circuit of Figure 6 that takes into consideration the presence of distributed capacitance, and the distributed capacitances C _SG1 and C _SG2 between the fixed electrodes SP ₁ and SP ₂ and the case are the same as those between the terminals A and B and the ground. A distributed capacitance C _SG0 between the movable electrode MP and the case is interposed between the terminal C and the ground, while a first and second electrostatic capacitance is interposed between the terminals A-C and B-C. Distributed capacitance in parallel with capacitances C ₁ and C ₂
C _SP1 and C _SP2 exist.

FIG. 8 is a sectional view showing an example of a differential capacitance type sensor, in which fixed electrodes SP ₁ and SP ₂ supported by lead wires L are provided in a case F, and
A flexible movable electrode MP whose base is fixed by an insulating sealing material I such as glass is provided, and the movable electrode MP is deflected by a mechanical displacement force P applied to its tip. As a result, the first and second capacitances C ₁ and C ₂ configuring the differential capacitance type sensor vary differentially.

In this case, a constant capacitance is formed between the end L _t of the lead wire L and the base of the movable electrode MP, and this corresponds to the distributed capacitances C _SP1 and C _SP2 in FIG. It's summery.

Therefore, as shown in FIG. 9, if a protruding shield part S is provided between the end _Lt of the lead wire L and the base of the movable electrode MP, the formation of distributed capacitances C _SP1 and C _SP2 can be prevented. You can also ignore this.

FIG. 10 is a block diagram showing an embodiment of the second invention and the third invention, and the terminals A to C of FIGS. 7 and 9 are connected to the terminals A to C. First, the operation will be explained while ignoring the distributed capacitances C _SP1 and C _SP2 .

First, the case where the output of the n-th bit of the counter CT is at a high level "H" will be described.

In this case, the first gate _G2A operates as an inverter, and its output changes in an opposite phase to the output of the inverter _G1 . On the other hand, inverter
Since the output of _G3 is at low level "L" (zero level), the output of the second gate _G2B is at high level "H" regardless of the state of the output of inverter _G1 .
(voltage +E) is maintained.

In this state, when the output C of the inverter _G1 is reversed from high level "H" to low level "L", the output A of the first gate _G2A is rapidly reversed to high level "H" and the constant voltage +E (See Figure 5A). This +E voltage causes the second
A series circuit of the combined capacitance C _t of the capacitance C ₂ and the distributed capacitance C _SG0 and the first capacitance C ₁ is charged in series.

FIG. 11 shows an equivalent circuit for series charging performed during this level inversion.

In this case, the first gate G _2A and the second gate
Since the output impedance of G _2B is extremely small, the distributed capacitances C _SG1 and C _SG2 are ignored.

Furthermore, in Fig. 10, a constant voltage of +E is given to one end of the second capacitor _C2 as the output of the second gate _G2B , but this is ignored in the equivalent circuit shown in Fig. 11. be.

This is because the +E voltage is divided by the parallel capacitance of the first capacitance C ₁ and the distributed capacitance C _SG0 and the second capacitance C ₂ and is applied as a bias voltage to the input terminal of the inverter G ₁ . This is because, as will be described later, this bias voltage is constant and does not affect the oscillation operation. Note that the values of the first capacitance C ₁ and the second capacitance C ₂ are almost equal and the distributed capacitance _SG0 is large compared to them, so the bias point is approximately +E/2
is set near .

With the start of series charging, the +E voltage charges the series capacitance of the composite capacitance C _t of the second capacitance C ₂ and the distributed capacitance C _SG0 and the first capacitance C ₁ , but the initial inverter of this inversion The maximum voltage at the input terminal C of G ₁ is determined by the impedance ratio of these capacitors.

After completion of this charging, discharging by the constant value current limiting circuit CC is started.

After series charging is completed, the input terminal of inverter _G1 is at high level, so its output C is at low level "L" (see period _t1 in Figure 5C),
Since the constant value current limiting circuit CC is connected between the input and output terminals of the inverter _G1 , the charge in the distributed capacitance _CSG0 and the second capacitance _C2 is transferred to the constant value current limiting circuit CC.
The discharge starts immediately through the output impedance of the inverter _G1 , but this discharge current is limited to a constant current value by the constant current limiter CC.
The potential at the input end of inverter _G1 decreases linearly as shown in FIG. 5B.

This discharge is performed in parallel to each capacity (parallel discharge), but the equivalent circuit at the time of this discharge is
Shown in Figure 2.

In this equivalent circuit, as in the equivalent circuit shown in FIG. 11, a voltage of +E is applied from the second gate G _2B to one end of the second capacitor C ₂ , but this is omitted.

Immediately after the level of the output of the first gate _G2A is inverted, the bias voltage at point C, that is, at the input terminal of the inverter _G1 , due to the +E voltage applied from the second gate _G2B is the same as in the case of Fig. 11. 1st to
The parallel capacitance of capacitance C ₁ and distributed capacitance C _SG0 and the second
It becomes a divided voltage divided by capacitance C ₂ and does not change the bias voltage. In other words, the +E voltage applied from the second gate _G2B does not pose any hindrance to the oscillation operation.

When the parallel discharge continues and the output B falls to the threshold level _VTH at which the output of the inverter _G1 is inverted, the output C of the inverter _G1 is inverted to "H", thereby causing the output of the first gate _G2A to Since A becomes “L”, the residual charges in the distributed capacitance C _SG0 and the second capacitance C ₂ are rapidly discharged, and the inverter
The potential at the input end of _G1 drops vertically.

Due to this potential drop, the output of the inverter _G1 becomes "H" (the output A of the first gate _G2A becomes "L"), so the current shown in Fig. 12 is a constant current through the constant value current limiting circuit CC. The distributed capacitance C _SGO and the second capacitance C ₂ are reversely discharged (charged) in the opposite direction.

The relationship between the bias voltage at point C due to the +E voltage applied from the second gate _G2B during this reverse discharge is also shown by the same circuit as the equivalent circuit shown in Figure 12 with the direction of current reversed. No changes occur.

Due to this reverse discharge, the input of inverter _G1 increases linearly. When the threshold level _VTH is reached, the output C of the inverter _G1 is inverted to "L",
As a result, the output A of the first gate _G2A becomes "H", so charging from the first gate is performed again, and these operations are repeated as in FIG. 3.

On the other hand, the output C of the inverter _G1 is counted by the counter CT, and when a certain number of counts is performed, the count output n changes from "H" to "L".
In order to maintain this state until a certain number of counts are performed again, this signal is applied to the second gate _G2B via the inverter _G3 , thereby turning on the second gate _G2B and turning on the first gate G2B. _2A
is turned off, and this time the same charging and discharging as described above is performed repeatedly between terminals B and C. When the count output n changes to "H" again, the first gate G2A is turned on and the second gate _G2A is turned on. G _2B is turned off and terminal A-
Charging and discharging between C is performed.

Therefore, the first and second gates G _2A and G _2B are turned on alternately, and accordingly, charging and discharging operations between terminals A and C and between terminals B and C are repeated.

In this case, the first gate and the second gate selectively feed the in-phase output of the amplifying means to the first gate, the second gate, and the like through the feedback means.
A switching means connected to one end of the second capacitor is formed. Therefore, when a non-inverting amplifier is used as _G1 , the switching means formed by the first and second gates can be realized by a simple changeover switch circuit.

Here, the terminal voltage change e ₁ of the distributed capacitance C _SG0 with respect to the threshold level V _TH as a reference is the combined capacitance of the distributed capacitance C _SG0 and the second capacitance C ₂ from the relationship shown in Figure 11. If _t , then it is expressed by the following equation.

e ₁ = C ₁ / C ₁ + C _t・E (11) Also, the terminal voltage change e ₁ is the threshold level
The time _t1 required for the voltage to decrease to V _TH is given by the following formula based on the relationship shown in Figure 12, where i is the discharge current of a constant value regulated by the constant value current limiting circuit CC. .

i・t ₁ = e ₁ (C ₁ +C _t ) ………(12) Calculating t ₁ from equations (11) and (12), t ₁ = C ₁・E/i ………(13) , during repeated charging and discharging, the distributed capacitance C _SG0
, a charge corresponding to the threshold level V _TH is determined as the reference potential, and charging and discharging are performed around this, so the terminal voltage change e ₁ on the charging side and the terminal voltage change e ₂ on the discharging side are By charging this terminal voltage change e _{for 2} minutes with a constant current i from the constant current limiting circuit CC,
The required charging time t ₂ is also equal to t ₁ and the following equation holds true.

t ₁ = t ₂ (14) These relationships are the same in charging and discharging between terminals B and C, and in this case, as shown in Fig. 11,
The first capacitance C ₁ and the second capacitance C ₂ in FIG. 2 are exchanged, and the equation (13) becomes the following equation.

t ₁ = C ₂ · E/i (15) Therefore, the "H" period of the pulse signal obtained from the count output n of the counter CT is applied to the first capacitance C 1, and the "L" period is applied to the first capacitance C _1. It corresponds to the second capacitance C ₂ , and if this is averaged by an integrating circuit of resistor R ₃ and capacitor C ₃ , the duty ratio of the pulse signal can be obtained, so C ₁ /(C ₁ +C ₂ )
This is the calculation result, which becomes the electrical signal as the conversion output Eo.

Figures 13 and 14 show distributed capacitances C _SP1 ,
Figure 11 and Figure 1 when considering the existence of C _SP2 .
This is an equivalent circuit similar to that shown in FIG. 2, and by considering FIGS. 11 and 12 in the same way as equations (11) to (13), the following equation can be obtained.

e ₁ = (C ₁ +C _SP1 )E/C ₁ +C _SP1 +C _SG0 +C ₂ +C _cp +C _cp・−E/C ₁ +C _SP1 +C _SG0 +C ₂ +C _cp ……(16) i・t ₁ = e ₁ (C _cp +C _SP1 +C ₁ +C ₂ +C _SG0 )
......(17) Therefore, C _cp is a compensation capacitor connected in parallel with the constant value current limiting circuit CC in Fig. 5,
If this is set to the same capacitance value as the distributed capacitance C _SP1 , the distributed capacitance C _SP1 given to the output C will be compensated for by the compensation capacitor C _cp in the charging state shown in _FIG . influence is eliminated.

Therefore, the following equation holds from equations (16) and (17).

t ₁ = (C ₁ + C _SP1 − C _cp ) E/i ...... (18) Here, since C _SP1 = C _cp , the equation (18) is t ₁ = C ₁・E/i ... ...(19), and the same results as equations (13) and (15) are obtained.

Note that, due to the structure of the sensor, the relationship C _SP1 ≈C _SP2 is obtained, so the purpose can be achieved using the same compensation capacitor C _cp .

In other words, the influence of distributed capacitances C _SG1 , C _SG2 , C _SG0 etc. is completely eliminated, and the compensation capacitor
By adding C _cp , the influence of distributed capacitances C _SP1 and C _SP2 can be eliminated, so a simple circuit configuration can reduce the distributed capacitance.
It is possible to obtain linear conversion characteristics without the influence of C _SG1 , C _SG2 , C _SG0 , C _SP1 , C _SP2, etc.

In addition, the single capacitance type sensor shown in Figure 1 is
The same purpose can be achieved by using one of the first and second capacitances C ₁ and C ₂ and using a fixed reference capacitance for the other.

FIG. 15 is a circuit diagram showing an embodiment of the fourth invention, in which differential capacitance type sensor DS to resistor R _3A , R _3B
The integration circuit with capacitors C _3A and C _3B is the first
It is the same as figure 0, but the constant value current limiter CC has
In contrast to FIG. 4, a device in which the drain and source connections are reversed is used.

In addition, the output of the integrating circuit is given to a two-wire output section OT mainly composed of differential amplifier A, and in differential amplifier A, the output voltage of the integrating circuit given to the inverting input and the resistor R ₄ , R ₅ and resistor
The difference with the reference voltage of the non-inverting input set by the potentiometer RV ₁ via R ₆ is amplified, and this output controls the FET Q ₇ to the line terminal to which the two-wire line is connected. The current value between LT ₁ and LT ₂ is determined.

However, FET Q ₇ and constant voltage diode ZD
The current through the feedback potentiometer RV ₂
The resulting voltage is passed through resistor _R5 as negative feedback and is applied to the non-inverting input of differential amplifier A, so the voltage between both inputs of differential amplifier A becomes almost zero. Then, the current between the line terminals LT ₁ and LT ₂ is balanced, thereby stabilizing the current value between the line terminals LT ₁ and LT ₂ .

Note that the power supply voltage from the receiving section is applied to the line terminals LT ₁ and LT ₂ via a two-wire line.
This is stabilized by a constant voltage diode ZD and then supplied as the power supply voltage V _DD to each part.

In addition, the line current between line terminals LT ₁ and LT ₂ is within the change range 4 specified in the field of industrial measurement.
It is a unified signal of ~20 mA, and is adjusted by the potentiometer RV ₁ so that the line current becomes a reference current of 4 mA in the balanced state of the differential capacitive sensor DS, and the range of change is controlled by the potentiometer. RV ₂
However, since the voltages from each potentiometer RV ₁ and RV ₂ are applied to the differential amplifier A via an adder circuit made up of resistors R ₄ to _{R 6} , it is possible to adjust the reference current and the range of variation. are carried out without mutual interference.

FIG. 16 is a circuit diagram in the case where the pulse signal obtained from the count output n of the counter CT is a double current signal with both positive and negative polarities, and the configuration of the output section OT is slightly different from that in FIG. 15. counter
Both +E and -E power supply voltages are applied to CT.

In other words, the output section OT is connected to the line terminals LT ₁ and LT ₂
The power supply voltage applied to is stabilized by a constant current circuit with FET Q ₈ and a constant voltage diode ZD, and both positive and negative power supply voltages +E and -E are set.
The intermediate voltage set by resistors R ₇ and R ₈ and potentiometer RV ₁ is applied to the inverting input of differential amplifier A, and is used as the operating reference voltage of differential amplifier A, and the count output n of counter CT is “H”. ”, a pulse signal with a peak value of +E is generated, and when it is “L”, a pulse signal with a peak value of −E is generated, so this is an integral signal formed by resistors R _3A and R _3B and capacitors C _3A and C _3B . If averaged by the circuit, the "H" period of the pulse signal corresponds to the first capacitance C ₁ in FIG. 15, and the "L" period corresponds to the second capacitance C ₂ , so that (C ₁ - The calculation of C ₂ )/(C ₁ +C ₂ ) is performed, and the same direction and equivalent fluctuations of the first and second capacitances C ₁ and C ₂ are eliminated.

The output of the integrator circuit indicating the result of this calculation is applied to the non-inverting input of the differential amplifier A, where it is amplified as a difference from the reference voltage of the inverting input, controls FET Q ₇ , and connects the line terminals LT ₁ , The current value that passes between _LT2 is determined.

In addition, the current of FET Q ₇ is connected to the feedback resistor R ₁₀
This terminal voltage is given as negative feedback to the non-inverting input of differential amplifier A via resistor _R9 , thereby stabilizing the current value of FET _Q7 . .

Note that if a CMOS type counter CT is used, a pulse signal with a peak value that is approximately equal to the power supply voltages +E, -E can be obtained.
By stabilizing E, the peak value of the pulse signal is also stabilized and becomes suitable.

However, this relationship is also the same for the counter CT shown in FIG.

In addition, the counter CT shown in Figures 15 and 16
As a counter, a 1-bit counter such as a flip-flop circuit may be used. In this case, the first and second gates G _2A and G _2B are input every cycle of the output signal of the inverter G ₁ shown in FIG. 5C. on·
A switch off takes place.

Furthermore, it is also possible to use something other than the CMOS type for the first and second gates G _2A , G _2B and the inverter G ₁ , but if the CMOS type is used, the output peak value will be regulated for the reasons mentioned above, so the output wave Due to high price regulations, the need to use a separate switching circuit or the like is eliminated, and the circuit configuration can be simplified.

However, in the case of CMOS type, a diode is generally added to the input side to prevent excessive input, so
In order to operate within the linear region of the input/output characteristics, it is desirable to add a voltage dividing capacitor between the input of inverter _G1 and the reference potential.

In addition, as the first and second gates G _2A and G _2B
The present invention can be modified in various ways, such as using a combination of an AND gate and an inverter, and selecting the output section OT according to the conditions.

As is clear from the above description, according to the present invention, a displacement conversion device with conversion characteristics that essentially eliminates the influence of distributed capacitance is realized, and therefore great effects can be obtained in remote measurement of various physical quantities.

[Brief explanation of drawings]

Fig. 1 is a sectional view showing an example of a single capacitance type sensor, Fig. 2 is an equivalent circuit of Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of the first invention, and Fig. 4 is a constant value current limiting circuit. A circuit diagram showing an example, Fig. 5 is a diagram showing waveforms of each part in Fig. 3, Fig. 6 is a conceptual diagram of a differential capacitance type sensor, Fig. 7 is an equivalent circuit of Fig. 6, and Fig. 8 is A sectional view showing an example of a differential capacitance type sensor, FIG. 9 is a sectional view similar to FIG. 8 when a shield is provided, and FIG. 10 is a block diagram showing an embodiment of the second and third inventions. Figure 11 is the equivalent circuit when charging, Figure 12 is the equivalent circuit when discharging, and Figures 13 and 14 are the equivalent circuit when parallel distributed capacitance is considered.
1 and 12, FIG. 15 is a circuit diagram showing an embodiment of the fourth invention, and FIG. 16 is a circuit diagram for obtaining a double current pulse signal from a counter. G ₁ ... 1st inverter (inverter), G ₂ ...
2nd inverter, G _2A ... 1st gate, G _2B ...
Second gate, C ₁ ... first capacitance (capacitance),
C ₂ ... second capacitance, CC ... constant value current limit circuit,
CT...Counter, _R3 , _R3A , _R3B ...Resistor,
C ₃ , C _3A , C _3B ... Capacitor, OT ... Output section,
LT ₁ , LT ₂ ...Line terminals.

Claims (1)

[Claims] 1. A capacitance that changes according to a physical change to be detected, an amplification means having one end of the capacitance connected to its input point, and the amplification device that is in phase with the input signal. feedback means for feeding back the output of the means to the other end of the capacitance with low output impedance; and a constant current connected between the output of the amplifying means and the input point, the phase of which is opposite to the signal at the input point. A capacitive displacement transducer comprising a limiting circuit and a compensation capacitor connected across the fixed value current limiting circuit. 2 first and second capacitances, at least one of which changes in response to a physical change to be detected, and one end of each of which is commonly connected; an amplifying means with the common connection point connected to its input point; A constant value current limiting circuit connected between the output of the amplifying means and the above input point having a phase opposite to the signal at the input point, a compensation capacitor connected to both ends of the constant value current limiting circuit, and an output signal of the amplifying means. a counter that counts a fixed number of , and the output of the amplifying means, which is in phase with the input point, is sent to the other end of each of the first and second capacitors via a feedback means according to the count output of the counter, and a low output is sent to the other end of each of the first and second capacitors. A capacitive displacement transducer equipped with switching means for selectively connecting by impedance. 3. first and second capacitances that vary differentially in accordance with the physical change to be detected and have one end of each connected in common, and an amplification means with the common connection point connected to its input point; a constant value current limiting circuit connected between the output of the amplifying means which is in opposite phase to the signal at the input point and the above input point; a compensation capacitor connected to both ends of the constant value current limiting circuit; and an output of the amplifying means. a counter that counts a certain number of signals; and the output of the amplifying means that is in phase with the input point based on the count output of the counter is passed through the feedback means to the first
and switching means selectively connected to the other end of each of the second capacitors with low output impedance. 4. first and second capacitances that vary differentially in response to a physical change to be detected and have one end of each capacitance connected in common, and an amplification means with the common connection point connected to its input point; a constant value current limiting circuit connected between the output of the amplifying means which is in opposite phase to the signal at the input point and the above input point; a compensation capacitor connected to both ends of the constant value current limiting circuit; and an output of the amplifying means. a counter that counts a fixed number of signals; and a count output of the counter that outputs the output of the amplifying means that is in phase with the input point to the other end of each of the first and second capacitances via feedback means. a switching means for selectively connecting the output impedance; an integrating circuit for averaging the pulse signals obtained from the count output of the counter;
A capacitive displacement converter equipped with an output section that converts into a current value that passes through a wire line. 5 Claims 1 and 2 characterized in that a MOS inverter is used as the amplification means.
3. The capacitive displacement converter according to item 3, item 4, or item 4. 6. The capacitive displacement converter according to claim 2, 3, or 4, characterized in that a CMOS gate is used as the switching means. 7. The capacitive displacement converter according to claim 2, 3, or 4, characterized in that a CMOS type counter is used as the counter.