JP2651187B2 - Charge level detection circuit - Google Patents

Charge level detection circuit

Info

Publication number
JP2651187B2
JP2651187B2 JP8231788A JP8231788A JP2651187B2 JP 2651187 B2 JP2651187 B2 JP 2651187B2 JP 8231788 A JP8231788 A JP 8231788A JP 8231788 A JP8231788 A JP 8231788A JP 2651187 B2 JP2651187 B2 JP 2651187B2
Authority
JP
Japan
Prior art keywords
level detection
detection circuit
external terminal
circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP8231788A
Other languages
Japanese (ja)
Other versions
JPH01254874A (en
Inventor
和哉 三瀧
啓之 木原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SHICHIZUN TOKEI KK
Original Assignee
SHICHIZUN TOKEI KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SHICHIZUN TOKEI KK filed Critical SHICHIZUN TOKEI KK
Priority to JP8231788A priority Critical patent/JP2651187B2/en
Publication of JPH01254874A publication Critical patent/JPH01254874A/en
Application granted granted Critical
Publication of JP2651187B2 publication Critical patent/JP2651187B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、容量性素子の充放電時に保護回路の持つイ
ンピーダンスによる電圧降下の影響を受けること無く容
量性素子の充電電圧レベルを検出する事を可能とする充
電レベル検出回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is to detect a charging voltage level of a capacitive element without being affected by a voltage drop due to an impedance of a protection circuit during charging and discharging of the capacitive element. The present invention relates to a charge level detection circuit that enables the following.

〔従来の技術〕[Conventional technology]

従来の充電レベル検出回路は第2図に示される様な構
成となっている。
The conventional charge level detection circuit has a configuration as shown in FIG.

即ち、1の抵抗素子、2の容量性素子、そして半導体
集積回路10内に形成された3の第1外部端子、4の第2
外部端子、5の第1保護回路、7の第2保護回路、8の
演算増幅器及び9のレベル検出回路により構成される。
That is, one resistive element, two capacitive elements, and three first external terminals formed in the semiconductor integrated circuit 10, and a second external terminal
It comprises an external terminal, a first protection circuit of 5, a second protection circuit of 7, an operational amplifier of 8, and a level detection circuit of 9.

ここで、前記抵抗素子1の抵抗値をR、該抵抗素子1
に入力される電圧をVin、前記容量性素子2の容量値を
C、前記第2外部端子4での充電電圧をVc、前記演算増
幅器8の出力電圧をVoutとすると、 Vc=−Vin/R・C×t (t:演算時間) となり、充電電圧Vcは第3図に示す時間に比例した波形
となる。そして前記レベル検出回路9により検出電圧Vk
を識別し、任意の動作を行う。この時、充電電圧Vcが検
出電圧Vkに達するまでの検出時間tkをカウントすること
により、検出電圧Vkをデジタル値に置き換えるA/D変換
として応用できる。
Here, the resistance value of the resistance element 1 is R,
Where Vin is the input voltage, C is the capacitance value of the capacitive element 2, Vc is the charging voltage at the second external terminal 4, and Vout is the output voltage of the operational amplifier 8. Vc = −Vin / R C × t (t: calculation time), and the charging voltage Vc has a waveform proportional to the time shown in FIG. The level detection circuit 9 detects the detection voltage Vk.
And perform any operation. At this time, by the charge voltage Vc counts the detection time t k until reaching the detection voltage Vk, it can be applied to the detection voltage Vk as the A / D converter to be replaced with a digital value.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかしながら、従来の充電レベル検出回路では前記第
2保護回路7の持つ抵抗成分により該第2保護回路の両
端に電位差が生じてしまう。このため、前記演算増幅器
8の出力電圧Voutと容量性素子2の充電電圧Vcとは第3
図に示す様に|Vc|<|Vout|という差異が生じてしまう。
この時、前記レベル検出回路9の入力側は演算増幅器8
の出力電圧Voutを検出しているため前記出力電圧Voutが
検出電圧Vkに達した時点で、前記充電電圧Vcが検出電圧
Vkに達していないにも関わらず検出電圧Vkを検出したも
のと判断し、誤検出時間tkをカウントしてしまってい
た。しかも第2保護回路7の持つ成功成分は半導体物質
で形成されており、熱・光等の影響により大きく抵抗値
が変化し、前記出力電圧Voutと充電電圧Vcとの差異は一
定でなく常に不安定であり、信頼性に欠けるという問題
があった。
However, in the conventional charge level detection circuit, a potential difference occurs between both ends of the second protection circuit due to the resistance component of the second protection circuit 7. Therefore, the output voltage Vout of the operational amplifier 8 and the charging voltage Vc of the capacitive element 2 are equal to the third voltage.
As shown in the figure, the difference | Vc | <| Vout | occurs.
At this time, the input side of the level detection circuit 9 is connected to the operational amplifier 8
Since the output voltage Vout is detected, the charging voltage Vc becomes the detection voltage at the time when the output voltage Vout reaches the detection voltage Vk.
It is determined that it detects a detection voltage Vk in spite of the not reached the Vk, had gotten a count of the false detection time t k. In addition, the successful component of the second protection circuit 7 is formed of a semiconductor material, and its resistance value largely changes due to the influence of heat, light, etc., and the difference between the output voltage Vout and the charging voltage Vc is not constant but always constant. There was a problem that it was stable and lacked reliability.

本発明の目的は、充電電圧の誤検出を無くし、検出精
度に優れた充電レベル検出回路を提供するものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a charge level detection circuit which eliminates erroneous detection of a charge voltage and has excellent detection accuracy.

〔課題を解決するための手段〕[Means for solving the problem]

上記目的を達成するための本発明の構成は、第1及び
第2外部端子と、前記第1外部端子に入力側を接続し第
2外部端子に出力側を接続してなる演算増幅器と、前記
第2外部端子に入力側を接続してなるレベル検出回路と
を有する半導体集積回路と、前記第1及び第2外部端子
間に接続された容量性素子と、前記第1外部端子に接続
された抵抗素子よりなる信号入力部とにより構成された
充電レベル検出回路に於いて、前記第1外部端子と演算
増幅器の入力側との間に第1保護回路を、又前記第2外
部端子とレベル検出回路の入力側との間に第2保護回路
をそれぞれ接続すると共に、前記第2外部端子と演算増
幅器の出力側との間には前記第2保護回路を経由しない
接続回路が形成されている。
In order to achieve the above object, a configuration of the present invention comprises first and second external terminals, an operational amplifier having an input side connected to the first external terminal and an output side connected to a second external terminal, A semiconductor integrated circuit having a level detection circuit having an input connected to a second external terminal; a capacitive element connected between the first and second external terminals; and a capacitor connected to the first external terminal. In a charge level detection circuit constituted by a signal input section comprising a resistance element, a first protection circuit is provided between the first external terminal and the input side of the operational amplifier, and a level detection circuit is provided between the second external terminal and the input terminal. A second protection circuit is connected to the input side of the circuit, and a connection circuit that does not pass through the second protection circuit is formed between the second external terminal and the output side of the operational amplifier.

さらに、前記第2外部端子と演算増幅器の出力側との
間の接続回路に第3保護回路を接続したことを特徴とす
る。
Further, a third protection circuit is connected to a connection circuit between the second external terminal and the output side of the operational amplifier.

〔実施例〕〔Example〕

以下本発明の実施例を図面に基づいて詳述する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第1図は本発明による充電レベル検出回路の構成図で
あり、第1図の構成図に於いて第2図の構成図との共通
部分には同一番号を付し、説明を省略する。第1図に於
いて第2図と異なった部分について説明すると、6は第
3保護回路であり、第2外部端子4と演算増幅器8の出
力側との間に形成されている。これにより、前記演算増
幅器8の出力側及びレベル検出回路9の入力側は第2外
部端子4との間に互いに独立した接続経路を設けたこと
になる。
FIG. 1 is a configuration diagram of a charge level detection circuit according to the present invention. In the configuration diagram of FIG. 1, the same parts as those of the configuration diagram of FIG. In FIG. 1, a portion different from FIG. 2 will be described. Reference numeral 6 denotes a third protection circuit, which is formed between the second external terminal 4 and the output side of the operational amplifier 8. Thus, an independent connection path is provided between the output side of the operational amplifier 8 and the input side of the level detection circuit 9 with the second external terminal 4.

次に、上記構成を有する充電レベル検出回路の動作を
説明する。但し、第1図の構成図に於ける第2図の構成
図との共通部分についての動作説明は省略する。
Next, the operation of the charge level detection circuit having the above configuration will be described. However, the description of the operation of the common part of the block diagram of FIG. 1 with the block diagram of FIG. 2 is omitted.

前記外部端子4の充電電圧Vc及び演算増幅器8の出力
電圧Voutは第3図に示す波形となり、第2図に示す従来
の構成図の場合と同じである。しかし、前記レベル検出
回路9の入力側は第2外部端子4との間に電流の流れの
無い独立した接続経路を持っており、従って前記第2保
護回路7の両端間に電位差は生じない。即ち前記レベル
検出回路9は充電電圧Vcの真値を判別することにより、
検出電圧Vkを高精度で検出可能となる。
The charging voltage Vc of the external terminal 4 and the output voltage Vout of the operational amplifier 8 have the waveforms shown in FIG. 3, which are the same as those in the conventional configuration shown in FIG. However, the input side of the level detection circuit 9 has an independent connection path through which no current flows between the input terminal and the second external terminal 4, so that no potential difference occurs between both ends of the second protection circuit 7. That is, the level detection circuit 9 determines the true value of the charging voltage Vc,
The detection voltage Vk can be detected with high accuracy.

〔発明の構成〕[Configuration of the invention]

以上の説明で明らかなように、本発明によれば容量性
素子からレベル検出回路までの接続経路に電圧降下を生
じさせないことにより、誤まった電圧検出を防ぎ高精度
な充電レベル検出回路の実現を可能としている。
As is apparent from the above description, according to the present invention, a voltage drop does not occur in the connection path from the capacitive element to the level detection circuit, thereby preventing erroneous voltage detection and realizing a highly accurate charge level detection circuit. Is possible.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明による充電レベル検出回路の構成図、第
2図は従来技術による充電レベル検出回路の構成図、第
3図は第2外部端子での充電電圧Vc及び演算増幅器8の
出力電圧Voutの積分時間tに対する充電波形の関係を示
す特性図である。 1……抵抗素子、 2……容量性素子、 5……第1保護回路、 6……第3保護回路、 7……第2保護回路、 8……演算増幅器、 9……レベル検出回路、 10……半導体集積回路。
1 is a configuration diagram of a charge level detection circuit according to the present invention, FIG. 2 is a configuration diagram of a charge level detection circuit according to the prior art, and FIG. 3 is a charge voltage Vc at the second external terminal and an output voltage of the operational amplifier 8. FIG. 9 is a characteristic diagram showing a relationship between a charging waveform and an integration time t of Vout. DESCRIPTION OF SYMBOLS 1 ... resistance element, 2 ... capacitive element, 5 ... 1st protection circuit, 6 ... 3rd protection circuit, 7 ... 2nd protection circuit, 8 ... operational amplifier, 9 ... level detection circuit 10 ... Semiconductor integrated circuit.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】第1及び第2外部端子と、前記第1外部端
子に入力側を接続し前記第2外部端子に出力側を接続し
てなる演算増幅器と、前記第2外部端子に入力側を接続
してなるレベル検出回路とを有する半導体集積回路と、
前記第1及び第2外部端子間に接続された容量性素子
と、前記第1外部端子に接続された抵抗素子よりなる信
号入力部とにより構成された充電レベル検出回路に於い
て、前記第2外部端子と前記演算増幅器の出力側との間
に保護回路を設け、前記第2の外部端子と前記レベル検
出回路との間には前記保護回路を経由しない接続回路が
形成されていることを特徴とする充電レベル検出回路。
An operational amplifier having an input side connected to the first external terminal and an output side connected to the second external terminal; and an input side connected to the second external terminal. A semiconductor integrated circuit having a level detection circuit formed by connecting
In the charge level detection circuit including a capacitive element connected between the first and second external terminals and a signal input unit including a resistance element connected to the first external terminal, A protection circuit is provided between an external terminal and the output side of the operational amplifier, and a connection circuit that does not pass through the protection circuit is formed between the second external terminal and the level detection circuit. Charge level detection circuit.
JP8231788A 1988-04-05 1988-04-05 Charge level detection circuit Expired - Lifetime JP2651187B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8231788A JP2651187B2 (en) 1988-04-05 1988-04-05 Charge level detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8231788A JP2651187B2 (en) 1988-04-05 1988-04-05 Charge level detection circuit

Publications (2)

Publication Number Publication Date
JPH01254874A JPH01254874A (en) 1989-10-11
JP2651187B2 true JP2651187B2 (en) 1997-09-10

Family

ID=13771189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8231788A Expired - Lifetime JP2651187B2 (en) 1988-04-05 1988-04-05 Charge level detection circuit

Country Status (1)

Country Link
JP (1) JP2651187B2 (en)

Also Published As

Publication number Publication date
JPH01254874A (en) 1989-10-11

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