JPH0460531B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a displacement conversion device that converts displacement due to differential pressure or pressure into an electrical signal via capacitance, and particularly relates to a displacement conversion device with improved resolution. This invention relates to a displacement conversion device.

<Prior Art> FIG. 13 shows a conventional displacement converter disclosed in Japanese Patent Application Laid-Open No. 57-26711 "Capacitive Displacement Converter", and this will be explained.

Cx is a capacitance whose capacitance value changes in response to displacement due to pressure or the like. One end of the capacitance Cx is connected to the input end of the inverter _G1 , and is also connected to the common potential point COM via the distributed capacitance Cs. A bidirectional constant current circuit CC is connected between the input and output ends of the inverter _G1 , and its output end is connected to the other end of the capacitor Cx via the inverter _G2 . Here, the inverters G ₁ and G ₂ form an amplifying means, and feed back a voltage in phase with the voltage at the input terminal of the inverter G ₁ from the output of the inverter G ₂ to the capacitor Cx.
Further, the bidirectional constant current circuit CC constitutes a feedback means that feeds back the voltage at the input end of the inverter _G1 in the opposite phase.

Next, the operation of the displacement converter shown in FIG. 13 will be explained using the waveform diagram shown in FIG. 14.

When the output of inverter _G2 is at a high level "H" and a voltage +E occurs (Fig. 14A), the series circuit of capacitance Cx and distributed capacitance Cs is rapidly charged by the rise of the voltage, and the terminal of distributed capacitance Cs is charged. Since the voltage suddenly reaches a constant voltage, it rises almost vertically as shown in FIG. 14B. Also, at this time, inverter G ₁
Since the output of is low level "L" and the zero potential of the common potential point COM, the charge in the distributed capacitance Cs is immediately discharged with a constant current i via the bidirectional constant current circuit CC and the output impedance of the inverter _G1 . As shown in FIG. 14B, the voltage at the input terminal of inverter _G1 decreases linearly. Inverter G ₁
When _the voltage drops to the _threshold voltage V _TH of capacity
After the residual charge of Cs is rapidly discharged through the capacitance Cx and the voltage at the input terminal of inverter _G1 drops vertically, the bidirectional constant current circuit is activated by the high level "H" at the output terminal of inverter _G1 . Constant current i due to CC
As a result, the distributed capacitance Cs is charged, and the voltage at the input terminal of the inverter _G1 increases linearly (Fig. 14C).
When the threshold voltage V _TH is reached, the output of inverter G ₁ is inverted to low level “L” and the output of inverter G ₂ becomes high level “H”, so charging from inverter G ₂ is performed again. ,
This operation is repeated.

Here, the changing voltage e ₁₀ across the distributed capacitance Cs with respect to the threshold voltage V _TH is expressed by the following equation.

e ₁₀ =Cx/Cx+CsE (1) Moreover, the time t ₁₀ required for the changing voltage e ₁₀ to decrease to the threshold voltage V _TH is given by the following equation.

it ₁₀ = e ₁₀ (Cx+Cs)...(2) Using equations (1) and (2), t ₁₀ = CxE/i...(3). Note that as charging and discharging are repeated, a charge corresponding to the threshold is determined as a reference potential in the distributed capacitance Cs, and charging and discharging are performed around this. Therefore, the changing voltage e ₁₀ on the charging side and the changing voltage on the discharging side e ₂₀ becomes equal, and by performing charging for this variable voltage e ₂₀ with constant current i from the bidirectional constant current circuit CC, times t ₁₀ and t ₂₀ become equal, and the following equation holds true.

t ₁₀ = t ₂₀ = E/iCx ...(4) Therefore, the periods t ₁₀ and t ₂₀ are proportional to the capacitance Cx,
The capacitance Cx changes depending on the displacement of the opposing electrodes.

<Problems to be Solved by the Invention> In such a conventional displacement conversion device, the period t ₁₀ (t ₂₀ ) of the output pulse signal is such that the capacitance Cx changes in a predetermined width for a displacement in a predetermined width. It works like this.

Therefore, when the fluctuation width of the displacement is small, the fluctuation range of the capacitance Cx is also small, which causes a problem that the resolution becomes small and the accuracy deteriorates.

<Means for solving the problems> In order to solve the above problems, the present invention has the following features:
A capacitance that changes according to the displacement to be detected, an amplifying means with one end of this capacitance connected to an input end, and a negative feedback means for supplying an inverted current from the output end of the amplifying means to its input end. , a drive means for driving the other end of the capacitance in an opposite phase to the input of the amplification means, one end of which is connected to the input end of the amplification means, and the other end connected to the input of the amplification means. A predetermined calculation is performed using a fixed capacitor with a capacitance value larger than the previous capacitance driven by the same phase voltage and a pulse signal related to the output of the previous amplification means to generate an output corresponding to the previous displacement. The main configuration is that the system is equipped with a microcomputer means for outputting data.

<Function> With the main configuration of the present invention as described above, a pulse signal having a pulse width corresponding to the displacement is output with a portion of the capacitance reduced by a predetermined value.
Resolution is expanded and accuracy is improved.

<Example> Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. Note that parts having the same functions as those in the prior art are designated by the same reference numerals, and their explanations will be omitted as appropriate.

One end of the capacitance Cx is connected to the input end of the inverter _G1 , and is also connected to the common potential point COM via the distributed capacitance Cs. A bidirectional constant current circuit CC is connected between the input and output terminals of the inverter _G1 to form a negative feedback path. In addition, the other end of the capacitance Cx is connected from the output end of the inverter G ₁ to one end of the input of the AND gate G ₃ and its output end, and the other end of the AND gate G ₃ is connected through the terminal TL ₁ . Its opening/closing is controlled by a control signal CS. Furthermore, a series circuit of a fixed capacitor C _F and an inverter G ₄ is connected between the input and output terminals of the inverter G ₁ .
The output pulse signal is taken out from the output end of the inverter _G1 via the terminal _TL2 . In addition, each inverter G ₁ , G ₄ and AND gate G ₃ are connected to the power supply voltage +
It is energized by E.

Next, the operation of the capacitance/time converter CTV ₁ shown in FIG. 1 and configured as described above will be explained using FIGS. 2 and 3.

First, a state in which the control signal CS is at a high level "H" and +E as shown in FIG. 3A will be explained.
In this case, AND gate G ₃ functions simply as a buffer gate.

When the output terminal of the inverter G ₁ is at a high level "H" during period T _X (FIG. 3C), the input terminal of the inverter G ₁ is connected as shown in FIG. 2A. In this state, since a voltage of +E is applied to the other end of the bidirectional constant current circuit CC, each capacitor is charged by this, and the voltage at the input end of the inverter _G1 rises at a constant rate, resulting in its threshold voltage V _TH When the voltage at the output end of the inverter _G1 exceeds the voltage (FIG. 3(b)), the voltage at the output terminal of the inverter G1 is inverted to the low level "L", resulting in the state shown in FIG. 2(b).

The charging charge of each capacitor immediately before it is reversed from A to B in Figure 2 is (C _F +Cx + Cs)V _TH - from A in Figure 2.
CxE, and if the voltage at the input terminal of the inverter _G1 at this time is V ⁺ , the charge in each capacitor immediately after inversion becomes ( _CF +Cx+Cs)V ⁺ _-CFE from FIG. 2B. Since the total amount of charge immediately before and after the inversion does not change, the following equation holds true.

(C _F +Cx+Cs)V _TH −CxE=(C _F +Cx+Cs)V ⁺ −C _F E ∴V ⁺ =V _TH +C _F −Cx/(C _F +Cx+Cs)E……(5) The second term is the threshold voltage V The changing voltage e ₁ increases from _TH , and this changing voltage e ₁ increases the constant current i of the bidirectional constant current circuit CC up to the threshold voltage V _TH .
The period _TX , which is the time reduced by , is given by:

iT _{X ′} =e _{1 ′ (} CF + _C (7) is obtained. Threshold voltage V _TH of inverter G ₁
When the voltage at the input terminal reaches , the output terminal of the inverter _G1 is inverted to a high level "H" and becomes the state shown in FIG. 2A. However, instead of V ⁺ in Figure 2 B, V _TH ,
The voltage V ^- at the input terminal of the inverter G ₁ is substituted for V _TH in Figure 2 A. Therefore, the relationship between the charges immediately before and after the inversion in this case is (C _F +Cx+Cs)V _TH −C _F E=(C _F +Cx+Cs)V ^- −CxE ∴V ^- =V _TH −C _F −Cx/( C _F + Cx + Cs) E...(8). The second term is the changing voltage e ₁ that drops from the threshold voltage V _TH , and the period is the time during which this changing voltage e ₁ is increased to the threshold voltage V _TH by the constant current i of the bidirectional constant current circuit CC.
T _X is given by the following formula.

_{iT _ _ _ _ _} obtain. From equations (7) and (10), the periods T _X and T _X ′ are equal,
In both cases, a pulse signal having a period corresponding to the difference between the capacitance Cx and the fixed capacitance _CF is obtained at the terminal TL ₂ . In this case, oscillation will not continue unless the relationship C _F > Cx is satisfied. Comparing equations (4) and (10) here, we find that in equation (4), the period corresponding to the capacitance Cx is
The oscillation with t ₁₀ is repeated, but in equation (10), the oscillation has _a period _T It can be made larger and the resolution is improved.

The above holds true if the constant current i, the power supply voltage E are constant, and the fixed capacitance C _F is known, but by adding an operation to switch the control signal CS to the low level "L" zero state, this can be changed. The resolution can be improved even if the value is not necessarily constant or known. Next, this point will be explained.

In this case, the other end of capacitance Cx is connected to the inverter.
Regardless of level changes at the output terminal of _G1 , oscillation is repeated via a series circuit of inverter _G4 and fixed capacitor C _E while being fixed at a low level "L". Therefore, if the other end of the capacitance Cx is connected to the common potential point COM in Figure 2 and the control signal CS is at a high level, the period T _F1 is calculated as follows.
T _F1 ′ (Figure 3 C) is as follows.

T _F1 = T _F1 '= C _F / iE ...... (11) Therefore, from equations (10) and (11), when C _F is constant, Cx = C _F (T _F1 / T _X -1) ...(12) When i is constant, the terminal is controlled by manipulating the control signal CS as Cx=i/E(T ₁ - T _X ) ...(13)
The unknown capacitance Cx can be determined using the period T _F1 and T _X of the pulse signal appearing at TL ₂ .

FIG. 4 is a block diagram showing an embodiment in which the capacitance is a differential capacitance in which the capacitance changes differentially with respect to each other.

Inverters G ₁ and G ₅ are connected in series to form an amplifier, and inverters G ₆ ,
A series circuit of G ₇ and fixed capacitance C _F is connected in positive feedback. Furthermore, a series circuit of inverters G _{8 ,} G ₉ and a bidirectional constant current circuit CC is connected together with inverter G ₆ by negative feedback between the output terminal of inverter G 6 and the input terminal of inverter G ₁ .

Furthermore, a fixed electrode FD ₁ facing the moving electrode MD,
The other ends of the differential capacitors C _H and _CL formed by FD ₂ are connected to the output end of the inverter G ₆ and the AND gates G _{10 and 2} , respectively.
Connected via _G11 . The output end of inverter _G5 is connected to the input end CL of counter _CT1 , and its n-bit output end Qn is connected to the input ends of AND gates _G10 and _G11 via inverter _G12 or directly.

DL is a latch, and a control signal CS is applied to its data terminal D, and a control signal corresponding to the rising edge of the counter output applied to its clock terminal C.
AND gate the level of CS through output terminal Q
Apply to the input terminals of G ₁₀ and G ₁₁ .

Next, the capacity/time converter configured as above
The operation of CTV ₂ will be explained using the waveform diagram shown in FIG.

First, the case where the control signal CS is at a high level "H" and in the +E state as shown in FIG. 5A will be described. In this case, the output of the latch DL is at a high level.

The output of counter CT ₁ is high level “H” (5th
In the state of period T _L shown in FIG. 5C (FIG. 5D), the output terminal of the AND gate _G10 is maintained at the low level "L", and the fixed electrode _FD1 is maintained at zero potential. Therefore, in this case, the differential capacitance C _H is connected in parallel to the distributed capacitance Cs in Figure 1, and the capacitance Cx
Since the relationship is functionally equivalent to that in which differential capacitance C _L is connected instead of , the following equation is obtained in the same way as equations (7) and (10) were derived.

T _L = n (C _F - C _L /i) E ... (14) However, in the case shown in Fig. 4, an AND gate is used while counting n bits of counter CT ₁ , compared to the case shown in Fig. 1. Since the differential capacitor C _L side is selected by G ₁₀ and G ₁₁ and oscillation is repeated, it is multiplied by n in equation (14).

When the output level of the inverter G ₁ (G ₅ ) is inverted n times, the output of the counter CT ₁ is inverted to the low level "L" (FIG. 5C) and enters the state of period T _H. In this state, the output of AND gate _G11 becomes low level and is fixed at zero potential. Therefore, in this case, the relationship is functionally equivalent to the relationship in Figure 1 where differential capacitance C _L is connected in parallel to distributed capacitance Cs and differential capacitance C _H is connected in place of electrostatic capacitance Cx. The following equation is obtained in the same way as equation (14) was derived.

T _H =n(C _F -C _H /i)E...(15) The above state is repeated. Therefore, the fixed capacitance C _F
The period corresponding to the difference between and the differential capacitance C _L or C _H
Since oscillation occurs with T _L and T _H , the differential capacitance C _L and C _H
A pulse signal of a frequency in which the ratio of the variable component becomes large can be obtained from the terminal TL ₂ , resulting in a capacitance/time converter CTV ₂ with high resolution.

However, if the constant current i and the power supply voltage E change over time and are not constant, or if the fixed capacitance is not known, the accuracy can be further improved by taking the following measures.

In this case, the control signal CS is inverted to low level "L" as shown in FIG. 5A. At this time, the output of the latch DL is inverted to low level "L" according to the rising timing of the output of the counter _CT1 (FIG. 5C). In this state, the AND gate
The outputs of G ₁₀ and G ₁₁ are both fixed at low level "L" and have zero potential. Therefore, in this case, the first
In the figure, differential capacitances C _L and C _H are connected in parallel to the distributed capacitance Cs.
is equivalent to connected, and the following equation can be obtained in the same way as equation (11) was derived.

T _F2 = n C _F /iE ...(16) Therefore, from equations (14), (15), and (16), when C _F is constant, When i is constant, terminal by manipulating the control signal CS as
The unknown differential capacitances C _L and C _H can be determined using the periods T _F2 , T _L , and T _H of the pulse signals appearing at TL ₂ .

Note that there is stray capacitance at both ends of the bidirectional constant current circuit CC.
When Ci exists and there is a delay Td in the oscillation path as a whole, the periods T _L ′, T _H ′, and T _F2 ′ are T _L ′=n(C _F2 −C _L −Ci)/iE+Td …… (19) T _H ′=n(C _F2 −C _H −Ci)/iE+Td ……(20) T _F2 ′=n(C _F2 −Ci)/iE+Td ……(21) These expressions _{When using _ _ _ _} Td is removed. In particular, when the differential capacitances C _L and C _H become smaller, errors due to delays in the oscillation path tend to occur, but in this case, according to equations (22) and (23), they do not become a cause of errors.

FIG. 6 is a block diagram showing the configuration of a microcomputer section which receives pulse signals from the capacitance/time conversion sections CVT ₁ and CVT ₂ and processes the signals.
The case where CVT ₂ is used as a capacity/time converter will be explained as an example.

Reference numeral 10 denotes a microcomputer section to which a pulse signal from the capacitance/time conversion section CVT ₂ is input, processes the signal, and outputs the signal. 11 is a timer counter that converts a time signal into a digital value. 12 is
RAM (random access memory), 13 is ROM
(read-only memory), and these addresses are specified from the CPU (processor) 14 to the bus 15,
This is done via the latch recorder 16. Output data from timer counter 11 is stored in RAM 12 via data bus 17. A predetermined calculation program and initial data are stored in the ROM 13, and calculations are performed according to the calculation procedure stored in the ROM 13 under the control of the CPU 14, and the results are stored in the RAM 12. 18 is a control bus, and timer counter 1 is controlled by the CPU 14.
1. Controls the operations of the RAM 12 and ROM 13 and outputs a control signal CS to the capacity/time converter CVT ₂ .

The final calculation result is converted into a duty signal by a timer counter 19, and the duty signal is converted into an analog signal by a duty/analog converter 20 and outputted to an output terminal 21.

Next, signal processing in the microcomputer section shown in FIG. 6 will be explained using the flowchart shown in FIG.

First, in the step, the period T _F2 is set as initial data.
is set from ROM13 to RAM12. next,
Spring constant K of moving electrode MD, fixed capacitance C _F , constant current i, number of bits n of counter CT ₁ , power supply voltage E, value Co of each differential capacitance C _L and C _H when differential pressure ΔP is zero, etc. is set from ROM 13 to RAM 12 (step). In the step, the capacity/time conversion section
Cycle of pulse signal output from CVT ₂ T _L , T _H
is loaded. Next, using the arithmetic program built into the ROM 13, equations (17), (18) or (22) are
The calculation of equation (23) is executed and the differential capacitances C _L and C _H are calculated (step).

The calculation in the step is performed as follows. The differential capacitances C _L and C _H are each expressed by the following equations.

C _L = Co1/1-KΔP ...(24) C _H = Co1/1-KΔP ...(24) From these formulas, the differential pressure ΔP is ΔP=1/K (C _L −C _H /C _L +C _H ) ...(25) It can be expressed as. Therefore, the differential pressure ΔP is calculated using the calculation program shown in equation (25) stored in the ROM 13 using C and C obtained in step. The calculation result is outputted to an output terminal 21 via a timer counter 19 and a duty/analog converter 20.

Since the period T _F2 does not change in a short time, the period T _L ,
Since the cycle T _F2 can be read in 1/5 to 1/10 cycle of reading T _H , this correction cycle is judged in the step. If the correction cycle is not reached, the process returns to the step, and when the correction cycle is reached, the process returns to the step. The cycle T _F2 is read by manipulating the control signal CS, and thereafter the calculations (17), (18), (22), and (23) are executed using this cycle T _F2 .

FIG. 8 is a block diagram showing a third embodiment of the capacity/time converter. This capacity/time converter
CTV ₃ shows a case where the phase of the moving electrode MD and the input phase of the input terminal CL of the counter CT ₁ are different.
In this case, an inverter _G13 is inserted between the input end CL of the counter _CT1 and the inverter _G5 to invert the input phase of the counter _CT1 . When doing this, insert an inverter _G14 between the output terminal of the counter _CT1 and the clock terminal C of the latch DL,
Moreover, even if OR gates G _{15 and G 16 are inserted in place of AND gates G 10 and} G ₁₁ shown in FIG. 4, the operation is similar to that shown in FIG. 4.

FIG. 9 is a block diagram showing a fourth embodiment of the capacity/time converter. This capacity/time converter
CTV ₄ uses two types of reference capacitance C _F and has two levels of resolution.

A series circuit of a NAND gate _{G 17 and} a fixed capacitor C _F1 , a series circuit of a NAND gate G ₁₈ and a fixed capacitor C _F2 are connected between the output terminal of the inverter G 6 and the input terminal of the inverter G ₁ , respectively. nand gate
G ₁₇ and G ₁₈ are switching signals given via the control bus 18 of the microcomputer section 18
SS ₁ controls G ₁₇ directly and G ₁₈ via inverter G ₁₉ . Accordingly, the output terminals Qn and Qm of counter CT ₁ are switched by switching signal SS ₁ .
Switched simultaneously via SW ₁ .

FIG. 10 is a block diagram showing a fifth embodiment of the capacity/time converter. This capacity/time converter
In CTV ₅ , when the phase of the moving electrode MD and the input phase of the input terminal CL of the counter CT ₁ are different, the power supply voltage that excites the fixed capacitor C _F is switched between two types, +E ₁ and +E ₂ , and fixed via the switch SW ₂ . The capacitance C _F is one piece. The switch SW ₂ and the switch SW ₁ which switch the output ends of the counter CT ₁ are switched by the switching signal SS ₁ .

FIG. 11 is a block diagram showing a sixth embodiment of the capacity/time converter. This capacity/time converter
When the phase of the moving electrode MD and the input phase of the input terminal CL of the counter CT ₁ are in phase, CTV ₆ connects the low voltage side of the power supply voltage that excites the fixed capacitor C _F to +E ₃ and zero via switch SW ₃ . The switching fixed capacitance C _F is set to one. Switch SW ₃ and counter
Switch SW ₁ , which switches the output end of CT ₁ , is a switching signal.
Switched by SS ₁ .

FIG. 12 is a block diagram showing a seventh embodiment of the capacity/time converter. This capacity/time converter
CTV ₇ has three types of fixed capacitors, C _F1 to C _F3 , when the phase of the moving electrode MD and the input phase of the input terminal CL of the counter CT ₁ are different, and the output terminal of the inverter G ₆ and the input terminal of the inverter G ₁ are connected to each other. A series circuit between the Noah gate G ₂₀ and the fixed capacitance C _F1 , the Noah gate
Series circuit of G ₂₁ and fixed capacitance C _F2 , Noah gate G ₂₂
Connect the series circuit with fixed capacitor C _F3 and
These NOR gates are switched in three stages using a switching signal _SS2 .

<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the first invention, the resolution can be improved compared to the conventional one, so it is possible to further improve the accuracy. According to the invention, in addition to the effects of the first invention, there is a change over time in the current value of the bidirectional constant current circuit,
It is possible to eliminate all stray capacitances occurring at both ends, time delays in the oscillation path, and fluctuations in power supply voltage. In particular, as the sensor itself becomes smaller and the differential capacitance itself becomes smaller, errors due to time delays in the oscillation path become larger, and in this case, even more effective effects are exhibited.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the capacitance/time converter of the present invention, FIG. 2 is a connection diagram for explaining the operation of the circuit shown in FIG. 1, and FIG.
The figure is a waveform diagram showing the waveforms of each part of the embodiment shown in Fig. 1, Fig. 4 is a block diagram showing the second embodiment related to the capacitance/time conversion section of the present invention, and Fig. 5 is shown in Fig. 4. 6 is a block diagram showing the overall configuration of the present invention; FIG. 7 is a waveform section showing waveforms of each part of the embodiment;
FIGS. 8 to 12 are block diagrams showing third to seventh embodiments of the capacitance/time converter of the present invention, and FIG. FIG. 14 is a block diagram showing a conventional displacement converter. FIG. 14 is a waveform diagram showing waveforms of various parts of the displacement converter shown in FIG. Cx...Capacitance, Cs...Distributed capacitance, C _L , C _H ...
...differential capacitance, CC...bidirectional constant current circuit, C _F ...
Fixed capacitance, CS...control signal, CT ₁ ...counter,
DL...Latch, CTV ₁ to CTV ₆ ...Capacity/time conversion section, 10...Microcomputer section, 11,
19...Timer counter, 17...Data bus,
18...Control bus, 20...Duty/
analog converter.

Claims (1)

[Claims] 1. A capacitance that changes according to the displacement to be detected, an amplifying means with one end of this capacitance connected to an input end, and an inverting capacitance from the output end of the amplifying means to its input end. negative feedback means for supplying a current; first driving means for driving the other end of the capacitance in phase opposite to the input of the amplifying means; one end of which is connected to the input end of the amplifying means; A fixed capacitor having a capacitance value larger than the capacitance driven by a voltage in phase with the input of the amplifying means and a pulse signal related to the output of the amplifying means are used to perform a predetermined calculation to correspond to the displacement. and a first microcomputer means for outputting an output. 2. A capacitance that changes differentially according to the displacement to be detected, an amplifying means in which the moving end of this capacitance is connected to the input end, and an inverted current flowing from the output end of this amplifying means to its input end. negative feedback means for supplying the control signal, and a cycle of repeating the power supply voltage and a predetermined potential in opposite phase to the input of the amplification means at a predetermined level of the control signal is alternately applied to the two fixed ends of the capacitance, thereby increasing the control signal. a second driving means for fixing the two fixed ends of the capacitance at a predetermined potential at an inversion level; one end is connected to the input end of the amplifying means, and the other end is driven with a voltage in phase with the input of the amplifying means; a fixed capacitor having a capacitance value larger than the capacitance of the capacitor, outputting the control signal based on a predetermined procedure, and performing a predetermined operation using a pulse signal related to the output of the amplifying means to calculate the displacement; and second microcomputer means for producing a corresponding output.