JP3168586B2 - Capacitance measurement circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitance measuring circuit, and more particularly to a capacitance measuring circuit used for a capacitance detecting type position sensor.

[0002]

2. Description of the Related Art This type of capacitance detection type position sensor detects a change in the position of an object to be processed or a position of an object to be controlled by a change in capacitance, and has been widely used.

As shown in FIG. 3, a conventional capacitance measuring circuit comprises a sensor 4, oscillators 8 and 9, and a frequency measuring circuit 10 as shown in FIG.
And was composed of

The sensor 4 includes fixed electrodes P1 and P2 and a movable electrode P3.

[0005] The movable electrode P3 is arranged between the fixed electrodes P1 and P2, interlocks with the object to be controlled, and is electrically grounded.

The capacitance between the fixed electrode P1 and the movable electrode P3 is C1, and the capacitance between the fixed electrode P2 and the movable electrode P3 is C1.
Let it be 2.

When the position of the object to be controlled shifts, the position of the movable electrode P3 shifts in conjunction therewith. At this time, when the movable electrode P3 shifts toward the fixed electrode P1, the capacitance C1 increases,
The capacitance C2 decreases. Conversely, when the movable electrode P3 shifts toward the fixed electrode P2, the capacitance C2 increases and the capacitance C1 decreases.

A capacitor C1 is connected to an oscillator 8 having an oscillation frequency f1.
Further, the capacitors C2 are connected to the oscillators 9 having the oscillation frequency f2, respectively. Since each oscillation frequency is determined by the value of the capacitance, the frequencies f1 and f2 are compared by the frequency comparison circuit 10 to detect a change in the capacitances C1 and C2, that is, a change in the position of the movable electrode P3. Was.

[0009]

In the conventional capacitance measuring circuit described above, when the movable electrode P3 is made small, the capacitances C1, C
2, the oscillation frequency increases, and the operation becomes unstable due to stray capacitance or the like. Therefore, there is a disadvantage that downsizing of the sensor is difficult.

In addition, since the detection is performed using a high-frequency signal, there is a problem that a high-level technique is required for designing and manufacturing the signal processing circuit.

[0011]

SUMMARY OF THE INVENTION A capacitance measuring circuit according to the present invention generates a measuring pulse having a predetermined period, and when one of the levels of the measuring pulse is at one level, the first and second capacitances to be measured are respectively measured. A first and a second measurement pulse supply circuit that supplies a charging current to the first and second capacitances to be measured, and discharges the charge of the first and second capacitances at the other level of the measurement pulse; the first and second load current of each measuring pulse supply circuit and the first and second current detecting circuit for detecting each of said first and second negative charge
And a current comparison circuit for detecting the difference of flow, the first Oyo
And a second current detection circuit are provided at each input terminal.
And the second and third load currents, respectively.
Two current mirror circuits, wherein the current comparison circuit comprises:
Output of each of the first and second current mirror circuits
A third calendar whose ends are connected to the input and output ends respectively
Comprising a Tomira circuit, said first and second measured capacitor
Of the capacitance value difference of the output terminal of the third current mirror circuit.
This is detected based on the current value .

[0012]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a capacitance measuring circuit according to the present invention.

As shown in FIG. 1, the capacitance measuring circuit of the present embodiment includes driving circuits 1 and 2 having the same configuration and a pulse generator 3.
, A sensor 4, current detection circuits 5 and 6, and a current comparison circuit 7.

The driving circuit 1 includes a delay circuit D11, a two-input NOR gate G11, and a two-input NAND gate G1.
2, the inverters E11 and E12, and the transistor Q1
1, Q12 and a capacitor C11.

The delay circuit D11 is composed of even-numbered inverters connected in cascade.

The drive circuit 2 is the same as the drive circuit 1 except that the component numbers are in the 20's.

The transistor Q11 is a P-channel MOS
The transistor Q12 is an N-channel MOS transistor.

The sensor 4 has a fixed electrode P, as in the prior art.
1 and P2 and a movable electrode P3.

The current detection circuits 5 and 6 are current mirror circuits, and their input terminals are connected to power supply terminals VD1 and VD2 of the drive circuits 1 and 2, respectively. An output terminal of the current detection circuit 6 is connected to an input terminal of a current comparison circuit 7 which is a similar current mirror circuit.

The output terminal of the current comparison circuit 7 and the output terminal of the current detection circuit 5 are commonly connected, connected to the output terminal O and the load resistor R, and the multi-terminal of the load resistor R is connected to the bias power source B. .

Next, the operation of this embodiment will be described.

First, a pulse from the pulse generator 3 is applied to the driving circuits 1 and 2. The pulse input to the drive circuit 1 is transmitted to the NOR gate G11, the delay circuit D11,
It is applied in parallel with the ND gate G12. The output of the delay circuit D11 is applied to the other one of the inputs of the NOR gate G11 and the NAND gate G12.

The output of the NOR gate G11 is inverted by an inverter E11 and applied to the gate of a P-channel MOS transistor Q11.

The output of the NAND gate G12 is inverted by an inverter E12 and applied to the gate of an N-channel MOS transistor Q12.

The de Rei down transistors Q11, Q12 are commonly connected to the fixed electrode P1 of the sensor 4 through the output terminal T1. The source of the transistor Q11, while being bypassed pulse component by the capacitor C1 1, and is connected to the power source VD via the current detection circuit 5. The source of transistor Q12 is grounded.

The drive circuit 2 is the same as the drive circuit 1 except that the output is connected to the fixed electrode P2 of the sensor 4 via the output terminal T2.

FIG. 2 shows an operation signal waveform of each part of the drive circuits 1 and 2.

FIG. 2A shows a waveform of an input pulse.

FIG. 2B shows the delay circuit D 1 of the drive circuit 1.
Is a pulse waveform at the output point A of FIG.

FIG. 2C shows a gate input waveform of the transistor Q11.

FIG. 2D shows a gate input waveform of the transistor Q12.

The transistor Q11, which is a P-channel MOS transistor, turns on when the gate input voltage is at a low level, and turns off when the gate input voltage is at a high level.

On the other hand, the transistor Q12, which is an N-channel MOS transistor, is turned on when the gate input voltage is at a high level, and turned off when the gate input voltage is at a low level.

Therefore, the transistors Q11 and Q12 are alternately turned on and off at the pulse repetition frequency f.

At the time of on / off switching, the delay circuit D
1 during the delay time d due to the transistors Q11 and Q12.
Are turned off, so that there is no so-called through current flowing through both transistors regardless of the load.

Of the source current of transistor Q11,
The pulse component is bypassed by the capacitor C11,
The DC component flows to the current detection circuit 5.

Here, the current when the P-channel MOS transistor Q11 is on depends on the capacitance C1 of the fixed electrode P1 of the sensor 4, the floating output capacitance of the transistors Q11 and Q12 and the capacitance of the wiring and the like. This is a transient current that charges the total parasitic capacitance CS1. The amount of charge flowing is the amount of the N-channel MOS transistor Q1.
2 is turned on, and is equal to the amount of charge discharged from the total CS1 of the capacitance C1 of the fixed electrode P1 of the sensor 4 and the stray capacitance or parasitic capacitance.

The time from when the polarity of the input pulse is inverted to when it is further inverted, that is, the duration is determined by the on-resistance and the capacitance C of each of the transistors Q11 and Q12.
It is set to be sufficiently longer than the charge and discharge time constant formed by 1 + CS1, for example, ten times or more. Therefore, the charge q1 charged and discharged in one pulse is represented by the following equation.

Q1 = (C1 + CS1) × VD where V
D is the power supply voltage.

The average current flowing through the current detection circuit 5, that is, the average current I1 of the drive circuit 5, is expressed by the following equation.

I1 = f × q1 = f (C1 + CS1) × VD where f is the pulse repetition frequency.

The operation of the drive circuit 1 has been described above. However, the drive circuit 2 has exactly the same configuration except that the drive circuit 2 is connected to the fixed electrode P2 of the capacitor C2 of the sensor 4.
The average current flowing through the current detection circuit 6, that is, the average current I2 of the drive circuit 6, is expressed by the following equation.

I2 = f (C2 + CS2) × VD where
CS2 is the sum of the stray capacitance and the parasitic capacitance including the drain output capacitance of the transistors Q21 and Q22 and the capacitance of the wiring and the like.

Here, the circuit elements directly connected to the sensor 4 are transistors Q11, Q12 and Q21, Q22.
Therefore, since CS1 and CS2 such as stray capacitances are small and the symmetry of both fixed electrodes P1 and P2 is good, the difference between the average currents of the drive circuits 1 and 2 is substantially expressed by the following equation. You.

I1−I2 = f (C1−C2) × VD Therefore, the difference between the capacitances C1 and C2 can be detected by comparing the difference between the average currents of the current detection circuits 5 and 6.

Here, the amount of displacement of the movable electrode P3 is x,
When the distance between the electrodes at the center position is D, the capacitance C
1 and C2 are represented by the following equations, respectively.

C1 = εS / (D−x) C2 = εS / (D + x) Here, ε indicates the permittivity between the sensor electrodes, and S indicates the facing area of the sensor electrodes.

Therefore, the difference between the capacitances C1 and C2 is expressed by the following equation.

C1-C2 = {εS / (Dx)} −｝ ε
S / (D + x)｝ = (I1-I2) / fVD = ΔI / fVD where −D <x <D, ΔI = I1-I2.

Thus, the displacement x is given by the following equation, and the displacement of the movable electrode P3 can be detected.

[0052]

Next, the operation of the current detection circuits 5 and 6 and the current comparison circuit 7 will be described.

[0054] drive current equal current of the power supply terminals VD1 dynamic circuit 1 is output from the current detection circuit 5 is a current mirror circuit, at the same time, current equal current of the power supply terminal VD2 of the drive circuit 2 from the current detection circuit 6 Output to the current comparison circuit 7. Therefore, the difference current between the drive circuits 1 and 2 flows through the load resistor R.

Therefore, a voltage corresponding to the difference current is generated between the output terminal O and the bias power supply B. By measuring this voltage, the difference current can be known.

The embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and various modifications can be made.

For example, it is apparent that the capacitance can be measured not only by the displacement sensor, but also by the capacitance itself.

For example, an unknown capacitor whose one end is grounded may be connected to the output terminal of one drive circuit, and the output terminal of the other drive circuit may be left open. In this case, the capacitance Cx
Is represented by the following equation.

Cx = ΔI / fVD

As described above, the capacitance measuring circuit of the present invention has an effect that it operates stably even if the sensor is downsized.

Further, since the detection is obtained as a difference between the DC current values, there is an effect that the signal processing is easy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a capacitance measuring circuit of the present invention.

FIG. 2 is an explanatory diagram showing operation waveforms in the capacitance measuring circuit according to the embodiment.

FIG. 3 is a block diagram showing an example of a conventional capacitance measuring circuit.

[Explanation of symbols]

 1, 2 drive circuit 3 pulse generator 4 sensor 5, 6 current detection circuit 7 current comparison circuit 8, 9 oscillator 10 frequency comparison circuit C11, C21 capacitor D11, D21 delay circuit E11, E12, E21, E22 inverter G11, G21 NOR Gate G12, G22 NANDR gate Q11, Q12, Q21, Q22 Transistor

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 27/26 G01B 7/06 G01D 5/24

Claims (2)

(57) [Claims] 1. A measuring pulse having a predetermined period is generated, a charging current is supplied to a first and a second capacitance to be measured at one level of the measuring pulse, and the other of the measuring pulse is supplied. First and second measurement pulse supply circuits for discharging the charge of the first and second capacitances to be measured at the level of the first and second measurement pulse supply circuits, respectively. current comparison to the load current detection and the first and second current detecting circuit for detecting respectively, a difference of the first and second load current
Circuit , wherein the first and second current detection circuits are connected to respective input terminals.
Receiving the first and second load currents, respectively
First and second current mirror circuits, wherein the current comparison circuit includes the first and second current mirror circuits.
Each output terminal of the color circuit to the input terminal and the output terminal respectively.
A third current mirror circuit connected to the third current mirror circuit, wherein the capacitance value difference between the first and second measured capacitances is determined by the third current mirror circuit .
A capacitance measuring circuit that detects the current value at the output terminal of the current mirror circuit. 2. The method according to claim 1, wherein each of the first and second measurement pulse supply circuits delays the measurement pulse and outputs a delay pulse, and performs a NOR operation on the measurement pulse and the delay pulse. A NOR gate that takes a logical AND of the measurement pulse and the delay pulse; a first inverter that inverts the output of the NOR gate; a second inverter that inverts the output of the NAND gate; Input the output of one inverter to the gate and source
A P-channel MOS transistor receiving power supply via the current detection circuit; and an N-channel having an output of the second inverter input to a gate, a source grounded, and a drain connected commonly to a drain of the P-channel MOS transistor. 2. The capacitance measurement circuit according to claim 1, further comprising a MOS transistor, wherein the measurement pulse is supplied from the drain commonly connected to the capacitance to be measured.