JP2958724B2 - Clock loss detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock disconnection detection circuit.

[0002]

2. Description of the Related Art In a circuit using a clock, it is often necessary to perform processing on the inside or outside of the circuit depending on whether or not the clock is cut off. For example, in a transmission circuit, since a clock loss is an abnormal state, it is necessary to control such that an unnecessary signal is not output at the time of the clock loss, or to control the output terminal to high impedance.
For this reason, a circuit for detecting a clock loss is required, and the conventional clock loss detection circuit is constituted by a time constant circuit using a resistor and a capacitor.

[0003] That is, the conventional clock disconnection detection circuit is
As illustrated in FIG. 4, a clock input (CLK) is supplied to a time constant circuit including a resistor 8 and a capacitor 5 through inverters 1 and 7, and an output thereof is connected to a first input terminal (IN1) of a comparator 6. It is configured. A reference voltage (V _B2 ) is connected to a second input terminal (REF) of the comparator 6, and a signal indicating the presence or absence of a clock is obtained at an output (OUT) of the comparator 6.

As shown in FIG. 5, a clock input (CL
When a clock pulse appears at K), the clock pulse is integrated by the time constant circuit of the resistor 8 and the capacitor 5, and the voltage of the first input terminal (IN1) of the comparator 6 is changed to the second input terminal (REF) of the comparator 6. _Becomes higher than the reference voltage (V _B2 ) that is input to the input terminal, and the output (OUT) pulse rises and is held.
Thereafter, when the clock is no longer input, the voltage of the first input terminal (IN1) of the comparator 6 gradually decreases, and the reference voltage (V _B2 ) input to the second input terminal (REF) of the comparator 6 is reduced. ), The pulse of the output (OUT) falls, and the break of the lock is detected.

In the operation of such a conventional circuit, FIG.
As shown in ( ₂ ), when the frequency of the clock input decreases, the discharge time during integration of the time constant circuit increases, so that the voltage of the first input terminal (IN1) of the comparator 6 becomes higher than the reference voltage ( _VB2 ). Is low, and the output (OU) from the comparator 6 is maintained even while the clock is continuously input.
During T), a pulse falling indicating a clock disconnection occurs.

[0006]

As described above, in the conventional clock disconnection detecting circuit, since the time constant of the resistor 8 and the capacitor 5 is constant, when the frequency of the input clock changes, erroneous detection of the clock disconnection occurs, which is prevented. Requires that the constant value of the resistor or capacitor be changed according to the clock frequency, and the circuit is not versatile. In particular, when the clock frequency decreases, it is necessary to increase the value of the resistance or the capacitance, and there is a disadvantage that the layout area increases.

[0007]

A clock disconnection detection circuit according to the present invention selects an inverter to which a clock input is connected and one of a first reference voltage and a ground voltage in accordance with the on / off state of the clock input pulse. A switch circuit to be sent, a source connected to a power supply, a P-channel MOS transistor having a gate connected to the output of the inverter, a drain connected to a drain of the P-channel MOS transistor, and a gate connected to the output of the switch circuit. An N-channel MOS transistor having a source connected to the ground voltage; a capacitor connected between the drain of the P-channel MOS transistor and the ground voltage; a first input terminal connected to the drain of the P-channel MOS transistor; Is connected to the second reference voltage,
A comparator that outputs a pulse indicating the level of the voltage at both the first and second input terminals.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the present invention.
In the figure, a clock input (CLK) is connected to an inverter 1
And a first input terminal (SW) of the switch circuit 2 and a second input terminal (IN2) of the switch circuit 2.
A reference voltage (V _B1 ), and a third input terminal (IN
The ground voltage is connected to 3). The power supply (VDD) is connected to the source of the P-channel MOS transistor 3, the output of the inverter 1 is connected to the gate, and the P-channel MOS transistor 4 is connected to the drain of the N-channel MOS transistor 4.
The drain of the S transistor 3, the output (Q) of the switch circuit 2 is connected to the gate, and the ground voltage is connected to the source. The capacitor 5 is connected between the drain of the P-channel MOS transistor 3 and the ground, and connects the drain of the P-channel MOS transistor 3 to the first input terminal (IN1) of the comparator 6 and the reference to the second input terminal (REF). A voltage (V _B2 ) is connected, and a pulse indicating a clock detection result is obtained at its output (OUT).

In this embodiment, as shown in FIG. 2, when a clock pulse appears at the clock input (CLK), the output pulse of the inverter 1 falls during the rising period of the clock pulse, and the P-channel MOS transistor 3 is turned on. Become. At the same time, the switch circuit 2 outputs the ground voltage input to the third input terminal (IN3), and accordingly, the N-channel MOS transistor 4 is turned off. That is, during the rising period of the clock pulse, the P-channel MOS transistor 3 is turned on and the N-channel MOS transistor is turned on.
Since the transistor 4 is turned off, the capacitor 5 is charged with electric charge. As a result, the voltage at the first input terminal (IN1) of the comparator 6 increases, and when the voltage becomes higher than the reference voltage (V _B2 ), the output is output. The (OUT) pulse rises. afterwards,
During the falling period of the clock pulse, the output pulse of inverter 1 rises, and P-channel MOS transistor 3 is turned off. At the same time, the switch circuit 2 outputs the reference voltage (V _B1 ) input to the second input terminal (IN2). If the reference voltage (V _B1 ) is set to the gate-source voltage at which the N-channel MOS transistor 4 is turned on, the discharge occurs through the on-resistance of the N-channel MOS transistor 4. If the discharging time constant is set to be larger than the charging time constant, the voltage of the first input terminal (IN1) of the comparator 6 is always higher than the reference voltage (V _B2 ) during the period when the clock is continuously input. And the output of the comparator 6 (O
UT) holds the pulse rise. Thereafter, when the clock is no longer input, the first input terminal (IN
When the voltage of 1) decreases and becomes lower than the reference voltage (V _B2 ), the pulse of the output (OUT) falls and the clock interruption is detected.

In this embodiment, when the frequency of the clock to be detected is changed, the on-resistance (R _ON ) of the N-channel MOS transistor is given by the following equation (1) by changing the reference voltage (V _B1 ). .

[0012] _{R ON = L / μC O W} (V SG -V T) ......... (1) where μ is the mobility, C _O is the capacitance per unit area, W is the gate width, L is the gate The length, V _GS is the voltage between the gate and the source, and _VT is the threshold voltage.

[0013] In (1), mu, C _O, V _T is the constant determined in the process of integrated circuits, W, since L is determined by the shape of the gate of the transistor, the R _ON by V _GS Can be variable.

When the clock frequency is reduced as shown in FIG. 3, the discharge time constant can be changed by adjusting the reference voltage (V _B1 ) as described above, and the waveform can be changed from a broken line waveform to a solid line waveform. Detection can be prevented.

[0015]

As described above, according to the present invention, the discharge time constant of the time constant circuit is adjusted by changing the gate voltage of the N-channel MOS transistor according to the frequency of the input clock and adjusting the on-resistance thereof. It can be varied, the versatility of the circuit can be obtained, and the layout area can be reduced because the on-resistance of the transistor is used instead of the resistor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a signal timing chart in the embodiment of the present invention.

FIG. 3 is a signal timing chart in the embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional clock loss detection circuit.

FIG. 5 is a signal timing chart in a conventional circuit.

FIG. 6 is a signal timing chart in a conventional circuit.

[Explanation of symbols]

 1,7 Inverter 2 Switch circuit 3 P-channel MOS transistor 4 N-channel MOS transistor 5 Capacitor 6 Comparator 8 Resistance

Claims (1)

(57) [Claims] An inverter connected to a clock input;
A switch circuit for selectively transmitting one of a first reference voltage and a ground voltage in accordance with the on / off of the clock input pulse; a P-channel MOS transistor having a source connected to a power supply and a gate connected to the output of the inverter When,
An N-channel MOS transistor having a drain connected to the drain of the P-channel MOS transistor, a gate connected to the output of the switch circuit, and a source connected to the ground voltage, between the drain of the P-channel MOS transistor and the ground voltage; The connected capacitor and the first
Is connected to the drain of the P-channel MOS transistor, the second input terminal is connected to a second reference voltage, and outputs a pulse indicating the level of both voltages of the first and second input terminals. A clock disconnection detection circuit comprising a comparator.