JPH0439894B2 - - Google Patents

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Publication number
JPH0439894B2
JPH0439894B2 JP2479186A JP2479186A JPH0439894B2 JP H0439894 B2 JPH0439894 B2 JP H0439894B2 JP 2479186 A JP2479186 A JP 2479186A JP 2479186 A JP2479186 A JP 2479186A JP H0439894 B2 JPH0439894 B2 JP H0439894B2
Authority
JP
Japan
Prior art keywords
output
electrode
signal
capacitance
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2479186A
Other languages
Japanese (ja)
Other versions
JPS62182619A (en
Inventor
Tadashi Azegami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP2479186A priority Critical patent/JPS62182619A/en
Publication of JPS62182619A publication Critical patent/JPS62182619A/en
Publication of JPH0439894B2 publication Critical patent/JPH0439894B2/ja
Granted legal-status Critical Current

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  • Measuring Fluid Pressure (AREA)
  • Transmission And Conversion Of Sensor Element Output (AREA)

Description

【発明の詳細な説明】 <産業上の利用分野> 本発明は、差圧を静電容量して電気信号に変換
する差圧変換装置に係り、特に温度および静圧の
影響を補正した差圧変換装置に関する。
[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a differential pressure conversion device that converts differential pressure into an electrical signal by capacitance, and particularly relates to a differential pressure converter that converts differential pressure into an electrical signal by capacitance, and particularly relates to a differential pressure converter that converts differential pressure into an electric signal by capacitance, and in particular, converts differential pressure by capacitance into an electrical signal. This invention relates to a conversion device.

<従来の技術> 第4図は差圧変換装置の従来の温度、静圧の変
動によるゼロ点変動、スパン変動補償の概念を説
明するための構成図である。1は一室構造の差圧
変換装置の本体断面を示し、両断面に測定すべき
圧力PH,PLを受けるダイヤフラム2,3がその
周縁をこの本体に溶接されて配置されており、本
体に形成された貫通孔4とこれらダイヤフラムで
囲まれた中空室内にはシリコン油等の封液5が満
たされている。中空室中央部には拡大された電極
室が形成され、この電極室内には本体に嵌合した
絶縁体6に片側が支持された移動電極7及びこれ
に対向して静電容量C1,C2を形成するための固
定電極8,9が配置されている。10は中空室を
介して両ダイヤフラム2,3の中空部を連結する
ロツドで、その中央部は電極室内において移動電
極7に固定されており、差圧に応動したダイヤフ
ラムの変位を移動電極に伝え、静電容量C1,C2
を差動的に変化させる。静電容量C1,C2は演算
回路11に導かれて(C2−C1)/(C2+C1)の
演算が施され、直流出力信号eOに変換される。こ
の信号eOは出力回路12に導かれて、遠隔点の負
荷RL、電源EBの直列回路に対し、4〜20mAスパ
ンの出力電流IOに変換される。13は本体1ある
いは封液5の温度Tを測定する温度センサ、14
は封液5の圧力即ち静圧PSを測定する圧力センサ
であり、これらセンサの出力は、補償電圧発生回
路15,16に導かれ、ゼロ点補償用の温度信号
eT、ゼロ点補償用の静圧信号eP変換され、加算点
17,18の演算回路11の出力信号eOに加算又
は減算されて温度変動又は静圧変動に対するゼロ
点の変動が補償される。温度又は静圧変動に対し
てダイヤフラム2,3のバネ定数変化等により生
ずるスパン変動が問題になる場合は、補償電圧発
生回路15,16より点線で示すスパン変動補償
用の温度信号、静圧信号eT′,eP′を発生させ、出
力回路12の電圧−電流変換利得を変化させてス
パンの変動を補償する。
<Prior Art> FIG. 4 is a configuration diagram for explaining the concept of compensating for zero point fluctuations and span fluctuations due to fluctuations in temperature and static pressure in a conventional differential pressure converter. 1 shows a cross section of the main body of a differential pressure converter having a one-chamber structure, and diaphragms 2 and 3 that receive the pressures P H and P L to be measured are placed on both cross sections, with their peripheral edges welded to this main body. A sealing liquid 5 such as silicone oil is filled in a hollow chamber surrounded by the through hole 4 formed in the diaphragm and the diaphragm. An expanded electrode chamber is formed in the center of the hollow chamber, and within this electrode chamber there is a movable electrode 7 supported on one side by an insulator 6 fitted to the main body, and a capacitance C 1 , C opposite to the movable electrode 7 . Fixed electrodes 8 and 9 for forming 2 are arranged. Reference numeral 10 denotes a rod that connects the hollow parts of both diaphragms 2 and 3 via a hollow chamber, and its central part is fixed to the movable electrode 7 in the electrode chamber, and transmits the displacement of the diaphragm in response to the differential pressure to the movable electrode. , capacitance C 1 , C 2
Differentially change. The capacitances C 1 and C 2 are led to the arithmetic circuit 11, where they are subjected to the calculation (C 2 −C 1 )/(C 2 +C 1 ) and converted into a DC output signal e O. This signal e O is led to the output circuit 12 and converted into an output current I O with a span of 4 to 20 mA for the series circuit of the remote load R L and the power supply E B. 13 is a temperature sensor for measuring the temperature T of the main body 1 or the sealing liquid 5; 14;
are pressure sensors that measure the pressure of the sealing liquid 5, that is, the static pressure P S , and the outputs of these sensors are led to compensation voltage generation circuits 15 and 16 to generate a temperature signal for zero point compensation.
e T is converted into a static pressure signal e P for zero point compensation, and added to or subtracted from the output signal e O of the arithmetic circuit 11 at summing points 17 and 18 to compensate for zero point fluctuations due to temperature fluctuations or static pressure fluctuations. Ru. If span fluctuations caused by changes in the spring constants of the diaphragms 2 and 3 due to temperature or static pressure fluctuations become a problem, the compensation voltage generation circuits 15 and 16 generate temperature signals and static pressure signals for span fluctuation compensation shown by dotted lines. e T ′ and e P ′ are generated, and the voltage-to-current conversion gain of the output circuit 12 is changed to compensate for span fluctuations.

<発明が解決しようとする問題点> しかしながら、この様な従来の容量式変換装置
は差動容量センサのほかに静圧を補償するための
圧力センサを必要とし小形化の障害となる上にロ
ーコストをめざすアナログ形の容量変換器を実現
する上での障害ともなる。
<Problems to be Solved by the Invention> However, such conventional capacitive conversion devices require a pressure sensor to compensate for static pressure in addition to the differential capacitance sensor, which is an obstacle to miniaturization and is low cost. This also poses an obstacle to the realization of an analog capacitive converter.

<問題点を解決するための手段> この発明は、以上の点を考慮してアナログ形で
差圧に対する静圧補償のできるようにするため、
移動電極に対して第1電極と第2電極が対向して
設けられこれ等の間に封液が満されて検出すべき
差圧に応じて差動的に変化する第1および第2静
電容量を形成する差動容量センサと、封液の温度
を検出する温度センサと、固定容量が入力端と出
力端との間に負帰還接続されかつ移動電極が入力
端に接続された増幅手段と、この増幅手段の出力
電圧を所定の閾値で検出して出力レベルを変える
検出ゲート手段と、付勢端の一端が所定の電圧で
付勢されこの検出ゲート手段の出力変化を第1も
しくは第2電極へ選択的に印加する第1もしくは
第2選択ゲート手段と、検出ゲート手段の出力レ
ベルの反転信号を増幅手段の入力端へ帰還する抵
抗手段と、検出ゲート手段の出力の変化周期を計
数しその計数値の所定値ごとに出力レベルを反転
しこの出力レベルに基づいて第1もしくは第2選
択ゲート手段を選択するカウント手段と、この第
1もしくは第2選択出手段の付勢端の他端にカウ
ント手段の出力レベルに対応した出力電圧を印加
する操作手段と、変化周期信号と温度センサの温
度信号が入力され静圧信号を演算する静圧演算手
段と、操作手段の出力に対して静圧信号と温度信
号により補正演算して差圧信号を出力する補正演
算手段とを具備する構成としたものである。
<Means for Solving the Problems> In consideration of the above points, the present invention has the following features in order to enable static pressure compensation for differential pressure in an analog form.
A first electrode and a second electrode are provided to face the moving electrode, and a sealing liquid is filled between these electrodes, and the first and second electrostatic charges change differentially in accordance with the differential pressure to be detected. A differential capacitance sensor that forms a capacitance, a temperature sensor that detects the temperature of a sealing liquid, and an amplification means in which a fixed capacitor is connected in negative feedback between an input end and an output end, and a moving electrode is connected to the input end. , a detection gate means that detects the output voltage of the amplification means at a predetermined threshold value and changes the output level; a first or second selection gate means for selectively applying the signal to the electrode; a resistance means for feeding back an inverted signal of the output level of the detection gate means to the input end of the amplification means; and counting the period of change in the output of the detection gate means. a counting means that inverts the output level every predetermined value of the count value and selects the first or second selection gate means based on the output level; and the other end of the biasing end of the first or second selection output means. an operating means for applying an output voltage corresponding to the output level of the counting means; a static pressure calculating means for calculating a static pressure signal to which the change period signal and the temperature signal of the temperature sensor are input; The configuration includes a correction calculation means for performing correction calculations based on the pressure signal and the temperature signal and outputting a differential pressure signal.

<実施例> 以下、本発明の実施例について図面に基づき説
明する。第1図は本発明の一実施例を示すブロツ
ク図である。尚、第4図に示す従来の容量式変換
装置と同一の機能を有する部分には同一の符号を
付し適宜に説明を省略する。
<Example> Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. Note that parts having the same functions as those of the conventional capacitive converter shown in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

差動容量センサ19は、移動電極7に対向して
固定電極8,9が配置され静電容量C1,C2がそ
れぞれ形成され、更に温度センサ13が組込まれ
ている。
The differential capacitance sensor 19 has fixed electrodes 8 and 9 arranged opposite to the movable electrode 7 to form capacitances C 1 and C 2 respectively, and further includes a temperature sensor 13 incorporated therein.

20,21は選択ゲート回路でありCMOSト
ランジスタQ1,Q2,Q3,Q4およびナンドゲート
G1,G2でそれぞれ構成されている。固定電極8,
9は選択ゲート回路20,21の出力端にそれぞ
れ接続されている。選択ゲート回路20の付勢端
の一端には電源電圧+Eが、他端には操作電圧V
がそれぞれ印加され、選択ゲート回路21の付勢
端の一端には電源電圧−Eが、他端には操作電圧
Vがそれぞれ印加されている。CMOSトランジ
スタQ1,Q2のゲートはナンバーゲートG1の出力
端と、CMOSトランジスタQ3,Q4のゲートはナ
ンドゲートG2の出力端とそれぞれ接続されてい
る。
20 and 21 are selection gate circuits, which include CMOS transistors Q 1 , Q 2 , Q 3 , Q 4 and NAND gates.
Each consists of G 1 and G 2 . fixed electrode 8,
9 is connected to the output terminals of the selection gate circuits 20 and 21, respectively. The power supply voltage +E is applied to one end of the biasing end of the selection gate circuit 20, and the operating voltage V is applied to the other end.
are applied, respectively, and the power supply voltage -E is applied to one end of the biasing end of the selection gate circuit 21, and the operating voltage V is applied to the other end. The gates of CMOS transistors Q 1 and Q 2 are connected to the output terminal of number gate G 1 , and the gates of CMOS transistors Q 3 and Q 4 are connected to the output terminal of NAND gate G 2 .

増幅回路22固定容量Ckと差動増幅器Q5で構
成され、差動増幅器Q5の反転入力端(−)は移
動電極7に接続され、非反転入力端(+)は共通
電位点COMにそれぞれ接続されている。差動増
幅器Q5の反転入力端(−)出力端との間には固
定容量Ckが接続されている。
The amplifier circuit 22 is composed of a fixed capacitor C k and a differential amplifier Q5 , and the inverting input terminal (-) of the differential amplifier Q5 is connected to the moving electrode 7, and the non-inverting input terminal (+) is connected to the common potential point COM. each connected. A fixed capacitor C k is connected between the inverting input terminal (−) output terminal and the differential amplifier Q 5 .

Q6は検出ゲート手段としての比較器であり、
その非反転入力端(+)は共通電位点のCOMに、
反転入力端(−)差動増幅器Q5の出力端にそれ
ぞれ接続されている。
Q 6 is a comparator as a detection gate means,
Its non-inverting input terminal (+) is connected to the common potential point COM,
The inverting input terminal (-) is connected to the output terminal of the differential amplifier Q5 , respectively.

G3はインバータでありその入力端は比較器Q6
の出力端へその出力端は抵抗Rを介して差動増幅
器Q5の反転入力端(−)に接続されると共にn
ビツトのカウンタQ7に接続されている。
G 3 is an inverter whose input terminal is a comparator Q 6
Its output terminal is connected to the inverting input terminal (-) of the differential amplifier Q5 via a resistor R, and the output terminal of n
Connected to bit counter Q7 .

インバータG1の入力端には比較器Q6の出力端
とカウンタQ7の出力端がそれぞれ接続され、イ
ンバータG2の入力端には比較器Q6の出力端とイ
ンバータG4を介してカウンタQ7の出力端がそれ
ぞれ接続されている。
The output terminal of comparator Q 6 and the output terminal of counter Q 7 are connected to the input terminal of inverter G 1 , respectively, and the output terminal of comparator Q 6 and the output terminal of counter Q 7 are connected to the input terminal of inverter G 2 via inverter G 4 . The output ends of Q 7 are connected respectively.

インバータG4の出力端は操作手段としての積
分器23の入力端と接続され、その出力端に操作
電圧Vを得る。
The output end of the inverter G4 is connected to the input end of an integrator 23 as an operating means, and an operating voltage V is obtained at its output end.

一方、静圧演算回路24は温度センサ13から
の温度TとカウンタQ7の変化周期tH(=tL)が入
力され封液5印加される静圧が演算され静圧信号
Psとして出力される。
On the other hand, the static pressure calculation circuit 24 inputs the temperature T from the temperature sensor 13 and the change period t H (=t L ) of the counter Q 7 , calculates the static pressure applied to the sealing liquid 5, and generates a static pressure signal.
Output as P s .

補正演算回路25には差圧ΔPに対応する操作
電圧V、温度Tおよび静圧信号Psが入力され差圧
Δpに対して静圧補正を行ない出力端26補正さ
れた差圧Δpcを出力する。
The correction calculation circuit 25 receives the operating voltage V, temperature T, and static pressure signal Ps corresponding to the differential pressure ΔP, performs static pressure correction on the differential pressure Δp, and outputs the corrected differential pressure Δp c at the output end 26. do.

次に以上の如く構成された実施例の動作につい
て第2図に示す波形図を参照して説明する。
Next, the operation of the embodiment configured as described above will be explained with reference to the waveform diagram shown in FIG.

カウンタQ7の出力端Qoがハイレベル“H”(=
+E)<第2図ヘ>の状態では、選択ゲート回路
20側が選択され比較器Q6の出力端のレベル変
化(第2図ニ)に対応してナンドゲートG1が開
閉される。いま、比較器Q6の出力端がハイレベ
ル“H”の状態(第2図ニ)ではトランジスタ
Q1,Q2のゲートはローレベル“L”となり、ト
ランジスタQ1がオン、Q2がオフとなり固定電極
8には+Eの電圧が印加される(第2図イ)。こ
のため差動増幅器Q5の入力端は正に上昇しよう
とするが、固定容量Ckを介しての差動増幅器Q5
の帰還作用により差動増幅器Q5の出力端の電圧
は急速に所定値eHだけ低下する(第2図ハ)。こ
の電圧低下は比較器Q6で検出されその出力端の
電圧レベルを正に反転させる(第2図ニ)。この
レベル変化によりインバータG3(第2図ホ)の出
力が反転され、抵抗Rを介して静電容量C1の電
荷が放電されその電位が徐々に低下させられるの
で、差動増幅器Q5は固定容量Ckを介してその電
荷を中和させるように動作し第2図ハに示すよう
にその出力端の電位を上昇させる。共通電位
COMの電位を越えると比較器Q6の出力端の電位
は急速に負に反転する(第2図ニ)。この反転す
るまでの期間をtH、抵抗Rに流れる電流をいiと
すれば、静電容量C1での電荷変動を考慮して次
式が成立する。
The output terminal Q o of counter Q 7 is at high level “H” (=
+E) In the state shown in FIG. 2F, the selection gate circuit 20 side is selected and the NAND gate G1 is opened and closed in response to the level change at the output terminal of the comparator Q6 (FIG. 2D). Now, when the output terminal of comparator Q6 is at high level "H" (Fig. 2 D), the transistor
The gates of Q 1 and Q 2 become low level "L", transistor Q 1 is turned on and transistor Q 2 is turned off, and a voltage of +E is applied to the fixed electrode 8 (FIG. 2A). Therefore, the input terminal of the differential amplifier Q 5 tends to rise positively, but the input terminal of the differential amplifier Q 5 through the fixed capacitance C k
Due to the feedback action of , the voltage at the output end of the differential amplifier Q5 rapidly drops by a predetermined value eH (Fig. 2C). This voltage drop is detected by comparator Q6 and inverts the voltage level at its output to positive (FIG. 2D). This level change inverts the output of inverter G 3 (Fig. 2 E), discharges the charge of capacitance C 1 through resistor R, and gradually lowers its potential, so that differential amplifier Q 5 It operates to neutralize the charge through the fixed capacitor C k and raises the potential at its output terminal as shown in FIG. 2C. common potential
When the potential of COM is exceeded, the potential of the output terminal of comparator Q6 rapidly turns negative (Fig. 2 D). If the period until this inversion is t H and the current flowing through the resistor R is i, then the following equation holds true taking into account the charge fluctuation in the capacitance C 1 .

C1(E−V)=CkeH (1) tHi=CkeH (2) 比較器Q6の出力端のレベル反転はナンドゲー
トG1を介してトランジスタQ1をオフQ2をオンと
し固定電極8に操作電圧Vを印加する(第2図
イ)。このため固定電極8は(E−V)の急激な
電位低下を生じ、この電位低下を中和すべく差動
増幅器Q5は固定容量Ckを介して所定値eHだけ電
圧を急激に上昇させ(第2図ハ)る。一方、差動
増幅器Q5の出力端の電位上昇は比較器Q6、イン
バータG3、抵抗Rを介して静電容量C1を充電し
その電位を上昇させようとするので、差動増幅器
Q5はその出力端の電位を徐々に低下させ(第2
図ハ)静電容量C1の電荷を中和させる。共通電
位点COMの電位を越えると比較器Q6の出力端の
電位は急速に正に反転し、最初の状態に戻る。こ
の反転するまでの期間tH′は期間tHに等しく(1)(2)
式が成立する。以後、これを繰り返す。
C 1 (E-V) = C k e H (1) t H i = C k e H (2) The level inversion at the output terminal of comparator Q 6 turns off transistor Q 1 via NAND gate G 1 Q 2 is turned on and an operating voltage V is applied to the fixed electrode 8 (FIG. 2A). For this reason, the fixed electrode 8 causes a sudden potential drop of (E-V), and in order to neutralize this potential drop, the differential amplifier Q 5 rapidly increases the voltage by a predetermined value e H via the fixed capacitor C k . (Figure 2 C). On the other hand, the potential increase at the output terminal of the differential amplifier Q5 attempts to charge the capacitance C1 via the comparator Q6 , inverter G3 , and resistor R and increase its potential.
Q5 gradually lowers the potential at its output terminal (second
Figure c) Neutralize the charge on capacitance C1 . When the potential at the common potential point COM is exceeded, the potential at the output end of the comparator Q6 rapidly reverses to positive and returns to the initial state. The period t H ′ until this reversal is equal to the period t H (1)(2)
The formula holds true. Repeat this from now on.

これ等を所定の回数繰り返すとカウンタQ7
出力端Qoのレベルが反転し(第2図ヘ)、今度は
選択ゲート回路21側が選択され(第2図ト)、
選択ゲート回路20側と同様の動作をする。この
場合には所定値eHに対してeL、期間tHに対してtL
とすると、次式が成立する。
When these steps are repeated a predetermined number of times, the level of the output terminal Qo of the counter Q7 is inverted (FIG. 2), and this time the selection gate circuit 21 side is selected (FIG. 2, G).
It operates in the same way as the selection gate circuit 20 side. In this case, e L for a given value e H and t L for a period t H
Then, the following formula holds true.

C2(V−(−E))=CkeL (3) tLi=CkeL (4) 次にカウンタQ7の出力端がハイレベル“H”
である期間をTH、ローレベル“L”である期間
をTLとすれば、第2に示すように例えばTH>TL
のときはインバータG4の平均出力電圧は(TH
(−E)+TLE/(TH+TL)で与えられ負電圧と
なる。この負電圧は積分器23の出力すなわち操
作電圧Vを上昇させる。操作電圧Vの上昇は固定
電極8,9の電圧(第2図イ,ロ)の振幅を減
少、増大させる。この結果、期間tH,tLが減少、
増大し、最終的にtH=tL、即ちTH=TLで平衡す
る。この場合には、(1)〜(4)式から次式が成立す
る。
C 2 (V-(-E)) = C k e L (3) t L i = C k e L (4) Next, the output terminal of counter Q 7 is at high level “H”
If the period during which the level is low is T H and the period during which the low level is “L” is T L , then as shown in the second figure, for example, T H > T L
When , the average output voltage of inverter G4 is (T H
It is given by (-E)+T L E/( TH + T L ) and becomes a negative voltage. This negative voltage increases the output of the integrator 23, that is, the operating voltage V. As the operating voltage V increases, the amplitude of the voltages (A and B in FIG. 2) of the fixed electrodes 8 and 9 decreases and increases. As a result, the periods t H and t L decrease,
increases, and finally reaches equilibrium at t H =t L , that is, T H =T L . In this case, the following equation holds true from equations (1) to (4).

V=E・C1−C2/C1+C2 (5) また、tH,tL,(1)〜(4)式から tH=tL=2E/i・C1C2/C1+C2 (6) を得る。 V=E・C 1 −C 2 /C 1 +C 2 (5) Also, from t H , t L , and equations (1) to (4), t H = t L = 2E/i・C 1 C 2 /C We get 1 +C 2 (6).

操作電圧Vは電源電圧Eに依存し、期間tH(=
tL)は電源電圧Eと電流iに依存するが電流iは
i=±E/Rで与えられることから結局電源電圧
Eを安定化すれば、操作電圧あるいは期間TH
静電容量C1,C2の和分の差あるいは和分の積に
比例した値として得られる。
The operating voltage V depends on the power supply voltage E, and the period t H (=
t L ) depends on the power supply voltage E and current i, but since the current i is given by i = ±E/R, if the power supply voltage E is stabilized, the operating voltage or period T H will be the capacitance C 1 , C 2 is obtained as a value proportional to the difference in the sums or the product of the sums.

なお、移動電極7と共通電位点COMとの間に
形成される分布容量Csはこの部分の電位が差動増
幅器Q5により常に共通電位点COM電位保持され
るので、分布容量Csの影響を受け難いものとな
る。
Note that the distributed capacitance C s formed between the moving electrode 7 and the common potential point COM is affected by the influence of the distributed capacitance C s because the potential of this part is always held at the common potential point COM potential by the differential amplifier Q 5 . It becomes difficult to accept.

次に静電容量C1,C2と補正前の差圧Δpなどと
の関係について説明する。差圧ΔPがゼロのとき
の各静電容量C1,C2の値をC0、移動電極7のバ
ネ定数をKとすれば、静電容量C1,C2は、 C1=C01/1−KΔP (7) C2=C01/1+KΔP (8) として現わせる。これ等の式から、差圧ΔPは ΔP=1/K(C1−C2/C1+C2)(9) となる。従つて、(5)式を用いて V=KE・ΔP (10) を得る。また、静電容量C0は封液5の誘電率を
ε、真空での静電容量をCvとすればC0=εCvであ
るから(7),(8)式を用いて ε=2/Cv(C1C2/C1C2) (11) となる。この式に(6)式を代入して tH=tL=E/iCv・ε (12) を得る。
Next, the relationship between the capacitances C 1 and C 2 and the differential pressure Δp before correction will be explained. If the value of each capacitance C 1 and C 2 when the differential pressure ΔP is zero is C 0 and the spring constant of the moving electrode 7 is K, then the capacitance C 1 and C 2 are as follows: C 1 =C 0 Express it as 1/1−KΔP (7) C 2 =C 0 1/1+KΔP (8). From these equations, the differential pressure ΔP becomes ΔP=1/K(C 1 −C 2 /C 1 +C 2 )(9). Therefore, using equation (5), we obtain V=KE・ΔP (10). Furthermore, if the dielectric constant of the sealing liquid 5 is ε and the capacitance in vacuum is C v , the capacitance C 0 is C 0 = εC v , so using equations (7) and (8), ε= 2/C v (C 1 C 2 /C 1 C 2 ) (11). Substituting equation (6) into this equation, we obtain t H = t L = E/iC v ·ε (12).

ところで、温度Tが上昇すると誘電率εは減少
し、静圧PSが増大すると誘電率εは増加するの
で、基準温度での誘電率ε0,a,bを定数とする
と、誘電率εは次式で示される。
By the way, as the temperature T increases, the dielectric constant ε decreases, and as the static pressure P S increases, the dielectric constant ε increases, so if the dielectric constant ε 0 at the reference temperature, a, and b are constants, the dielectric constant ε is It is shown by the following formula.

ε=ε0(1−aT+bTS) (13) これを変形して、静圧PSは PS=1/b・ε−ε0/ε0+a/bT(
14) となる。誘電率εの変化率をΔε、α=1/b、
β=−a/bとおくと(14)式は、 PS=α・Δε−βT (15) となる。α,βはそれぞれΔε、Tに対する補正
係数である。
ε=ε 0 (1−aT+bT S ) (13) Modifying this, the static pressure P S is P S =1/b・ε−ε 00 +a/bT(
14) becomes. Let the rate of change of the dielectric constant ε be Δε, α=1/b,
If β=−a/b, equation (14) becomes P S =α·Δε−βT (15). α and β are correction coefficients for Δε and T, respectively.

静圧演算回路24は温度センサ13からの温度
Tと誘電率εに関連した期間TH(=TL)信号とを
入力し、誘電率の変化率Δεを演算して(15)式
で示す演算の後、静圧PSを算出する。
The static pressure calculation circuit 24 inputs the temperature T from the temperature sensor 13 and the period T H (=T L ) signal related to the dielectric constant ε, calculates the rate of change in the dielectric constant Δε, and calculates the rate of change in the dielectric constant Δε, which is expressed by equation (15). After the calculation, static pressure P S is calculated.

一方、差圧ΔPは(9)式で示されるが、この(9)式
は理想的な場合、即ち固定電極8,9、移動電極
7相互間が平行でかつバネ定数Kも一定であるよ
うな場合について成立する式である。しかし、実
際には静圧PSあるいは温度Tが変化すると、本体
1が変形するなどして(9)式で得られた差圧ΔPが
変化する。そこで、差圧ΔPを補正する必要があ
る。
On the other hand, the differential pressure ΔP is expressed by equation (9), which is expressed in the ideal case, that is, when the fixed electrodes 8 and 9 and the movable electrode 7 are parallel to each other, and the spring constant K is also constant. This is an equation that holds true for the following cases. However, in reality, when the static pressure P S or the temperature T changes, the main body 1 deforms and the differential pressure ΔP obtained by equation (9) changes. Therefore, it is necessary to correct the differential pressure ΔP.

この補正は、演正演算回路25で実行する。補
正演算回路25は差圧ΔPに比例した操作電圧V
が入力されるが、これに対して静圧演算回路24
からの静圧PS、温度センサ13からの温度Tによ
り下式に示す演算を施し、補正後の差圧ΔPCを出
力端26に出力する。
This correction is executed by the correction calculation circuit 25. The correction calculation circuit 25 generates an operating voltage V proportional to the differential pressure ΔP.
is input, but in response to this, the static pressure calculation circuit 24
The calculation shown in the following formula is performed using the static pressure P S from the temperature sensor 13 and the temperature T from the temperature sensor 13, and the corrected differential pressure ΔP C is outputted to the output terminal 26.

静圧PSに対する補正係数をk1、温度に対する補
正係数をk2とすると、補正された差圧ΔPCは次の
ようになる。
Assuming that the correction coefficient for static pressure P S is k 1 and the correction coefficient for temperature is k 2 , the corrected differential pressure ΔP C is as follows.

ΔPC=ΔP1+k1PS+k2T) (16) 第3図は本発明の他の実施例を示す部分ブロツ
ク図である。移動電極8と増幅回路22との接続
にケーブルを用いると共通電位COMとの間に分
布容量Csができるが、第1図に示す実施例では差
動増幅器Q5の反転入力端(−)の電位が共通電
位点COMの電位に保持されるのでガード効果が
ある。しかしこれは差動増幅器Q5のオープンル
ープゲインが充分高いときに成立するが、静電容
量C1あるいはC2を介して差動増幅器Q5へ伝達さ
れる信号に対して減衰効果を及ぼすことは避け得
ない。これに対して第3図に示すようにケーブル
のガードGDに差動増幅器Q5の出力端の電位を印
加すると、ガード容量は固定容量Ckと並列に形
成され、心線CDから共通電位点COMへの分布容
量Csの効果は除去される。このことは、(5)式の導
出において固定容量Ckが消去されていることか
らも判る。
ΔP C =ΔP1+k 1 P S +k 2 T) (16) FIG. 3 is a partial block diagram showing another embodiment of the present invention. When a cable is used to connect the movable electrode 8 and the amplifier circuit 22, a distributed capacitance Cs is created between the common potential COM and the inverting input terminal (-) of the differential amplifier Q5 in the embodiment shown in FIG. Since the potential of is held at the potential of the common potential point COM, there is a guard effect. However, although this is true when the open loop gain of the differential amplifier Q5 is sufficiently high, it has an attenuating effect on the signal transmitted to the differential amplifier Q5 via the capacitance C1 or C2 . cannot be avoided. On the other hand, when the potential of the output end of the differential amplifier Q5 is applied to the guard GD of the cable as shown in Fig. 3, the guard capacitance is formed in parallel with the fixed capacitance Ck , and the guard capacitance is formed in parallel with the fixed capacitance Ck. The effect of distributed capacitance C s on COM is removed. This can also be seen from the fact that the fixed capacitance C k is eliminated in the derivation of equation (5).

逆に、固定容量Ckをガード容量で代替し、部
品としての固定容量Ckを削除することもできる。
Conversely, it is also possible to replace the fixed capacitor C k with a guard capacitor and eliminate the fixed capacitor C k as a component.

<発明の効果> 以上、実施例とともに具体的に説明した様に本
発明によれば、カウンタの出力端に得られる変化
周期を用いて静圧信号を得ると共に積分器23出
力に得られる差圧信号を補正して静圧補正がなさ
れたアナログの差圧信号を得るようにしたので、
小形で静圧補償のされた精度の高い容量式変換装
置を実現することができる。
<Effects of the Invention> As described above in detail with the embodiments, according to the present invention, the static pressure signal is obtained using the change period obtained at the output end of the counter, and the differential pressure obtained at the output of the integrator 23 is Since the signal was corrected to obtain an analog differential pressure signal with static pressure correction,
A compact, static pressure compensated, highly accurate capacitive conversion device can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロツク図、
第2図は第1図に示す実施例の動作を説明する波
形図、第3図は本発明の他の実施例を示す部分ブ
ロツク図、第4図は従来の容量式変換装置の構成
を示すブロツク図である。 5……封液、7……移動電極、8,9……固定
電極、13……温度センサ、19……差動容量セ
ンサ、20,21……選択ゲート回路、22……
増幅回路、24……静圧演算回路、25……補正
演算回路、Ck……固定容量、C1,C2……静電容
量、V……操作電圧、PS……静圧。
FIG. 1 is a block diagram showing one embodiment of the present invention;
Fig. 2 is a waveform diagram explaining the operation of the embodiment shown in Fig. 1, Fig. 3 is a partial block diagram showing another embodiment of the present invention, and Fig. 4 shows the configuration of a conventional capacitive conversion device. It is a block diagram. 5... Sealing liquid, 7... Moving electrode, 8, 9... Fixed electrode, 13... Temperature sensor, 19... Differential capacitance sensor, 20, 21... Selection gate circuit, 22...
Amplifier circuit, 24...Static pressure calculation circuit, 25...Correction calculation circuit, C k ...Fixed capacitance, C1 , C2 ...Capacitance, V...Operating voltage, P S ...Static pressure.

Claims (1)

【特許請求の範囲】[Claims] 1 移動電極に対して第1電極と第2電極が対向
して設けられこれ等の間に封液が満されて検出す
べき差圧に応じて差動的に変化する第1および第
2静電容量を形成する差動容量センサと、前記封
液の温度を検出する温度センサと、固定容量が入
力端と出力端との間に負帰還接続されかつ前記移
動電極が前記入力端に接続された増幅手段と、こ
の増幅手段の出力電圧を所定の閾値で検出して出
力レベルを変える検出ゲート手段と、付勢端の一
端が所定の電圧で付勢されこの検出ゲート手段の
出力変化を前記第1もしくは第2電極へ選択的に
印加する第1もしくは第2選択ゲート手段と、前
記検出ゲート手段の出力レベルの反転信号を前記
増幅手段の前記入力端へ帰還する抵抗手段と、前
記検出ゲート手段の出力の変化周期を計数しその
計数値の所定値ごとに出力レベルを反転しこの出
力レベルに基づいて前記第1もしくは第2選択ゲ
ート手段を選択するカウント手段と、この第1も
しくは第2選択出手段の付勢端の他端に前記カウ
ント手段の出力レベルに対応した出力電圧を印加
する操作手段と、前記変化周期信号と前記温度セ
ンサの温度信号が入力され静圧信号を演算する静
圧演算手段と、前記操作手段の出力に対して前記
静圧信号と前記温度信号により補正演算して差圧
信号を出力する補正演算手段とを具備する容量式
変換装置。
1 A first electrode and a second electrode are provided facing the moving electrode, and a sealing liquid is filled between the first and second static electrodes, and the first and second static electrodes change differentially according to the differential pressure to be detected. A differential capacitance sensor forming a capacitance, a temperature sensor detecting the temperature of the sealing liquid, a fixed capacitor connected in negative feedback between an input end and an output end, and the movable electrode connected to the input end. amplification means, a detection gate means for detecting the output voltage of the amplification means at a predetermined threshold value and changing the output level; first or second selection gate means for selectively applying the signal to the first or second electrode; resistance means for feeding back an inverted signal of the output level of the detection gate means to the input end of the amplification means; and the detection gate. counting means for counting the change period of the output of the means, inverting the output level every predetermined value of the counted value, and selecting the first or second selection gate means based on the output level; operating means for applying an output voltage corresponding to the output level of the counting means to the other end of the biasing end of the selection output means; A capacitive conversion device comprising a pressure calculation means and a correction calculation means for performing a correction calculation on the output of the operation means using the static pressure signal and the temperature signal and outputting a differential pressure signal.
JP2479186A 1986-02-06 1986-02-06 Capacity type converter Granted JPS62182619A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2479186A JPS62182619A (en) 1986-02-06 1986-02-06 Capacity type converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2479186A JPS62182619A (en) 1986-02-06 1986-02-06 Capacity type converter

Publications (2)

Publication Number Publication Date
JPS62182619A JPS62182619A (en) 1987-08-11
JPH0439894B2 true JPH0439894B2 (en) 1992-07-01

Family

ID=12148007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2479186A Granted JPS62182619A (en) 1986-02-06 1986-02-06 Capacity type converter

Country Status (1)

Country Link
JP (1) JPS62182619A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8884301B2 (en) 1999-10-12 2014-11-11 Semiconductor Energy Laboratory Co., Ltd. EL display device and a method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8884301B2 (en) 1999-10-12 2014-11-11 Semiconductor Energy Laboratory Co., Ltd. EL display device and a method of manufacturing the same

Also Published As

Publication number Publication date
JPS62182619A (en) 1987-08-11

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