JPH0559603B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an offset cancel circuit, and more particularly to an offset cancel circuit such as an automatic line equalizer implemented in a MOS integrated circuit.

[Conventional technology]

Conventionally, this type of offset cancel circuit, as shown in the circuit diagram in FIG. A connected 2-input analog adder 3, a comparator circuit 4 that compares the output terminal of the 2-input analog adder 3 with a reference voltage _Vr3 , and an output of the comparator circuit 4 for a certain period of time, where one period of the clock pulse _φc is t seconds. Calculate the number of pulses sent within (2 ⁿ -1)・t seconds, and the number of pulses is (2 ⁿ -1)/2
A control signal generation circuit 5 that generates a control pulse φ _b or φ _a depending on whether the pulse is larger or smaller, and switches S _a , which are controlled by the control pulses φ _a and φ _b , respectively.
A charging/discharging circuit 6 that charges or discharges the integral capacitor C with a predetermined current by closing Φ _b , and a compensation signal line 7 that applies the voltage across the integral capacitor C to the other input terminal of the two-input analog adder 3. Contains. 8 and 9 are n bit up counters,
10 is a monostable multivibrator. The output signal of comparator circuit 4 enters one input terminal of AND circuit _A1 , and the other input terminal receives clock pulse φ _c
enters and performs a logical product. Also, the clock pulse φ _c is n
Up input terminal U ₂ of bit up counter 9
Also count the time it takes to enter.

Now, the maximum count value of n bit up counter 9
²ⁿ - ₁ is assumed to be K2, and the count value of the n bit up counter 8 at each time is assumed to be _K1 . The n-bit up counters 8 and 9 are respectively counted by the output pulse from the AND circuit _A1 and the clock pulse _φc , and when the n-bit up counter 9 reaches the maximum count value _K2 , the n-bit up counter 8 is counted.
If the count value K ₁ of is K ₁ > (K ₂ /2), then from the output Q ₁
"H" is output to one input terminal of AND circuit _A2 . At the same time, the output of n bit up counter 9
Q ₂ is differentiated by the monostable multivibrator 10 and input to the other input terminal of the AND circuit A ₂ , and a control pulse φ _b is generated. The control pulse φ _b closes the switch S _b to discharge the integrating capacitor C with a constant current, and applies the voltage of the integrating capacitor C to the two-input analog adder 3 via the amplifier circuit 11 with a gain of 1.

Conversely, the count value of n bit up counter 8 is K ₁
When K ₁ < (K ₂ /2), “L” is output from the output Q ₁ to the inverter I ₁ , and the inverted output “H” is output to one input terminal of the AND circuit A ₂ . . Simultaneously output from n bit up counter 9
Q ₂ is differentiated by the monostable multivibrator 10 and output to the other input terminal of the AND circuit A ₃ to generate a control pulse φ _a . The control pulse φ _a closes the switch S _a , charges the integrating capacitor C with a constant current, and applies the voltage to the two-input analog adder 3 . In this way, the DC component becomes the reference voltage V _r3
An output signal that is corrected is obtained.

This offset cancel circuit has an offset compensation error due to the use of a current mirror circuit in the charge/discharge circuit 6. When switch S _a is closed
The current I _Sa flowing through the pMOS transistor T _r2 and the current I _Sb flowing through the nMOS transistor T _r4 when the switch S _b is closed are not necessarily equal. it is
The potential V ₁ at the connection point between the drain of pMOS transistor T _r1 and the drain of nMOS transistor T _r3 ,
This is because the potential V ₂ at the connection point between the drain of the pMOS transistor T _r2 and the drain of the nMOS transistor T _r4 is not necessarily equal. Therefore, the amount of change in the voltage of the integral capacitor C during charging is |
Vc ⁺ |, when discharging to |Vc ^- |, |Vc ⁺ |≠|
Vc ^- becomes ｜. On the other hand, if the time during which the comparator output is "H" within a certain period of time is t _H and the time when it is "L" is t _L , then the equilibrium condition of this offset compensation circuit is t _H ·|
Vc ^- |=t _L・|Vc ⁺ |. Therefore |Vc ⁺ |≠
When |Vc ^- |, t _H ≠ t _L , and an offset compensation error occurs.

[Problem that the invention seeks to solve]

The conventional offset cancel circuit described above is
Since a current mirror circuit is used, there is a drawback that the offset compensation error becomes large as a result of the difference in magnitude between the positive direction compensation voltage and the negative direction compensation voltage. SUMMARY OF THE INVENTION An object of the present invention is to provide an offset cancel circuit which has a small offset compensation error and is suitable for integration into a MOS integrated circuit.

[Means for solving problems]

The offset cancel circuit of the present invention includes an amplification means for adding a compensation signal to a predetermined input signal and amplifying it, or for amplifying the input signal and adding the compensation signal, and an output signal of the amplification means to be set at a reference voltage. A clock is used to count the time when the output of the comparison circuit is at a high level or a time when it is at a low level. Depending on the situation, the first and second pulses are generated simultaneously and then the third and fourth pulses are generated, or the first and third pulses are generated simultaneously and then the second and fourth pulses are generated. a control signal generation circuit that simultaneously generates pulses of a first switch inserted between one terminal of the sampling capacitor and controlled by the fourth pulse; and a second switch inserted between one terminal of the sampling capacitor and the ground terminal and controlled by the first pulse. a third switch inserted between the other terminal of the sampling capacitor and the second reference voltage terminal and controlled by the third pulse, and between the other terminal of the sampling capacitor and the ground terminal. A fourth switch is inserted into the circuit and controlled by the second pulse, and performs an inverting integral operation or a non-inverting integral operation depending on whether the output of the comparator circuit is a specified count value within a certain period of time. and a switched capacitor integrator for outputting the compensation signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. This embodiment includes an amplifier circuit 2 that amplifies a predetermined input signal such as a communication signal, a 2-input analog adder 3 in which the output terminal of the amplifier circuit 2 is connected to one input terminal, and a 2-input analog adder 3. A comparison circuit 4 compares the signal at the output terminal with the first reference voltage V _r1 , and the output of the comparison circuit 4 is maintained for a certain period of time (2 ⁿ −
1) Count the number of pulses sent within t seconds, and generate the first and second pulses φ ₁ and φ ₂ simultaneously depending on whether the number of pulses is larger or smaller than (2 ⁿ -1)/2 After that, the third and fourth pulses φ ₃ and φ ₄ are generated simultaneously, or after the first and third pulses φ ₁ and φ ₃ are generated simultaneously, the second and fourth pulses φ ₂ and φ are generated. _Four
, a control signal generating circuit 5A that simultaneously generates , an operational amplifier 15, an integrating capacitor C ₁ , a sampling capacitor C _S , and a control signal generating circuit 5A that is inserted between the inverting input terminal of the operational amplifier 15 and one terminal of the sampling capacitor C _S . The fourth switch S ₄ is controlled by the first pulse φ ₄ of the sampling capacitor C s and the first switch S ₁ is inserted between one terminal of the sampling capacitor C _s and the ground terminal and controlled by the first pulse φ ₁ . - A third switch S ₃ inserted between the other terminal of the capacitor C _S and the second reference voltage terminal V _r2 and controlled by the third pulse φ ₃ , a sampling capacitor
consisting of a second switch S ₂ inserted between the other terminal of C _S and the ground terminal and controlled by a second pulse φ ₂ ;
The logical product of the output of the comparator circuit 4 and the clock φ _c is the number of pulses sent within a certain period of time (2 ⁿ -1) t seconds, which is counted by the n bit up counter 8, and the number of pulses is (2 ⁿ -1). a switched capacitor (hereinafter referred to as SC) integrator 14 that performs an inverting or non-inverting integration operation depending on whether the integrator is larger or smaller than /2;
The output of the SC integrator 14 is converted into a 2-input analog adder 3.
and a compensation signal line 7 to be applied to the other input terminal of. The specific configuration of the control signal generation circuit 5A includes an inverter I ₁ , AND circuits A ₁ , A ₂ ,
The components up to the n-bit up counters 8 and 9 and the monostable multivibrator 10 are the same as in the conventional example. The first clock pulse _φ1 is an AND circuit
It is given as the logical sum of the outputs of A ₂ and A ₃ . Similarly, the second to fourth pulses φ ₂ to φ ₄ are AND
OR of the outputs of circuit A ₂ and AND circuit A ₃ passed through delay circuit 13, AND circuit A ₃ and AND circuit
The logical sum of the output of A ₂ passed through the delay circuit 12, the logical sum of the output of AND circuit A ₂ passed through the delay circuit 12, and the output of AND circuit A ₃ passed through the delay circuit 13. are obtained respectively.

Next, the operation of this embodiment will be explained. For convenience, the explanation will be based on the assumption that n=3. FIG. 2 is a waveform diagram showing the operation of one embodiment. When the output signal of the amplifier circuit 2 (offset voltage V _OS in this case) is higher than the first reference voltage V _r1 , the output of the comparator circuit is "H".
Then, the n bit up counter 8 is counted by the AND of the comparator output and the clock pulse _φc . Since the n bit up counter 9 for time measurement is always counting, the maximum count value (2 ³ -1)・t
One pulse is output to the monostable multivibrator 10 every second=7·t seconds. At this time, if the time during which the comparator output is "H" within a certain period of time is longer than the time during which it is "L", the n bit up counter 8
The count value is (2 ³ -1)/2 within a fixed time of 7 t seconds.
From the output _Q1 of up counter 8 to exceed
"H" is output to AND circuit _A2 . However, it is assumed that the period of the input signal is sufficiently shorter than the above-mentioned fixed time. Therefore, one pulse is generated from A ₂ by logical product with the pulse φ _D that passed through the monostable multivibrator 10, and after the first and second pulses φ ₁ and φ ₂ are generated, the third and fourth pulses are generated. Pulses φ ₃ and φ ₄ are generated. Therefore, switches S ₁ and S ₂ are closed for a certain period of time,
Next, the switches S ₃ and S ₄ are closed for a certain period of time, so that the SC integrator 14 performs an inversion integration operation and integrates the negative compensation signal ΔVC ^- =-(C _S /C _I )·V _r2 .
Therefore, the output of the two-input analog adder 3 also changes by ΔVC ^- , but the above operation is repeated as long as it is higher than the first reference voltage V _r1 .

Conversely, if the time during which the comparator output is "H" is shorter than the time when it is "L" within a certain period of time, the count value does not exceed (2 ³ - 1)/2 and the n bit up counter 8 “L” is output from the output Q ₁ to the inverter I ₁ , which becomes the inverted output “H” and is sent to the AND circuit A ₃
is output to. Therefore, one pulse is generated from A ₃ by AND with the pulse φ _D passed through the monostable multivibrator 10, and the first and third pulses φ 1,
After φ ₃ is generated, second and fourth pulses φ ₂ and φ ₄ are generated. Therefore, the SC integrator 14 performs a non-inverting integration operation and generates a positive compensation signal ΔVC ⁺ =Δ(C _S /C _I )・
Integrate V _r2 and move to the positive side by the output ΔVC ⁺ of the two-input analog adder 3. As is clear from the above explanation, the positive compensation signal ΔVC ⁺ and the negative compensation signal ΔVC ^- are determined by the ratio of C _I and C _S , so |ΔVC ⁺ |=|
ΔVC ^- |, and the error that previously occurred does not occur. Since it is obvious that the SC integrator can be easily realized with a MOS integrated circuit, it goes without saying that this embodiment is suitable for a MOS integrated circuit. Furthermore, _S.R.
is a reset switch for initialization, but it is not always necessary.

A second embodiment of the present invention shown in FIG. 4 will be described. A comparison circuit 4 that places a two-input analog adder 3 immediately after the input signal terminal, uses the output of the two-input analog adder 3 as an input to an amplifier circuit 2, and compares the output of the amplifier circuit 2 with a first reference voltage. It may also be used as an input signal. Hereinafter, the circuit configuration and operating principle are the same as in the first embodiment.

〔Effect of the invention〕

As explained above, the present invention uses an SC integrator to generate a compensation signal with equal absolute values in the positive and negative directions, so the offset compensation error is small and the offset signal is suitable for MOS integrated circuits. This has the effect of providing a set cancel circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
1 is a waveform diagram showing the operation of FIG. 1, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a block diagram of another embodiment of the present invention. 1...Input signal terminal, 2...Amplification circuit, 3...
2-input analog adder, 4...comparison circuit, 5A...
...Control signal generation circuit, 6...Charging/discharging circuit, 7...
...compensation signal line, 8, 9...n bit up counter, 10...monostable multivibrator, 1
1...Amplification circuit, 12, 13...Delay circuit, 14
...SC integrator, A ₁ , A ₂ , A ₃ ...AND circuit, I ₁
...Inverter, O ₁ ~ O ₄ ... OR circuit, S ₁ ~ _{S 4}
...First to fourth switches, S _a , S _b ... Switch, S _R ... Reset switch, T _r1 , T _r2 ...
pMOS transistor, T _r3 , T _r4 ... nMOS transistor, V ⁺ ... positive power supply terminal, V ^- ... negative power supply terminal, V _r1 ... first reference voltage, V _r2 ... second reference voltage, V _r3 , V _r4 ...Reference voltage, _φ1 to _φ4 ...First to fourth pulses, _φa , _φb ...Control pulse, _φc
...Clock pulse.

Claims (1)

[Claims] 1. Amplifying means that adds a compensation signal to a predetermined input signal and amplifies it, or amplifies the input signal and adds the compensation signal, and a comparison circuit that compares the output signal of this amplification means with a reference voltage; The clock counts the time when the output of the comparator circuit is at a high level or the time when it is at a low level, and depending on whether or not the output reaches a predetermined count value within a certain period of time, A control signal that simultaneously generates two pulses and then generates a third and fourth pulse, or simultaneously generates the first and third pulses and then simultaneously generates the second and fourth pulses. a generating circuit, an operational amplifier, an integrating capacitor connected between the output and the inverting input of the operational amplifier, a sampling capacitor, and inserted between the inverting input terminal of the operational amplifier and one terminal of the sampling capacitor. a second switch inserted between one terminal of the sampling capacitor and a ground terminal and controlled by the first pulse;
a third switch inserted between the other terminal of the sampling capacitor and the second reference voltage terminal and controlled by the third pulse; a third switch inserted between the other terminal of the sampling capacitor and the ground terminal; Comprising a fourth switch controlled by a second pulse, the comparator performs an inverting integral operation or a non-inverting integral operation depending on whether the output of the comparator circuit is a prescribed count value within a certain period of time, and performs the compensation. An offset cancel circuit comprising a switched capacitor integrator that outputs a signal.