JPS6410708A - Offset canceling circuit - Google Patents

Offset canceling circuit

Info

Publication number
JPS6410708A
JPS6410708A JP62165651A JP16565187A JPS6410708A JP S6410708 A JPS6410708 A JP S6410708A JP 62165651 A JP62165651 A JP 62165651A JP 16565187 A JP16565187 A JP 16565187A JP S6410708 A JPS6410708 A JP S6410708A
Authority
JP
Japan
Prior art keywords
compensation
circuit
integration operation
offset
inverted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62165651A
Other languages
Japanese (ja)
Other versions
JPH0559603B2 (en
Inventor
Yutaka Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62165651A priority Critical patent/JPS6410708A/en
Publication of JPS6410708A publication Critical patent/JPS6410708A/en
Publication of JPH0559603B2 publication Critical patent/JPH0559603B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)

Abstract

PURPOSE:To obtain an offset cancellation circuit, which makes an offset compensation error small, and in addition is suitable to be made into a MOS integrated circuit by providing a switched capacitor integrator, which operates an inverted integration operation or a non-inserted integration operation, and outputs a compensation signal. CONSTITUTION:The number of pulses, sent from the logical product of the output of a compensation circuit 4 and a clock phic within definite time (2<n>-1).tsec ('t' is one period of clock phic), is counted by the n-bit up-counter 8 of a control signal generation circuit 5A. Then, the switched capacitor integrator 14, which operates the inverted integration operation or the non-inverted integration operation according as the number of the pulses is larger or smaller than (2<n>-1)/2. Thus, because the positive compensation signal and the negative compensation signal are determined by the ratio of an integration capacitor CI and a sampling capacitor CS, it comes to generate the compensation signals, having the same absolute values of a positive direction and a negative direction, and the offset cancellation circuit, which has the small offset compensation error, and is suitable to be made into the MOS integrated circuit, is obtained.
JP62165651A 1987-07-01 1987-07-01 Offset canceling circuit Granted JPS6410708A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62165651A JPS6410708A (en) 1987-07-01 1987-07-01 Offset canceling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62165651A JPS6410708A (en) 1987-07-01 1987-07-01 Offset canceling circuit

Publications (2)

Publication Number Publication Date
JPS6410708A true JPS6410708A (en) 1989-01-13
JPH0559603B2 JPH0559603B2 (en) 1993-08-31

Family

ID=15816408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62165651A Granted JPS6410708A (en) 1987-07-01 1987-07-01 Offset canceling circuit

Country Status (1)

Country Link
JP (1) JPS6410708A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020240693A1 (en) * 2019-05-28 2020-12-03 日本電信電話株式会社 Variable reference voltage source

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020240693A1 (en) * 2019-05-28 2020-12-03 日本電信電話株式会社 Variable reference voltage source
JPWO2020240693A1 (en) * 2019-05-28 2020-12-03

Also Published As

Publication number Publication date
JPH0559603B2 (en) 1993-08-31

Similar Documents

Publication Publication Date Title
JPS5441061A (en) Analogue/digital converter
JPS6410708A (en) Offset canceling circuit
JPS5218363A (en) Circuitry for clock
JPS55124317A (en) Digital filter circuit
JPS54161819A (en) Digital picture tracking device
JPS525577A (en) Time count correcter
CH630501B (en) TIME CORRECTION-ADJUSTMENT CIRCUIT FOR ELECTRONIC WATCH PART, ESPECIALLY ELECTRONIC BRACELET WATCH.
JPS57157621A (en) Digital error generating circuit
JPS5787617A (en) Phase shift circuit
JPS6419821A (en) Reset synchronization delay circuit
JPS6436116A (en) Timing pulse generating circuit
JPS56126311A (en) Switched capacitor circuit
JPS5789329A (en) Counting circuit
JPS57194378A (en) Test circuit of electronic clock
JPS54138975A (en) Position pulse correcting circuit
JPS55124318A (en) Overflow detection/correction circuit
JPS5286758A (en) High accurate digital delay circuit
JPS52141163A (en) Sample hold circuit
JPS6437799A (en) Dynamic shift register circuit
JPS544556A (en) Counter type encoder
JPS5516249A (en) Time modifying system of electronic clock
JPS55676A (en) Pulse delay circuit
JPS5474666A (en) Level adjusting system for counter type coder
JPS55164370A (en) Detecting unit for rise time of analogue signal
JPS6457818A (en) Phase tracking circuit