JPS5789329A - Counting circuit - Google Patents

Counting circuit

Info

Publication number
JPS5789329A
JPS5789329A JP16472880A JP16472880A JPS5789329A JP S5789329 A JPS5789329 A JP S5789329A JP 16472880 A JP16472880 A JP 16472880A JP 16472880 A JP16472880 A JP 16472880A JP S5789329 A JPS5789329 A JP S5789329A
Authority
JP
Japan
Prior art keywords
count
events
event
generated
basis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16472880A
Other languages
Japanese (ja)
Inventor
Toshio Mazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16472880A priority Critical patent/JPS5789329A/en
Publication of JPS5789329A publication Critical patent/JPS5789329A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/02—Input circuits

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To count two events efficiently, by detecting and counting two events, which are generated asynchronously, indepdendently of each other. CONSTITUTION:The up-count event and the down-count event which are generated asynchronously are detected independently of each other on the basis of the clock signal from a synchronizing clock generating circuit 3 by the first- stage latch 1U for up-count or the first-stage latch 1D for down-count. Respective events are strobed on the basis of the synchronizing clock signal after a prescribed time after latched in the first-stage latches 1U and 1D and are counted by an up/down counter 4 each time an event is generated, and a count value N at each time point is outputted to n-number output lines 41 expressing the count value. Only when respective events are sampled, the up-count, the down-count, and latches for them are cleared.
JP16472880A 1980-11-25 1980-11-25 Counting circuit Pending JPS5789329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16472880A JPS5789329A (en) 1980-11-25 1980-11-25 Counting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16472880A JPS5789329A (en) 1980-11-25 1980-11-25 Counting circuit

Publications (1)

Publication Number Publication Date
JPS5789329A true JPS5789329A (en) 1982-06-03

Family

ID=15798765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16472880A Pending JPS5789329A (en) 1980-11-25 1980-11-25 Counting circuit

Country Status (1)

Country Link
JP (1) JPS5789329A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4509183A (en) * 1982-09-16 1985-04-02 Helene R. Wright Bidirectional transition counter with threshold output
JPS62101125A (en) * 1985-10-28 1987-05-11 Koyo Denshi Kogyo Kk Input circuit for addition/subtraction counter
JPS62207024A (en) * 1986-03-07 1987-09-11 Koyo Denshi Kogyo Kk Input circuit for addition and subtraction counter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4509183A (en) * 1982-09-16 1985-04-02 Helene R. Wright Bidirectional transition counter with threshold output
JPS62101125A (en) * 1985-10-28 1987-05-11 Koyo Denshi Kogyo Kk Input circuit for addition/subtraction counter
JPS62207024A (en) * 1986-03-07 1987-09-11 Koyo Denshi Kogyo Kk Input circuit for addition and subtraction counter

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