JPS6439831A - Analog/digital converter - Google Patents

Analog/digital converter

Info

Publication number
JPS6439831A
JPS6439831A JP19530587A JP19530587A JPS6439831A JP S6439831 A JPS6439831 A JP S6439831A JP 19530587 A JP19530587 A JP 19530587A JP 19530587 A JP19530587 A JP 19530587A JP S6439831 A JPS6439831 A JP S6439831A
Authority
JP
Japan
Prior art keywords
gain
offset
input signal
calculation
analog input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19530587A
Other languages
Japanese (ja)
Inventor
Hidetoshi Kaida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP19530587A priority Critical patent/JPS6439831A/en
Publication of JPS6439831A publication Critical patent/JPS6439831A/en
Pending legal-status Critical Current

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Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To adjust an offset and a gain when a device is being operated, by estimating a digital data of an analog input signal which is omitted at the time of measuring the offset and the gain. CONSTITUTION:The offset quantity and the gain of a voltage/frequency transducer 3 are calculated each time by leading in a reference signal and a ground signal by a prescribed period, respectively, through a switching circuit 2 by a calculation control circuit 5 for executing a prescribed calculation, based on the counter output of a counter 4 for counting the number of output pulses from the transducer 3, and also, executing a control of the switching circuit 2. Subsequently, based on the offset quantity and the gain which have been calculated, a prescribed calculation is executed, the digital quantity corresponding to an unknown analog input signal is derived, and also, the digital quantity of an analog input signal which is not inputted for the calculation of the offset quantity and the gain is predicted. That is, an input signal data which has dissipated from a past data is estimated and supplemented (extrapolated). In such a way, even in the course of operation, the offset and the gain can be adjusted.
JP19530587A 1987-08-06 1987-08-06 Analog/digital converter Pending JPS6439831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19530587A JPS6439831A (en) 1987-08-06 1987-08-06 Analog/digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19530587A JPS6439831A (en) 1987-08-06 1987-08-06 Analog/digital converter

Publications (1)

Publication Number Publication Date
JPS6439831A true JPS6439831A (en) 1989-02-10

Family

ID=16338944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19530587A Pending JPS6439831A (en) 1987-08-06 1987-08-06 Analog/digital converter

Country Status (1)

Country Link
JP (1) JPS6439831A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7909232B2 (en) 2003-05-06 2011-03-22 Nomura Plating Co., Ltd. Mold and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7909232B2 (en) 2003-05-06 2011-03-22 Nomura Plating Co., Ltd. Mold and method of manufacturing the same

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