JPS5552633A - Pulse multiplication unit - Google Patents

Pulse multiplication unit

Info

Publication number
JPS5552633A
JPS5552633A JP12541378A JP12541378A JPS5552633A JP S5552633 A JPS5552633 A JP S5552633A JP 12541378 A JP12541378 A JP 12541378A JP 12541378 A JP12541378 A JP 12541378A JP S5552633 A JPS5552633 A JP S5552633A
Authority
JP
Japan
Prior art keywords
pulse signals
detection
signals
cnt1
reg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12541378A
Other languages
Japanese (ja)
Inventor
Makoto Amano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Co Ltd
Original Assignee
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Co Ltd filed Critical Shinko Electric Co Ltd
Priority to JP12541378A priority Critical patent/JPS5552633A/en
Publication of JPS5552633A publication Critical patent/JPS5552633A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain easily arbitrarily multiple pulse signals, which are synchronized with detection pulse signals approximately, by an electronic circuit by operating OR between pulse signals of a K-multiplied frequency, which are formed during one period of detection pulse signals, and detection pulse signals.
CONSTITUTION: Detection signal f is applied to counter circuit CNT1 and register circuit REG after being shaped into pulseh signal f1n. Counter circuit CNT1 counts reference pulse signals f0 were the period is fixed and a proper number of pulse signals exist between respective pulse signals of detection pulses f1n, and loads the counted value into register REG. Data of register REG is compared with data of counter circuits CNT1 and CNT2, where multiple pulse signals Kf0 are inputted, by comparator circuits CMP1 and CMP2, and outputs f2 and f3 are outputted at an agreement time. Signals f2 and f3 and detection pulse signals f1n are applied to OR gate 5, and output signals fn are taken out.
COPYRIGHT: (C)1980,JPO&Japio
JP12541378A 1978-10-11 1978-10-11 Pulse multiplication unit Pending JPS5552633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12541378A JPS5552633A (en) 1978-10-11 1978-10-11 Pulse multiplication unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12541378A JPS5552633A (en) 1978-10-11 1978-10-11 Pulse multiplication unit

Publications (1)

Publication Number Publication Date
JPS5552633A true JPS5552633A (en) 1980-04-17

Family

ID=14909484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12541378A Pending JPS5552633A (en) 1978-10-11 1978-10-11 Pulse multiplication unit

Country Status (1)

Country Link
JP (1) JPS5552633A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0495352A2 (en) * 1991-01-14 1992-07-22 Siemens Aktiengesellschaft Circuit arrangement for improving the temporal resolution of consecutive pulse-shaped signals
JPH0488891U (en) * 1990-07-12 1992-08-03

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5012875A (en) * 1973-04-09 1975-02-10
JPS5038546A (en) * 1973-06-27 1975-04-10

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5012875A (en) * 1973-04-09 1975-02-10
JPS5038546A (en) * 1973-06-27 1975-04-10

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0488891U (en) * 1990-07-12 1992-08-03
EP0495352A2 (en) * 1991-01-14 1992-07-22 Siemens Aktiengesellschaft Circuit arrangement for improving the temporal resolution of consecutive pulse-shaped signals

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