JPS55125720A - Pulse width detector - Google Patents

Pulse width detector

Info

Publication number
JPS55125720A
JPS55125720A JP3457479A JP3457479A JPS55125720A JP S55125720 A JPS55125720 A JP S55125720A JP 3457479 A JP3457479 A JP 3457479A JP 3457479 A JP3457479 A JP 3457479A JP S55125720 A JPS55125720 A JP S55125720A
Authority
JP
Japan
Prior art keywords
pulse
pulse width
inputted
reg
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3457479A
Other languages
Japanese (ja)
Inventor
Hatsuhiko Naito
Yoshitaka Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3457479A priority Critical patent/JPS55125720A/en
Publication of JPS55125720A publication Critical patent/JPS55125720A/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE: To enable to detect the pulse width with a simple constitution and high accuracy, by counting the clock pulse on the pulse width and generating the marker pulse when the output level is in agreement with the reference level.
CONSTITUTION: When the signal in which pulse width is changed is inputted to the gate AND from the terminal in, the pulse from the clock pulse genertor CLG is inputted to the counter by the number corresponding to the pulse width. The number of clock pulses N1 corresponding to the set pulse width t1 and the digital number N1 of the same number are inputted to the adder AD and held at the register REG. The output of the counter and the reference level of REG are compared at the digital comparator DC, and the marker pulse Pt1 is outputted via the multi-OM when in agreement. The output pulse N1 of REG is inputted to the adder AD into being 2N1 and stored in REG. When the pulse P1 is inputted to the reference level alteration circuit TC, 2N1 is outputted from REG to DC, the output of AD is 3N1 and marker pulse is outputted every time when the input pulse width is a multiple of the reference pulse width.
COPYRIGHT: (C)1980,JPO&Japio
JP3457479A 1979-03-23 1979-03-23 Pulse width detector Pending JPS55125720A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3457479A JPS55125720A (en) 1979-03-23 1979-03-23 Pulse width detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3457479A JPS55125720A (en) 1979-03-23 1979-03-23 Pulse width detector

Publications (1)

Publication Number Publication Date
JPS55125720A true JPS55125720A (en) 1980-09-27

Family

ID=12418088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3457479A Pending JPS55125720A (en) 1979-03-23 1979-03-23 Pulse width detector

Country Status (1)

Country Link
JP (1) JPS55125720A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53109462A (en) * 1977-03-07 1978-09-25 Mitsubishi Electric Corp Arbitrary frequency generator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53109462A (en) * 1977-03-07 1978-09-25 Mitsubishi Electric Corp Arbitrary frequency generator

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