SU1437858A1 - Computing device - Google Patents

Abstract

The invention relates to the field of computing and can be used to filter values defined by time intervals. The purpose of the invention is to expand the functionality. Set The device contains a generator 1 1-1Mpulsov, counter 2, reversible counter 3, controlled frequency divider 4, triggers 5.6, register 7, elements AND 8-14, element OR 15, distributor 16 pulses, input 17 of the coefficient division, output 18, the inputs of the values of the time intervals 19, the initial installation 20 of the device. The goal is achieved due to the possibility of filtering values represented by time intervals. 1 il. (L

Description

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The invention relates to a computational technique and can be used to filter the values specified by time intervals.

The purpose of the invention is the expansion of functional capabilities due to digital filtering of values defined by time intervals.

The drawing shows the functional diagram of the device.

The device contains a generator of 1 pulses, a counter 2, a reversible counter 3, a controlled divider 4 frequencies, triggers 5 and 6, a register 7, elements AND 8-14, an element OR 15, a distributor 16 pulses, an input 17 of the device division factor, an output 18 devices, input 19 values of time intervals, input 20 of the initial installation of the device.

The device works as follows.

Before you start the signal,

data at input 20, counters 2 and 3, and triggers 5 and 6 are reset to the zero state. In the initial state, at the input 19 of the device, there is a high level potential. In T & 4eH}, i.e., the first measured time interval T, a low level potential is supplied to this input and the pulses from the generator 1 output, the passage through elements 15 and 14, are filled with counters 2 and 3, and the end of the specified interval is the contents of these counters N where f is the frequency of the pulses of the generator 1. At the end of the first measured time interval at the input 19 of the device, the high level potential is restored, as a result of which the trigger 5 goes into one state, and the pulses from the output of the generator 1 through the elements 8 and 9 arrive on the stroke of the distributor 16. The first clock pulse from the output of the distributor 16 allows overwriting the contents of counter 2 to register 7, the second pulse from the output of the distributor 16 resets the counter 2 to the zero state, and the third clock pulse from the output of the distributor 16 passes through element 10 , translates trigger 6 into a single state S, thereby temporarily stopping the flow of pulses from the output of generator 1 to the input of the distributor 16 and allowing them to flow through elements 8 and 13 to the input of about Q

s 0

five

5 0 Q 5 Q

of the military count of the counter j and simultaneously. Separately, the contents of counter 3 are recorded to zero, after which the signal from its borrowing code, passed through element 10, returns trigger 6 to the zero state, again allowing pulses from the generator 1 output through elements 8 and 9 to the input of the distributor 6 and prohibit their arrival from the countdown input of the counter 3 and the counting input of the divider 4, From the output of the element 13 to the counting input of the divider 4 receives N pulses, where N. is the contents of the counter 3 after the first measured interval, a. from the output of divider 4 through element 14 to the counting input of counter 2 enters N.4. k pulses, where k is the divisor factor of 4, specified from the input 17 of the device.

The fourth, last, clock pulse from the output of the distributor 16, having passed through the element 12, enters the counting input of the trigger 5 and returns it to the zero state. The passage of pulses from the output of generator 1 through element 8 (9 and 13) is blocked. In addition, the fourth clock pulse from the output of the distributor 16 permits the copying of information from register 7 to counter 3. Thus, the computing device will be in a state similar to the initial one, with the only difference being that by the arrival of the next time interval TQ in counters 2 and 3 values will be fixed respectively T f- k T, -f.

When processing the second measured time interval Td, which proceeds similarly to the indicated processing of the first interval T, these values are added to the resulting counters 2 and 3, respectively.

Further analysis shows that at the output 18 of the device, the information takes place in accordance with the expression

. N (.) F (z),

where Jl (z) and T (Z) are r-transformations

respectively, the sequence received at the output 18 of the device,

and the input time interval.

Thus, the proposed device implements low-pass filtering.

Claims (1)

Invention Formula A computing device containing a counter, a reversible counter, a controlled frequency divider, the first trigger, seven AND elements and an OR element, the input clock of the device is connected to the first input of the first And element, the second input of which is connected to the forward output of the first trigger, the first inputs the second and third elements And are connected, respectively, to the output of the first element And to the output of the controlled frequency divider, which is different from the fact that, in order to expand the functional capabilities through digital filter The second trigger, register, and pulse distributor are entered into the values set by time intervals, the clock input is connected to the first input of the OR element, the second input of which is connected to the input of the OR element, the second input of which is connected to the input of the time interval values of the device and the first the input of the fourth element And, the output of which is connected to the synchronous input of the first trigger, the input of the installation of Oh which is connected to the input of the installation in O of the reversible counter, the input of the initial installation of the device in ode initial setting of the second flip-flop five 0 and to the first input of the fifth element And whose output is connected to the installation input to (J counter, the outputs of the pulse distributor from the first to the third are connected respectively to the synchronous input of the register, the second input of the fifth element And, and to the first input of the sixth element And whose output is connected to the synchronous input of the second trigger, the direct and inverse output of which is connected respectively to the first input of the seventh element Peak to the second input of the second element I, the output of which is connected to the synchronous input of the distributor, the fourth output of which connected to the second input of the fourth element Nick to the input of the reversible counter record, the overflow output and information output of which is connected respectively to the second input of the sixth AND element and to the device output, the code of the OR element is connected to the input of the addition of the reversible counter unit and the second input of the third AND element, the output of which is connected to the counting input of the counter, the output of which is connected 0 to the information input of the register, the output of which is connected to the information input of the reversible counter, the input subtraction of which is connected to the output of the seventh And element and to the counting input of the controlled frequency divider, the input of the division factor of which is connected to the input of the device dividing ratio, the output of the first element And connected to 0 the second input of the seventh element I. five 35