JPH1070440A - Cr oscillating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a CR oscillation circuit in which high oscillation frequency accuracy is realized with small hardware configuration by using one T flip-flop to alternately select either of two the CR circuits. SOLUTION: When the Q output of a T flip-flop(TFF) 18 which charges/ discharges alternately 1st and 2nd CR circuits 11, 13 exclusively is at an L level, an N-channel MOS transistor(TR) 1 is not conductive, an N-channel MOS TR 2 is conductive, a switch SW 1 is closed and a switch SW 2 is open. A comparator 16 compares a charging voltage of a capacitor C1 with a reference voltage Vref and provides an output of a pulse to the TFF 18 when they are equal to each other so as to invert an output state of the TFF 18 thereby selecting a capacitor C2 in a charging direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CR oscillation circuit,
In particular, the present invention relates to a CR oscillation circuit suitable for being incorporated in a single-chip microcomputer and its peripheral devices.

[0002]

2. Description of the Related Art FIG. 10 is a diagram showing a conventional CR oscillation circuit, in which 29 is a CR circuit having a predetermined time constant, 30 is an output terminal, and 31 is a reference for generating a predetermined reference potential _Vref. Potential circuit, 32 is a comparator, CR
The output voltage of the circuit 29 is compared with the reference potential _Vref generated by the reference potential circuit 31. A one-shot pulse generation circuit 34 generates a single pulse having a predetermined time width when an output pulse of the comparator 32 is input. R3 and C3 are resistors and capacitors constituting the CR circuit 29;
R4 and R5 are resistors constituting the reference potential circuit 31, T
R3 is an n-channel MOS transistor, and V _DD is a power supply voltage.

The CR circuit 29 comprises a resistor R3 and a capacitor C3 connected in series, and charges the capacitor C3 with a power supply voltage V _{DD according} to a predetermined time constant. Reference potential circuit 31 consists of resistors R4 and R5 connected in series, a reference from a power supply voltage V _DD potential _{V re f = V DD × R5} / (R4 +
R5).

Next, the operation will be described. Power supply voltage V _DD
When the capacitor C3 of the CR circuit 29 is charged by this, the potential at point e rises as shown in FIG. At time t52 when the potential at the point e becomes equal to the reference potential _Vref , the comparator 32 outputs a pulse to the one-shot pulse generation circuit 34. As a result, a single pulse having a predetermined time width (t52 to t53) is generated from the one-shot pulse generation circuit 34. As shown in FIG. 11, during the predetermined time (t52 to t53), the potential at the point f becomes “H”.
When the point f becomes “H”, the n-channel MOS transistor T
Since R3 is turned on, the capacitor C3 discharges the accumulated charge, and the potential at point e becomes 0V.

The CR oscillation circuit shown in FIG. 10 performs pulse oscillation having a constant frequency as shown in FIG. 11 by repeating charging and discharging of the capacitor C3 of the CR circuit 29 as described above. The oscillated pulse is taken out from the output terminal 30 to the outside.

[0006]

As shown in FIG.
A period during which the potential at the point e is rising is referred to as an H period, and a period during which the potential at the point e is falling or at 0 V is referred to as an L period. In the conventional CR oscillation circuit shown in FIG. 10, when the resistor R3 and the capacitor C3 constituting the CR circuit 29 are externally provided outside the microcomputer and a high-precision one is selected, the time width of the H period is set accurately. be able to. On the other hand, the time width of the L period is defined by the one-shot pulse generation circuit 34. Since the one-shot pulse generation circuit 34 is built in the microcomputer,
The effects of variations inherent in semiconductor integrated circuits cannot be avoided. As a result, the time width of the L period varies. This variation in the L period appears as an error in the oscillation frequency of the CR oscillation circuit.

A CR oscillation circuit shown in FIG. 12 has been proposed in order to reduce the error in the oscillation frequency due to the variation in the L period. 12, 35 is a CR circuit in which a resistor R6 and a capacitor C6 are connected in series, 36 is a terminal, 37
Is a CR in which a resistor R7 and a capacitor C7 are connected in series.
A circuit, 38 is a terminal, 40 and 42 are comparators, and 44 is an RS flip-flop. TR4 and TR5 are n-channel MOS transistors.

[0008] Negative logic signals are usually indicated by overlining the signal name. In the following description, * is added before the signal name.
It is marked with a mark. For example, a negative logic signal of the logic signal S is expressed as * S.

In the CR oscillation circuit shown in FIG.
Output when the output Q of the flip-flop 44 is "L" *
Since Q becomes “H”, the n-channel MOS transistor TR5 turns on. As a result, the potential at point h is fixed at 0V. On the other hand, since the n-channel MOS transistor TR4 is off, the capacitor C6 is charged. The capacitor C6 is charged, the potential at the point g rises, and the reference potential V
At the time when the value becomes equal to _ref , the comparator 40 outputs a pulse and sets the RS flip-flop 44.
Then, the output Q of the RS flip-flop 44 becomes “H”.
And the output * Q becomes “L”, so that the n-channel MO
S transistor TR4 turns on, and n channel MOS transistor TR5 turns off. As a result, the capacitor C6
Starts discharging, and the capacitor C7 starts charging, and continues charging until the potential at the point h becomes equal to the reference potential _Vref .

The CR oscillation circuit shown in FIG. 12 performs pulse oscillation at a constant frequency by repeating the above process.
The oscillated pulse is taken out from the terminal 36 or the terminal 38 to the outside.

In this CR oscillation circuit, the capacitor C
6 is called an H period, and a period when the capacitor C7 is charged is called an L period.
And the time constant determined by the capacitor C6, and the L period is defined by the time constant determined by the resistor R7 and the capacitor C7. Resistance R6, capacitor C6
Since the resistor R7 and the capacitor C7 can be externally connected to the microcomputer and a good product can be selected, both the H period and the L period can have an accurate time width.

Since the improved CR oscillation circuit shown in FIG. 12 is constructed as described above, accurate H period and L
Since the period can be realized, the accuracy of the oscillation frequency is good.
Since the number of comparators 40 and 42 is required, there is a problem that the amount of hardware increases. As a result, there has been a problem that the circuit configuration of the microcomputer is complicated and the cost is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. By alternately switching two sets of CR circuits by one T-type flip-flop, high oscillation frequency accuracy can be achieved with a small hardware configuration. It is an object of the present invention to obtain a CR oscillation circuit capable of realizing the above.

[0014]

According to a first aspect of the present invention, a CR oscillation circuit alternately compares two CR circuits and a charging voltage of the two CR circuits with a reference potential. A voltage detecting means for detecting a point in time at which the two CR circuits become equal to each other, and a switching means for exclusively switching the two CR circuits to a charging state or a discharging state based on the detection result of the voltage detecting means.

According to a second aspect of the present invention, the CR oscillation circuit includes a first CR circuit and a second CR circuit, each of which has a unique time constant and performs charging and discharging, and the voltage detecting means includes the first CR circuit and the second CR circuit. The comparator comprises a comparator for comparing the charging voltage of the 1CR circuit or the second CR circuit with the reference potential and outputting a pulse when the two become equal, and the switching means switches the T to which the output pulse from the comparator is input.
-Type flip-flop, a first switching element and a second switching element that operate in conjunction with each other to control charging and discharging of the first CR circuit and the second CR circuit by the Q output and the inverted Q output of the T-type flip-flop, and in conjunction with each other A first switch for controlling a connection between the first CR circuit and the comparator by a Q output and an inverted Q output of the T-type flip-flop; and the second CR.
A second switch for controlling the connection between the circuit and the comparator.

A CR oscillation circuit according to a third aspect of the present invention comprises a first CR circuit and a second CR circuit each including a resistor and a capacitor connected in series.

According to a fourth aspect of the present invention, in the CR oscillation circuit, the first switching element and the second switching element include MOS transistors.

In the CR oscillation circuit according to the fifth aspect of the invention, the reference potential is set to a value within a range in which the variation of the oscillation frequency is minimized.

In the CR oscillation circuit according to the present invention, the reference potential is set in a range from 0.6 times to 0.66 times the power supply voltage.

According to a seventh aspect of the present invention, a non-overlap portion is provided between the "H" period of the Q output of the T-type flip-flop and the "H" period of the inverted Q output. is there.

In the CR oscillation circuit according to the present invention, a two-input AND gate and a two-input NO gate are provided after the Q output terminal or the inverted Q output terminal of the T-type flip-flop.
An R gate is juxtaposed, the terminal output is divided into two, one is directly input to the two-input AND gate and the two-input NOR gate, and the other is input to the two-input AND gate and the two-input NOR gate via a delay circuit. Is to be entered.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 shows C according to Embodiment 1 of the present invention.
FIG. 3 is a diagram showing an R oscillation circuit, in which 11 is the first C
R circuit (CR circuit), 12 is a first output terminal, 13 is a second output terminal
A CR circuit (CR circuit), 14 is a second output terminal, 16 is a comparator (voltage detecting means), and 18 is a T-type flip-flop (hereinafter, also referred to as TFF, switching means). R
1, R2 are resistors, C1, C2 are capacitors, TR1, T
R2 is an n-channel MOS transistor (MOS transistor, first switching element, second switching element,
Switching means), SW1 and SW2 are switches (first switch,
Second switch, switching means). V _ref is a reference potential.

The first CR circuit 11 is composed of a series connection of a resistor R1 and a capacitor C1, and charges the capacitor C1 with a power supply voltage _VDD with a time constant R1 × C1. Second CR circuit 13
Consists of a series connection of a resistor R2 and a capacitor C2, and charges the capacitor C2 with a power supply voltage V _DD with a time constant R2 × C2.

The switches SW1 and SW2 are set as follows. That is, when the Q terminal output of the TFF 18 is "L" and the * Q terminal output is "H", the switch SW1
Is closed and the switch SW2 is opened. Conversely, when the Q terminal output of the TFF 18 is "H" and the * Q terminal output is "L", the switch SW1 is open and the switch SW2 is closed.

Next, the operation will be described. FIG. 2 shows FIG.
A of the CR oscillation circuit according to the first embodiment of the present invention shown in FIG.
FIG. 6 is a diagram showing a waveform at a point, a waveform at a point b, and an output of a Q terminal of the TFF 18. Hereinafter, referring to FIGS. 1 and 2, FIG.
The operation of the CR oscillation circuit according to the first embodiment of the present invention will be described.

As shown in FIG. 2, at time t11, T
When the output Q of the FF 18 is "L", the output of the TFF 18 *
Since Q becomes "H", the n-channel MOS transistor TR1 is turned off, the n-channel MOS transistor TR2 is turned on, the switch SW1 is closed, and the switch SW2 is open.
Then, since the n-channel MOS transistor TR2 is on, the potential at the point b is pulled down to the ground (GND) potential and fixed at 0V. On the other hand, since the n-channel MOS transistor TR1 is off, the capacitor C1 starts charging. At the time t12 when the charging of the capacitor C1 continues and the potential at the point a rises and becomes equal to the reference potential _Vref , the comparator 16 outputs a pulse to the TFF.

When a pulse is input to the T terminal of the TFF 18, the output Q of the TFF 18 becomes "H" and the output * Q becomes "L", so that the n-channel MOS transistor TR
1 turns on, and the n-channel MOS transistor TR2 turns off. SW1 is opened and SW2 is closed. n
Since the channel MOS transistor TR1 is on,
The capacitor C1 starts discharging the accumulated charge, and discharges until the potential at the point a becomes 0V. On the other hand, the capacitor C2 starts charging and continues charging until the potential at the point b becomes equal to the reference potential _Vref .

The comparator 16 outputs a pulse at time t13 when the charging of the capacitor C2 continues and the potential at the point b rises and becomes equal to the reference potential _Vref, and the pulse is input to the TFF 18. As a result, the output Q of the TFF 18 becomes “L”,
Since the output * Q becomes “H”, the initial state (time t11
State), and the potential at point a starts to rise.

By repeating the above process, pulse oscillation at a constant frequency is performed. The oscillation pulse is extracted from the first output terminal 12 or the second output terminal 14 to the outside.
The oscillation waveform extracted from the first output terminal 12 is shown in FIG.
It is the same as the waveform shown at the point, and the oscillation waveform taken out from the second output terminal 14 is the same as the waveform at the point b.

In this CR oscillation circuit, as shown in FIG. 2, a period during which the capacitor C1 is charging is referred to as an H period, and a period during which the capacitor C2 is charging is referred to as an L period. Given by the formula. H period = −R1 × C1 × LN (1−V _ref / V _DD ) (1) L period = −R2 × C2 × LN (1−V _ref / V _DD ) (2) LN represents a natural logarithm, _Vref is a reference potential, V
_DD is the power supply voltage. From the equations (1) and (2), the oscillation frequency f is obtained as in the following equation. f = 1 / (H period + L period) [Hz] (3)

As described above, according to the first embodiment, the following effects can be obtained. As can be seen from the equations (1) to (3), the resistors R1 and R2 and the capacitor C
The oscillation frequency f can be determined by the values of 1, C2. Since the resistors R1 and R2 and the capacitors C1 and C2 can be externally provided outside the microcomputer, high-precision ones can be selected. This makes it possible to improve the accuracy of the oscillation frequency f.

Further, in the conventional CR oscillation circuit, it is necessary to increase the driving capability of the n-channel MOS transistor in order to reduce the influence of the variation in elements built in the microcomputer. On the other hand, in the CR oscillation circuit according to the first embodiment, the n-channel MOS transistor TR1 or TR2 pulls the point a or the point b to "L" only in a half cycle. Therefore, n-channel MOS transistor TR1 or TR2
Has enough time, so that the driving capacity is small. As a result, n channel MOS transistor TR
1 and TR2 can be reduced in size, which contributes to downsizing and low power consumption of the microcomputer.

Further, as can be seen from equations (1) and (2), the H period can be determined only by the combination of the resistor R1 and the capacitor C1, and the L period is determined only by the combination of the resistor R2 and the capacitor C2. You can decide. That is, since the H period and the L period can be determined independently of each other, the duty of the oscillation pulse can be freely set. For example, the waveform at point a shown in FIG. 2 is output from the first output terminal 12, and the duty of the pulse obtained from the first output terminal 12 is given by the following equation. H period / (H period + L period) (4) As described above, the H period is determined by the time constant R1 × C1.
Since the period is determined by the time constant R2 × C2, the resistances R1, R2
By appropriately selecting the capacitors C1 and C2, the duty of the oscillation pulse can be set to a desired value from the equation (4).

Further, in the CR oscillation circuit according to the first embodiment shown in FIG.
Only one comparator and one flip-flop were used for each. To make this possible, a T-type flip-flop is used as the flip-flop 18 and the switches SW1 and SW2 are alternately opened and closed, so that the potential at the point a and the potential at the point b are alternately input to the comparator 16. I have to. in this way,
According to the first embodiment, the amount of hardware can be reduced, which contributes to miniaturization and low power consumption of the microcomputer.

Embodiment 2 The second embodiment is similar to FIG.
By setting the reference potential _Vref of the comparator 16 of the CR oscillation circuit according to the first embodiment to an optimum value, the variation of the oscillation frequency due to the variation of the comparator is minimized.

FIG. 3 is a circuit diagram of the C according to the first embodiment shown in FIG.
FIG. 5 is a diagram illustrating a time change of an output voltage Vo from a first output terminal 12 of the R oscillation circuit. In FIG. 3, the vertical axis represents the normalized output voltage (Vo / V _DD ) obtained by dividing the output voltage Vo by the power supply voltage V _DD , and the horizontal axis represents the RC delay time (unit: 10 ⁻⁸ seconds). In the CR oscillation circuit according to the first embodiment shown in FIG. 1, when n-channel MOS transistor TR1 is turned off and capacitor C1 forming first CR circuit 11 is charged, output voltage Vo from first output terminal 12 changes with time. It changes as shown in FIG.

As can be seen from FIG. 3, the output voltage Vo rises steeply and becomes equal to the power supply voltage V _DD in a short time. Therefore, when the reference potential V _ref is set to a value close to the power supply voltage V _DD , When the determination potential of the comparator 16 varies, the variation of the oscillation frequency f increases. Conversely, if the reference potential _Vref is set to a value close to the ground potential (0 V), the RC delay time is shortened and the oscillation cycle is shortened. Become like

FIG. 4 is a diagram showing an example of the RC delay time error when the reference potential _Vref is changed when the voltage judgment error of the comparator 16 is 10 mV. In the figure, each column shows, from the left, a reference potential V _ref (V), an RC delay time t (ns), an RC delay time error (ns), and an error rate (%). However, the power supply voltage V _DD = 5.00 (V)
It is. The error rate (%) is calculated from the following equation. Error rate (%) = RC delay time error (ns) ÷ RC delay time t (ns) × 100 (5)

FIG. 5 shows a reference potential V _ref (V) (power supply voltage V _ref (V)).
FIG. 10 is a diagram plotting the RC delay time t (ns) and the error rate (%) when ( _DD = 5 V) is changed from 0.00 V to 5.00 V.

4 and 5 that the error rate in the range indicated by "A" in each figure is the smallest. The range of the reference potential _Vref corresponding to the range indicated by “A” is 3.00 V to 3.30 V. 4 and 5
Is the value when the power supply voltage V _DD is 5 V, so that the optimum range of the reference potential V _ref at which the error rate becomes the smallest is 0.
6V _DD ~0.66V _DD is obtained. As can be seen from the above equations (1) to (3), since the RC delay time defines the oscillation frequency f, the optimum range of the reference potential V _ref at which the error rate of the RC delay time becomes the smallest is 0. 6V
_{DD ~0.66V DD} is, to minimize the variation of the oscillation frequency f.

As shown in equations (1) to (3),
R1 and R defining H period, L period and oscillation frequency f
2, C1 and C2 are all coefficients, and changing these values only changes the H period or the L period, that is, the RC delay time. Since the RC delay time error changes according to the rate of change of the RC delay time, the error rate calculated from equation (5) does not change. FIG. 6 shows the reference potential V _ref when the value of the capacitor C is set to 5 times as compared with the case of FIG.
(V), RC delay time t (ns), RC delay time error (ns) and error rate (%). FIG. 6 shows that the RC delay time t (ns) and the RC delay time error (ns) are five times as large as those in FIG. 4, but the error rate does not change. Therefore, the range in which the error rate indicated by “A” in the figure is the smallest is the same as that in FIG.

FIG. 4 and FIG.
7 shows a value when the voltage judgment error is 10 mV. FIG. 7 shows a case where the voltage judgment error changes to 20 mV, for example, which is twice as large. From FIG. 7, it can be seen that the RC delay time error is doubled and the error rate is doubled as compared with FIG. However, the range of the reference potential _Vref having the smallest error rate matches the case of FIG. 4 as indicated by “A” in the figure.

[0043] As described above, according to the second embodiment, when the power supply voltage is V _DD, by setting the reference potential V _ref of the comparator 16 in the range of 0.6V _DD ~0.66V _DD, The variation of the oscillation frequency f can be minimized.

Embodiment 3 FIG. FIG. 8 is a circuit diagram showing a T oscillator used in the CR oscillation circuit according to the first embodiment of the present invention shown in FIG.
FIG. 3 is a diagram showing output waveforms of a Q output and a * Q output of a type flip-flop 18. FIG. 8A shows an output waveform of a simple TFF. As can be seen from the figure, a simple TFF
In this case, the edge of the "H" period of the Q output and the edge of the "H" period of the * Q output are critical. For example, at time t2
If the fall of the Q output is delayed or the rise of the * Q output is advanced in 2, there is a possibility that both the Q output and the * Q output will be in the "H" state and overlap. When the overlap occurs, the points a and b in FIG. 1 are short-circuited (short-circuited), so that the circuit does not operate normally. As a result, the lengths of the H period and the L period shown in FIG. 2 vary, and the accuracy of the oscillation frequency f decreases.

The above problem can be prevented by taking non-overlapping measures so that the "H" period of the Q output of the TFF 18 and the "H" period of the * Q output do not overlap. . The third embodiment provides a TFF with a non-overlapping measure.

FIG. 8B shows an output waveform of a TFF in which non-overlapping measures are taken. For example, a dead time (non-overlap portion) (t33 to t34) is provided between the "H" period of the Q output (t32 to t33) and the "H" period of the * Q output (t34 to t35). Therefore, the "H" period of the Q output and the "H" period of the * Q output do not overlap.

FIG. 9 is a graph showing T with non-overlapping measures.
FIG. 2 is a diagram illustrating a circuit configuration of an FF and waveforms of respective units. FIG.
As shown in (a), the TFF 18 which has been subjected to non-overlapping measures uses only the Q output. Q output is delay circuit 2
It is branched into two before 0. One is a direct 2-input AND
The signal is input to the gate 22 and the two-input NOR gate 24, and the other is input to the two-input AND gate 22 and the two-input NOR gate 24 after being delayed by the delay circuit 20. Q ′ is output from the two-input AND gate 22, and the two-input NOR
* Q ′ is output from the gate 24.

FIG. 9B shows the waveforms at points c, d, Q 'output and * Q' output. The waveform at the point d passed through the delay circuit 20 is represented by t4 from the waveform at the point c which is the Q output of the TFF 18.
It is delayed by 1 to t42. Q 'output is the waveform at point c and d
It is obtained by ANDing with the point waveform. * Q '
The output is the NOR of the waveform at point c and the waveform at point d. As a result, the “H” period of the Q ′ output (t4
2 to t43) and the “H” period of the * Q ′ output (t44 to t4)
5) does not overlap, and there is a dead time (non-overlapping portion) (t43 to t44) between the two.

In the third embodiment, Q 'output and * Q' output through the circuit shown in FIG. 9A are used instead of the Q output and * Q output of the TFF 18.

In the circuit example of FIG. 9A, an example is shown in which the Q output of the TFF 18 is used. However, the same effect can be obtained by using the * Q output only by inverting the polarities of the Q 'output and * Q' output. can get.

As described above, according to the third embodiment, a non-overlapping measure is taken so that the "H" period of the Q output of the TFF 18 and the "H" period of the * Q output do not overlap. In addition, the oscillation frequency can be accurately and stably maintained.

[0052]

As described above, according to the first aspect of the present invention, the CR oscillation circuit comprises two CR circuits and the two C
A voltage detecting means for alternately comparing the charging voltage of the R circuit with a reference potential and detecting a point in time at which the charging voltage becomes equal to the reference potential, and the two CR circuits are mutually exclusive based on a detection result of the voltage detecting means. Since the switching means for switching between the charging state and the discharging state is provided, there is an effect that high oscillation frequency accuracy can be obtained with a small hardware configuration.

According to the second aspect of the present invention, the CR oscillating circuit comprises a first CR circuit and a second CR circuit each of which has two time constants and performs charging and discharging.
The voltage detecting means comprises a comparator which compares the charging voltage of the first CR circuit or the second CR circuit with a reference potential and outputs a pulse when the two become equal, and the switching means receives an output pulse from the comparator. T-type flip-flop, which operates in conjunction with each other, outputs the first CR by the Q output and the inverted Q output of the T-type flip-flop.
A first switching element and a second switching element for controlling charging and discharging of the circuit and the second CR circuit, and
A first switch for controlling a connection between the first CR circuit and the comparator by a Q output and an inverted Q output of the T-type flip-flop in cooperation with each other;
A second circuit for controlling the connection between the R circuit and the comparator;
Since the switch is constituted by the switch, there is an effect that the duty of the oscillation pulse can be freely set.

According to the third aspect of the present invention, since the first CR circuit and the second CR circuit are each formed of a resistor and a capacitor connected in series, the resistors and the capacitor have high precision as external components. Since it can be selected, there is an effect that the accuracy of the oscillation frequency can be improved.

According to the fourth aspect of the present invention, since the first switching element and the second switching element are constituted by MOS transistors, the main part can be formed in the integrated circuit. C according to the invention
There is an effect that it is easy to apply the R oscillation circuit to a microcomputer or the like.

According to the fifth aspect of the present invention, since the reference potential is set to a value within a range in which the variation of the oscillation frequency is minimized, there is an effect that a CR oscillation circuit with high oscillation frequency accuracy can be obtained. .

According to the sixth aspect of the present invention, the reference potential is set in a range from 0.6 times to 0.66 times the power supply voltage. There is an effect that a specific value can be obtained.

According to the seventh aspect of the present invention, the "H" period of the Q output of the T-type flip-flop and the "H" period of the inverted Q output.
Since the non-overlap portion is provided between the periods, the oscillation frequency can be accurately and stably maintained.

According to the present invention, a two-input AND gate and a two-input NOR gate are arranged next to the Q output terminal or the inverted Q output terminal of the T-type flip-flop, and the terminal output is divided into two. , One of which is directly input to the two-input AND gate and the two-input NOR gate, and the other is input to the two-input AND gate and the two-input NOR gate via a delay circuit. "H" period of the Q output of the
Since a non-overlapping portion in which the output “H” period does not overlap can be formed, there is an effect that the oscillation frequency can be accurately and stably maintained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a CR oscillation circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a waveform at point a, a waveform at point b, and a Q terminal output of a TFF in the CR oscillation circuit shown in FIG.

FIG. 3 is a diagram showing a time change of an output voltage Vo from an output terminal of a CR oscillation circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of an RC delay time error when the reference potential _Vref is changed when the voltage determination error of the comparator is 10 mV.

FIG. 5: Reference potential V _ref (V) (power supply voltage V _DD = 5 V)
FIG. 10 is a diagram plotting an RC delay time t (ns) and an error rate (%) when (time) is changed from 0.00V to 5.00V.

6 is a diagram _showing a reference potential V _ref (V) and an RC delay time t when the value of the capacitor C is set to 5 times as compared with the case of FIG. 4;
(Ns), RC delay time error (ns), and error rate (%).

FIG. 7 shows a reference potential V _ref (V), an RC delay time t (ns), and a reference potential V _ref (V) when the voltage determination error changes to 20 mV which is twice as large.
It is a figure which shows RC delay time error (ns) and an error rate (%).

FIG. 8 is a diagram showing output waveforms of a Q output and a * Q output of a T-type flip-flop (TFF) used in a CR oscillation circuit according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a circuit configuration of a TFF in which non-overlapping measures are taken and waveforms of respective units.

FIG. 10 is a diagram showing a conventional CR oscillation circuit.

FIG. 11 is a diagram showing a waveform at point e and a waveform at point f in the conventional CR oscillation circuit.

FIG. 12 is a diagram illustrating a CR oscillation circuit proposed to reduce an error in oscillation frequency caused by variation in an L period generated in a conventional CR oscillation circuit.

[Explanation of symbols]

11 1st CR circuit (CR circuit), 13 2nd CR circuit (CR circuit), 16 comparators (voltage detecting means), 1
8 T-type flip-flop (switching means), R1, R2
Resistors, C1, C2 capacitors, TR1, TR2 n-channel MOS transistors (MOS transistors, first
Switching element, second switching element, switching means), SW1, SW2 switches (first switch, second switch, switching means), _Vref reference potential.

Claims (8)

[Claims] A voltage detecting means for comparing the charging voltages of the two CR circuits with a reference potential alternately and detecting a point in time at which the charging voltage becomes equal to the reference potential; A switching circuit for switching the two CR circuits to a charging state or a discharging state exclusively based on a detection result. 2. The two CR circuits each comprise a first CR circuit and a second CR circuit which have their own time constants and perform charging and discharging, and the voltage detecting means determines the charging voltage of the first CR circuit or the second CR circuit. The comparator comprises a comparator for comparing the reference potential and outputting a pulse when the two become equal. The switching means is a T-type flip-flop to which the output pulse from the comparator is inputted. A first switching element and a second switching element for controlling charging and discharging of the first CR circuit and the second CR circuit by an output and an inverted Q output;
And a first switch for controlling a connection between the first CR circuit and the comparator by a Q output and an inverted Q output of the T-type flip-flop in conjunction with each other, and a connection between the second CR circuit and the comparator. 2. The CR oscillation circuit according to claim 1, further comprising a second switch for controlling the operation of the CR oscillator. 3. The CR oscillation circuit according to claim 2, wherein each of the first CR circuit and the second CR circuit comprises a resistor and a capacitor connected in series. 4. The CR oscillation circuit according to claim 2, wherein the first switching element and the second switching element comprise MOS transistors. 5. The CR oscillation circuit according to claim 1, wherein the reference potential is set to a value within a range in which a variation in oscillation frequency is minimized. 6. A method according to claim 1, wherein the reference potential is set to 0.6 to 0.
2. The method according to claim 1, wherein the range is set up to 66 times.
The CR oscillation circuit according to any one of claims 1 to 4. 7. The "H" level of the Q output of the T-type flip-flop.
7. A non-overlapping section is provided between the period and the "H" period of the inverted Q output.
The CR oscillation circuit according to any one of the preceding claims. 8. A two-input AND gate and a two-input NOR gate are arranged next to the Q output terminal or the inverted Q output terminal of the T-type flip-flop, and the terminal output is divided into two.
One is the 2-input AND gate and the 2-input NOR
8. The CR oscillation according to claim 2, wherein a signal is directly input to a gate and the other is input to the two-input AND gate and the two-input NOR gate via a delay circuit. circuit.