JP2001006384A - Sample and hold circuit and reference voltage generation circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sample and hold circuit by which the same output voltage and characteristic can be obtained in the sample mode and the holding mode and a reference voltage generation circuit connectable with a load with a high frequency by applying, this sample and hold circuit. SOLUTION: By preparing two capacitors for sampling a voltage of the same terminal and using them alternately, the same circuit state can be secured in the sample mode and the holding mode, and the same output voltage and the same characteristic are obtained. The reference voltage generation circuit is comprised of two circuit blocks B1, B2, and the 1st circuit block B1 generates a fixed reference voltage and also makes a high-frequency connection possible between the reference voltage generation circuit and a load by applying the sample and hold circuit to the 2nd circuit block B2. For stabilizing the voltage and permitting a high-frequency connection, the 1st circuit block B1 and the 2nd circuit block B2 vary the clock duty and frequency for driving the circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit for generating and supplying a reference voltage when performing a signal operation / amplification process using a fully differential amplifier using a CMOS circuit, and an output of the reference voltage generating circuit. The present invention relates to a sample / hold circuit for stabilization.

[0002]

2. Description of the Related Art Various analog signal processing circuits include:
In some cases, a circuit called a sample / hold circuit is used to transfer a signal between a certain signal source and a circuit that processes the signal. In this sample / hold circuit, an input voltage (signal voltage) sampled in the sample mode is held during the hold mode period, so that it is often used for an A / D converter that requires a certain amount of time for signal processing.

[0003] A circuit as shown in FIG. 4 is known as one of sample / hold circuits for transferring such signals. (DAJOHNS, K.MARTIN, Analog Integra
tedCircuit Design John Wiley & Sons, Inc., 1997
See p348. A paper published in 1991 by N. Sooch et al. Is provided as a reference. ). This sample / hold circuit has a low-pass filter function in addition to the sample / hold function, and is considered to be a circuit that is advantageous for transferring a DC signal or a very low frequency signal.

First, the operation of this circuit will be described. In this circuit, an input signal Vs is applied to an input terminal Vin. In this state, first, in the sample mode, the switch SW-a selects the terminal connected to the ground potential which is the reference of the operation of the first input terminal Via of the amplifier AMP-a, and the switch SW-b selects the input terminal Vin. By doing so, the signal Vs applied to the input terminal Vin is sampled on the capacitor Cb. At this time, the capacitor Ca is charged to a certain voltage, but due to the characteristics of the amplifier AMP-a,
Since the first input terminal Via is at the ground potential, the voltage charged in the capacitor Ca is output to the output terminal Vo. Next, when the switch SW-a enters the hold mode, the first switch of the amplifier AMP-a is turned on.
Input terminal Via is selected, and the switch SW-b is connected to the output terminal V
When o is selected, the input terminal Vin is disconnected from the main circuit. A capacitor Ca and a capacitor Cb are provided between the input terminal Via and the output terminal Vo of the amplifier AMP-a.
Are connected in parallel.

In the course of such an operation, the voltage charged in the capacitor Ca is basically a weighted average of the input signal Vs sampled up to that time, and the input signal Vs is always constant in the sample mode. When a voltage is supplied, the above operation is repeated, and when the circuit reaches a steady state, the voltage charged to the capacitor Ca and the voltage charged to the capacitor Cb in the sample mode have the same value. . Since the voltage value is the input signal voltage in the sample mode, it is considered that the output voltage in the sample mode and the output voltage in the hold mode have the same value under such conditions. .

An A / D converter for converting an analog signal into a digital signal is one of the circuits for transferring a DC voltage as described above. In this A / D converter, an input signal is compared with a certain voltage, and a conversion from an analog signal to a digital signal is performed by determining “0” or “1” according to the magnitude relationship. If there is a fluctuation in the voltage that becomes the reference for "
Since the boundary for determining 0 ”and“ 1 ”is unclear, high-precision conversion cannot be performed, and therefore, a very stable voltage is required as a reference voltage for this comparison. A stabilized voltage will be supplied.

Various types of A / D converters have been proposed. One of them is an A / D converter using a fully differential amplifier having excellent common-mode noise removal performance and the like as a fundamental element of a circuit. A / D converter is known.
In an A / D converter using this full differential amplifier,
The output of the amplifier is on the + side (hereinafter p) with respect to a certain voltage (hereinafter, referred to as a common code voltage (referred to as Vcm)).
Called output. ) And two outputs on the negative side (hereinafter referred to as n outputs). In some cases, two reference voltages, one corresponding to the p output and the other corresponding to the n output, are required as the reference voltages. Many (eg SHLewis et al. Journal o
f Solid-State Ciorcuit, Vol.SC-22, pp.954-961 (198
7)). FIG. 5 shows an example of a circuit for generating such two reference voltages (G. Nicollini et al., Journal of Solid-State Ciorcuit, V
ol.SC-26, pp. 41-50 (1991), and JP-A-5-1815
No. 56).

The reference voltage generating circuit shown in FIG. 5 includes first and second constant current sources I1 and I2 controlled so that substantially equal currents flow, and an area A1 connected to the first constant current source I1.
Area A2 (A) connected to a first bipolar transistor Q1 having an emitter E1 of
2> A first unit Y1 having a second bipolar transistor Q2 having an emitter E2 of A1), first and second input terminals Vi1 and Vi2, and first and second output terminals Vo1 and Vo2. FULL DIFFERENTIAL AMPLIFIER AMP
1 and the first voltage V1 connected to the emitter E1 of the first bipolar transistor Q1 of the first unit Y1.
Switch TA1 that can select a terminal TA1 of the first full-differential amplifier and a capacitor Cx1 connected between the first switch SW1 and a first input terminal Vi1 of the first full differential amplifier. Of the first capacitor C1, the terminal TA1, and the second bipolar transistor Q2 of the first unit.
Terminal TA2 of the voltage V2 connected to the emitter E2 of the
And a second capacitor C2 of a capacitance Cx2 connected between the second switch SW2 and the first input terminal Vi1 of the first full differential amplifier. A third switch SW3 capable of selecting the terminal TA1 and the ground terminal; a third switch SW3 and a second input terminal Vi2 of the first full differential amplifier AMP1.
And a third capacitor C3 of a capacitance Cx1 connected between
A fourth switch SW4 capable of selecting the terminal TA1 and the terminal TA2; a fourth switch SW4 and a first input terminal Vi2 of the first full differential amplifier AMP1.
And a fourth capacitor C4 of capacitance Cx2 connected between
A fifth switch SW5 capable of selecting a first output terminal Vo1 of the first full differential amplifier AMP1 and a first voltage terminal TD1 for supplying a common code voltage Vcm; and a fifth switch SW5. SW5 and the first full differential amplifier A
A capacitor C connected between the first input terminal Vi1 of MP1
The connection between the x3 fifth capacitor C5, the first input terminal Vi1 of the first full differential amplifier AMP1, and the first output terminal Vo1 of the first full differential amplifier AMP1 is turned on / off. A sixteenth switch SW6 capable of selecting a fifteenth switch SW15 to be turned off, a second output terminal Vo2 of the first full differential amplifier AMP1, and a first voltage terminal TD1 for supplying a common code voltage Vcm. And the sixth switch SW
6 and a second capacitor C6 of a capacitance Cx3 connected between the second input terminal Vi2 of the first full differential amplifier AMP1 and a second capacitor C6 of the first full differential amplifier AMP1.
And a second unit Y2 having a sixteenth switch SW16 for turning on / off the connection between the input terminal Vi2 and the second output terminal Vo2 of the first full differential amplifier AMP.

This circuit operates as a reference voltage generating circuit that generates a constant voltage that is almost independent of temperature by the following operation (however, here, for the sake of simplicity, two output voltages generated by this circuit are used). Only the operation of generating one voltage is shown. The other voltage generating operation is basically the same except that the sampling voltage is different.)

First, in the first unit Y1, the first and second constant current sources I1 and I2 are controlled so that substantially equal currents flow. The area A1 of the emitter E1 of the first bipolar transistor Q1 connected to the first constant current source I1 is different from the area A2 of the emitter E2 of the second bipolar transistor Q2 connected to the second constant current source I2. (For example, A2 / A1-10
Is set to 2.) The densities of the currents flowing through the two bipolar transistors will be different. At this time, due to the nature of the emitter-base voltage of the bipolar transistor,
Emitter voltage V1 of first bipolar transistor Q1
And the emitter voltage V of the second bipolar transistor Q2
2 decreases with temperature at about 2 mV / ° C. On the other hand, the difference (V1-V2) between the emitter voltages of the two bipolar transistors Q1 and Q2 is about 0.198 mV / ° C.
(However, when A2 / A1 to 10).

The voltage V generated in the first unit Y1
1 and V2, the second unit Y2 first
During the operation period T1, the first and second capacitors C1 and C2
Are connected to a terminal TA1 having a voltage V1 by first and second switches SW1 and SW2, respectively.
At this time, the voltage of the first input terminal Vi1 of the amplifier is a certain voltage, but this voltage is equal to the first input terminal Vi1 and the second input terminal Vi1.
An offset voltage having the same absolute value and opposite sign for the first input terminal and the second input terminal with respect to the reference voltage (referred to as VB1) of the operation of the input terminal (the magnitude is Vos1 /
2)).
This can be shown as VB1 + Vos1 / 2. Therefore, the first and second capacitors C1 and C2 are both (VB1
+ Vos1 / 2) -V1.
Also, at this time, the terminal of the fifth capacitor C5 opposite to the input terminal Vi1 of the amplifier is connected to the first voltage terminal TD1 by the fifth switch SW5, and this fifth capacitor C5 is connected to (VB1 + Vos1). / 2) It means that the battery is charged to a voltage of -Vcm. The first output terminal Vo1 is connected to the first input terminal Vi1 via the fifteenth switch SW15, and its voltage is the same as that of the first input terminal Vi1, VB1 + V.
It is os1 / 2. That is, in the first operation period T1, the output of the reference voltage generation circuit does not have the predetermined reference voltage value.

Next, when the selection of the first, second, fifth, and fifteenth switches is switched to enter a second operation period T2, the first and second capacitors C1 and C2 are switched to the first and second capacitors, respectively. The first and second switches SW1 and SW2 respectively connect the ground potential and the second terminal TA2 which is the emitter voltage V2 of the second bipolar transistor Q2. At this time, the first input terminal Vi1 of the full differential amplifier AMP1
Maintain the same VB1 + Vos1 / 2 as in the first operation period T1. At this time, the terminal of the fifth capacitor C5 opposite to the first input terminal Vi1 of the full differential amplifier is connected to the first output terminal Vo1 of the full differential amplifier.

Here, paying attention to the amount of charge stored in each capacitor during the first operation period T1 and the second operation period T2, the electric charge storage of the node connected to the first input terminal Vi1 of the full differential amplifier AMP1 is performed. In consideration of the above, when the voltage Vout11 of the first output terminal Vo1 of the full differential amplifier AMP1 in the settling state in the second operation period T2 is obtained, Vout11 = Vcm + {Cx1 * V1 + Cx2 * (V1-V2)} / Cx3 (1). (The output Vout12 of the second output terminal Vo2 of the full differential amplifier is similarly obtained, and the differential output Vref1 = (Vout11−
When Vout12) is obtained, Vref1 = 2 * {Cx1 * V1 + Cx2 * (V1-V2)} / Cx3 (2) is a value independent of Vcm. )

Here, the temperature was changed by selecting an appropriate value (Cx2 / Cx1-10 if the above-mentioned temperature dependence of V1, (V1-V2) is assumed) of the ratio between the capacitances Cx1 and Cx2. Sometimes, the change in the voltage V1 and the voltage (V
1-V2) will cancel each other, and an output voltage that is almost independent of temperature will be obtained.

By the way, in the reference voltage generating circuit using such a switched capacitor, the output voltage gradually changes due to the decrease of the charge stored in the capacitor due to leakage or the like, so that a predetermined reference voltage can be stably obtained. Therefore, it is necessary to alternately switch the first operation period T1 and the second operation period T2 in a certain cycle.

[0016]

However, in the reference voltage generation circuit shown in FIG. 5, the second unit Y2 is different from the first operation period T1 in which the output of the first unit Y1 and the ground potential are sampled. Operation period T in which the reference voltage is sampled and the reference voltage is output as an output after the arithmetic processing
2, two operation periods are required, and in the first operation period T1, the output voltage of the reference voltage generation circuit has a value different from a predetermined reference voltage value. Therefore,
When the operating frequency of the load circuit is increased and the frequency of the connection between the reference voltage generating circuit and the load is also increased, the problem that the presence of the first operation period T1 hinders the increase in the frequency is considered. Have.

As one method of solving such a problem, the output Vo of the second unit Y2 of the reference voltage generating circuit shown in FIG.
A method is conceivable in which the sample / hold circuit shown in FIG. 4 is modified and connected to Vo2 so as to correspond to a full differential amplifier. The sample / hold circuit shown in FIG.
As described above, when a constant input voltage is given in the sample mode, the same voltage is considered to be output in both the sample mode and the hold mode.
By utilizing this feature, it is possible to use the output voltage not only in the hold mode but also in the sample mode, and it is considered that the output and the load can be connected at a high frequency.

However, a detailed study of the operation of this circuit from such a viewpoint reveals that there are the following problems. First, the sample / hold circuit is a switched-capacitor circuit, and is susceptible to the influence of floating capacity of wiring, switches, and the like. That is, the output voltage value is slightly different between the sample mode and the hold mode due to the difference in the operation / connection state of the switch between the sample mode and the hold mode.

Second, because the circuit state is different between the sample mode and the hold mode, when the sample / hold circuit and the load circuit are electrically connected in each state, the sample / hold circuit The difference is that the settling characteristic at which the change in the output voltage value returns to the predetermined voltage is different between the sample mode and the hold mode. This becomes remarkable especially when the load to be connected is large, and causes a problem.

In view of the above problems, the present invention provides a sample / hold circuit capable of maintaining the same output voltage / characteristic in a sample mode and a hold mode, and further provides the sample / hold circuit. An object of the present invention is to provide a reference voltage generating circuit which has stable output voltage characteristics and can be connected to a load at a high frequency.

[0021]

According to the present invention, there is provided a sample / hold circuit comprising: an operational amplifier having an input terminal and an output terminal; a first capacitor connected between an input terminal and an output terminal of the operational amplifier; A first switch capable of selecting an input terminal of the operational amplifier and a first voltage terminal to which a voltage serving as a reference of the operation of the input terminal is supplied; and an output terminal of the operational amplifier and a signal voltage input terminal capable of being selected. A second switch, a second capacitor connected between the first switch and the second switch, an input terminal of the operational amplifier, and a voltage serving as a reference for operation of the input terminal. A third switch for selecting a terminal on a side different from the first switch, and selecting an output terminal of the operational amplifier and the signal voltage input terminal. A fourth switch for selecting a terminal on a side different from the second switch; and a capacitor connected between the third switch and the fourth switch having the same capacitance as the second capacitor. And a third capacitor having:

Further, a sample / hold circuit according to the present invention comprises: a full differential amplifier having first and second two input terminals and first and second two output terminals; A first capacitor connected between a first input terminal and a first output terminal of the full differential amplifier;
Input terminal and a first input terminal serving as a reference for the operation of the first input terminal.
And a second switch capable of selecting a first output terminal and a first signal voltage input terminal of the full differential amplifier. , A second capacitor connected between the first switch and the second switch, a first input terminal of the full differential amplifier, and operation of the first input terminal. A third switch for selecting a first voltage terminal to which a first voltage serving as a reference is supplied, and selecting a terminal on a side different from the first switch; A fourth switch for selecting a first output terminal of the amplifier and the first signal voltage input terminal, the fourth switch selecting a terminal different from the second switch, and the third switch The same capacitance as the second capacitor connected between the fourth switch A third capacitor, a fourth capacitor connected between a second input terminal and a second output terminal of the full differential amplifier, and a second input terminal of the full differential amplifier. A fifth switch capable of selecting between a first voltage terminal to which a first voltage serving as a reference of the operation of the second input terminal is supplied, and a second output terminal of the full differential amplifier A sixth switch capable of selecting a second signal voltage input terminal and a second signal voltage input terminal; a fifth capacitor connected between the fifth switch and the sixth switch; 2 terminal and a first voltage terminal to which a first voltage serving as a reference for operation of the second input terminal is supplied, and which is different from the fifth switch. And a second output terminal of the full differential amplifier and a seventh switch for selecting An eighth switch that can select a second signal voltage input terminal and selects a terminal on a side different from the sixth switch, and is connected between the seventh switch and the eighth switch; And a sixth capacitor having the same capacitance as the fifth capacitor, so as to constitute a full differential amplifier (having first and second input terminals and first and second output terminals). be able to.

Further, the reference voltage generating circuit according to the present invention is a reference voltage generating circuit for generating one or more voltages that are stable against a change in ambient temperature with reference to the first voltage,
The reference voltage generation circuit has at least two circuit blocks, each of the circuit blocks including at least one switched capacitor element to which a switched capacitor is connected, and the first circuit block has a first clock. Has at least two operation periods of a first operation period and a second operation period, and the second circuit block has a third operation period and a fourth operation period driven by a second clock And the first operation period
Is driven by the first clock,
A circuit block for generating and outputting a predetermined reference voltage during the second operation period, wherein the second circuit block comprises:
The predetermined reference voltage output during the second operation period of the first circuit block is sampled by driving by the second clock, and the predetermined reference voltage is sampled during both of the third and fourth operation periods. It is a circuit block that outputs a predetermined reference voltage, and the second circuit block includes the sample / hold circuit, whereby a stable reference voltage that is almost independent of temperature can be obtained.

Further, the reference voltage generating circuit of the present invention has a first
A reference voltage generating circuit that generates a second voltage that is stable with respect to fluctuations in ambient temperature based on the voltage of the first circuit block, wherein the first circuit block includes at least a third voltage , A first unit for generating two voltages of a fourth voltage, and calculating the third voltage and the fourth voltage.
A second unit that amplifies to generate the second voltage;
And a second circuit block, at least between the second unit and a load for supplying the second voltage, for stabilizing the second voltage to be supplied. Wherein the second unit has a first operational amplifier having a first input terminal and a first output terminal, and a first operational amplifier for generating the third voltage of the first unit.
A first switch selectable between a first terminal and a ground terminal; a first capacitor connected between the first switch and a first input terminal of the first operational amplifier; A second switch capable of selecting a first terminal of the unit generating the third voltage and a second terminal of the first unit generating the fourth voltage; 2 switch and a second capacitor connected between a first input terminal of the first operational amplifier, and the second unit includes at least a first capacitor of the first operational amplifier. A third switch capable of selecting an output terminal of the first amplifier and a first voltage terminal for supplying the first voltage, and a third switch connected between the third switch and a first input terminal of the first operational amplifier. A third capacitor, wherein the third unit comprises a second capacitor. A second operational amplifier having a power terminal and a second output terminal; a fourth capacitor connected between a second input terminal and a second output terminal of the second operational amplifier; A fourth switch capable of selecting a second input terminal of the operational amplifier and a second voltage terminal to which a fifth voltage serving as a reference for operation of the second input terminal is supplied; A second output terminal of the operational amplifier and the first output terminal;
A fifth switch capable of selecting a first output terminal of the operational amplifier, a fifth capacitor connected between the fourth switch and the fifth switch, and a second switch of the second operational amplifier. And a second voltage terminal to which a fifth voltage serving as a reference for the operation of the second input terminal is supplied, and a terminal on a side different from the fourth switch can be selected. A sixth switch to be selected, a second output terminal of the second operational amplifier, and a first output terminal of the first operational amplifier, the terminal being different from the fifth switch. And a sixth capacitor connected between the seventh switch and the sixth switch, the sixth capacitor having the same capacitance as the fifth capacitor. Significantly higher frequency of circuit and load connections It is possible to become.

Further, the reference voltage generating circuit of the present invention
A first operation period of length t1 in which the third switch selects a first voltage terminal for supplying the first voltage, and a third operation period in which the third switch selects the first voltage terminal. Has a second operation period of a length t2 for selecting the terminal on the opposite side, and the first operation period and the second operation period are alternately repeated. A unit for generating the second voltage at one output terminal, wherein the length t1 of the first operation period and the length t2 of the second operation period have a relationship of t1 <t2, Third
The fourth switch selects a second input terminal of the second operational amplifier, the fifth switch selects a second output terminal of the second operational amplifier, and the sixth switch selects the second output terminal of the second operational amplifier. The second switch is supplied with a fifth voltage which is a reference for the operation of the second input terminal of the second operational amplifier.
, And the seventh switch selects the first output terminal of the first operational amplifier.
Operation period, and the fourth to seventh switches are respectively connected to the third
To select the terminal on the opposite side to the operation period of the fourth
The third operation period and the fourth operation period are alternately repeated so that the second output terminal is connected to the second output terminal in each of the third and fourth operation periods. Wherein the length of the first operation period t1, the length of the third operation period t3, and the length of the fourth operation period t4 are t1 <t3 t1 <t4 With this relationship, the frequency of the connection between the reference voltage generating circuit and the load can be greatly increased.

Further, the reference voltage generating circuit of the present invention
A second voltage having a voltage difference substantially equal to the + side and the − side with respect to the voltage of
A reference voltage generating circuit for generating two voltages of a third voltage, wherein the first circuit block generates at least two voltages of a fourth voltage and a fifth voltage in the reference voltage generating circuit. A second unit for calculating and amplifying the fourth voltage and the fifth voltage to generate the second voltage and the third voltage; and a second circuit for generating the second voltage and the third voltage. A block comprising at least the second unit and the second voltage;
A third unit for stabilizing the second voltage to be supplied and the third voltage between the load for supplying the third voltage and the second unit; 2 of 2
A first fully differential amplifier having one input terminal and first and second two output terminals, a first terminal of the first unit for generating the fourth voltage, and a ground terminal; A first switch capable of selecting the first switch, the first switch and the first switch.
A first capacitor connected between the first input terminal of the full differential amplifier and the fourth unit of the first unit.
A second terminal capable of selecting a first terminal for generating the first voltage and a second terminal for generating the fifth voltage of the first unit; and A second capacitor connected between the first input terminal of the first full differential amplifier, a first terminal of the first unit for generating the fourth voltage, and a ground terminal And a third capacitor connected between the third switch and a second input terminal of the first full differential amplifier; and a first switch connected between the third switch and the first unit. A fourth switch capable of selecting a first terminal generating the fourth voltage of the first unit and a second terminal generating the fifth voltage of the first unit; Connected between the first switch and the first input terminal of the first full differential amplifier.
And the second unit selects at least a first output terminal of the first full differential amplifier and a first voltage terminal for supplying the first voltage. A possible fifth switch, a fifth capacitor connected between the fifth switch and a first input terminal of the first full differential amplifier, and a first full differential type A sixth switch capable of selecting a second output terminal of the amplifier and a first voltage terminal for supplying the first voltage, and a second switch of the sixth switch and the first full differential amplifier; A third capacitor connected between the third unit and the third input terminal and a third and fourth output terminal. A second full differential amplifier, and a third input terminal and a third output terminal of the second full differential amplifier. , A third capacitor connected to the third input terminal of the second full differential amplifier, and a second voltage supplied as a reference for operation of the third input terminal. A seventh switch capable of selecting a voltage terminal; an eighth switch capable of selecting a third output terminal of the second full differential amplifier and a first output terminal of the first full differential amplifier; Switch, an eighth capacitor connected between the seventh switch and the eighth switch, a third input terminal of the second full differential amplifier, and the third input terminal A ninth switch that is capable of selecting a second voltage terminal to which a sixth voltage serving as a reference for the operation is supplied, and that selects a terminal on a side different from the seventh switch;
A third output terminal of the second full differential amplifier and a first output terminal of the first full differential amplifier can be selected, and a terminal on the side different from the eighth switch is selected. A tenth switch to select, the ninth switch and the first
And a ninth capacitor connected between the second full differential amplifier and a fourth output terminal of the second full differential amplifier. A connected tenth capacitor, a fourth input terminal of the second full differential amplifier, and a second voltage to which a sixth voltage serving as a reference for operation of the fourth input terminal is supplied. An eleventh switch capable of selecting a terminal; a twelfth switch capable of selecting a fourth output terminal of the second full differential amplifier and a second output terminal of the first full differential amplifier. A switch, an eleventh capacitor connected between the eleventh switch and the twelfth switch, a fourth input terminal of the second full differential amplifier, and a fourth input terminal of the fourth input terminal. A second voltage terminal to which a sixth voltage serving as an operation reference is supplied can be selected. Thus, a thirteenth switch for selecting a terminal on a side different from the eleventh switch, a fourth output terminal of the second full differential amplifier, and a fourth output terminal of the first full differential amplifier 2 output terminals can be selected,
A fourteenth switch for selecting a terminal on a side different from the twelfth switch, the thirteenth switch and the fourteenth switch.
And a twelfth capacitor having the same capacitance as the eleventh capacitor, which is connected between the first and second switches.
It is possible to obtain a stable reference voltage that is almost independent of temperature with a fully differential amplifier.

Further, the reference voltage generating circuit of the present invention
Units select the first voltage terminal from which the fifth switch supplies the first voltage, and the sixth switch selects the first voltage terminal from which the first voltage is supplied. A first operation period having a length t1 and a second operation period having a length t2 in which the fifth and sixth switches each select a terminal on the opposite side to the first operation period; By alternately repeating the first operation period and the second operation period, in the second operation period, the second voltage is applied to the first output terminal, and the third voltage is applied to the second output terminal. A unit for generating a voltage, the length t of the first operation period
1 and the length t2 of the second operation period are in a relationship of t1 <t2, and the third unit is configured such that the seventh switch is connected to a third input terminal of the second full differential amplifier. And the eighth switch selects a third output terminal of the second full differential amplifier, and the ninth switch selects a third input terminal of the second full differential amplifier. Selecting a second voltage terminal to which a sixth voltage serving as a reference for the operation is supplied, the tenth switch selecting a first output terminal of the first full differential amplifier, An eleventh switch selects a fourth input terminal of the second full differential amplifier, a twelfth switch selects a fourth output terminal of the second full differential amplifier, A thirteenth switch serves as a reference for operation of a fourth input terminal of the second full differential amplifier. Selects the second voltage terminal pressure is supplied, the third length t3 of the fourteenth switch selects the second output terminal of said first full differential amplifier
And a fourth operation period of length t4 in which each of the seventh to fourteenth switches selects a terminal on the opposite side to the third operation period, and the third operation period And the fourth operation period are alternately repeated, whereby the third and
A unit for generating the second voltage at the third output terminal and the third voltage at the fourth output terminal during each of the fourth operation periods, wherein the unit generates the second voltage at the third output terminal; T1 and the length t3 of the third operation period and the fourth
Since the length of the operation period t4 is in the relationship of t1 <t3 t1 <t4, it is possible to use a fully differential amplifier to greatly increase the frequency of connection between the reference voltage generation circuit and the load. Becomes

Further, the reference voltage generating circuit of the present invention
Switching from the third operation period to the fourth operation period, and from the fourth operation period to the third operation period.
Is switched to the operation period of the first circuit block of the second circuit block.
The operation is performed during the operation period, so that a constant output voltage / output characteristic can be obtained almost continuously.

The reference voltage generating circuit according to the present invention switches the first operation period to the second operation period when the first operation period is switched to the second operation period.
With respect to the fluctuation width occurring with respect to the output terminal voltage of the circuit block of the first circuit block, the first voltage and a predetermined voltage which is a value at which the voltage of the output terminal of the first circuit block has reached a steady value during the second operation period. When the allowable error with respect to the difference from the reference voltage is X, in the first circuit block, when the period is switched from the first operation period to the second operation period, the output terminal of the first circuit block is The longer time it takes for the fluctuation width of the resulting output voltage to settle below the tolerance X is t
In the second circuit block, switching from the third operation period to the fourth operation period and switching from the fourth operation period to the third operation period are performed in the second circuit block.
Is performed within the operation period of the first circuit block and after the lapse of the time t0 or more after the switching from the first operation period to the second operation period in the first circuit block, so that the output voltage is more constant. / Output characteristics can be obtained.

In the reference voltage generating circuit of the present invention, when the switching period of the operation period of the first circuit block is F1 and the switching period of the operation period of the second circuit block is F2, K is an integer and K is an integer. Since * F1 = F2, a constant output voltage / output characteristic can be obtained almost continuously.

In the reference voltage generating circuit according to the present invention, the frequency of the second clock for driving the second circuit block is set to f2, and the circuit serving as the load of the reference voltage generating circuit is electrically connected to the second circuit block. When the frequency to be connected is fload, the noise given to the analog circuit using the reference voltage from the reference voltage generation circuit can be suppressed because fload ≧ f2. The reference voltage generation circuit according to the present invention can supply a stable reference voltage even to a large load because a plurality of second circuit blocks are formed for one first circuit block. Becomes

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the drawings. [Embodiment 1] FIG. 1 is a circuit diagram of a sample / hold circuit according to a first embodiment of the present invention.

In the present embodiment, the first input terminal Via, the second input terminal Vib connected to the ground potential, and the output terminal Vo
And an operational amplifier AMP-a having
A first capacitor Ca connected between a first input terminal Via and an output terminal Vo of the operational amplifier AMP-a
A first switch SW capable of selecting a first input terminal Via and a ground potential serving as a reference for operation of the first input terminal Via
-a, a second switch SW-b capable of selecting an output terminal Vo and a signal input terminal Vin of the operational amplifier AMP-a, a second capacitor Cb, and a first switch of the operational amplifier AMP-a.
And a third switch SW for selecting a terminal on the side different from the first switch SW-a, which can select an input terminal Via and a ground potential serving as a reference for the operation of the first input terminal Via. -c, and a fourth switch SW-d which can select the output terminal Vo and the signal input terminal Vin of the operational amplifier AMP-a and selects a terminal different from the second switch SW-b. And a third capacitor Cc connected between the fourth switch SW-d and the third switch SW-c and having the same capacitance as the second capacitor Cb.

The operation of this circuit is as follows. First, as described above, the voltage of the signal input terminal Vin is changed to the second voltage in the sample mode.
Is sampled by the capacitor Cb. At this time, one terminal of the second capacitor Cb is connected to the first output terminal Vo of the operational amplifier AMP-a by the second switch SW-b. The other terminal of the second capacitor Cb is connected by a first switch SW-a to a ground potential serving as a reference for the operation of the first input terminal Via of the operational amplifier AMP-a. At this time, both ends of the third capacitor Cc are connected to the third and fourth capacitors Cc.
Are connected to the first input terminal Via and the output terminal Vo of the operational amplifier AMP-a by switches SW-c and SW-d, respectively.

Next, when the first to fourth switches are switched from the sample mode to the state in which the first to fourth switches select terminals on the opposite side to the sample mode, and the apparatus enters the hold mode, the second capacitor Cb and Third capacitor C
c is replaced with the sample mode state, and the operation state of the circuit is basically the same as the sample mode.

Therefore, the same operation state / characteristic is ensured in the sample mode and the hold mode.
Therefore, when a constant voltage is supplied to the signal input terminal Vin in the sample mode, the sample mode and the hold mode are completely equivalent, and the same output voltage / output characteristics can be obtained.

[Second Embodiment] FIG. 2 is a circuit diagram of a sample / hold circuit according to a second embodiment of the present invention. The sample / hold circuit according to the present embodiment is a circuit obtained by expanding the sample / hold circuit according to the first embodiment so as to correspond to a fully differential input / output. -b, and a circuit equivalent to the sample / hold circuit of the first embodiment is formed for each of the two input terminals Vin-p and Vin-n constituting the differential input. .

In the operation, the circuit connected to each of the two input terminals Vin-p and Vin-n constituting the differential input performs the same operation as the sample / hold circuit of the first embodiment. The operation principle of this circuit is applied in the following third embodiment, and the details will be described in the third embodiment.

[Third Embodiment] FIG. 3 is a circuit diagram of a reference voltage generating circuit according to a third embodiment of the present invention.
In this embodiment, the first unit Y
The first and second units Y2 have the same configuration as the conventional example of FIG. Therefore, a detailed description of the configuration here is omitted. However, the first unit Y1 and the second unit Y2 only need to operate basically the same as the circuit of FIG. 5, and both the first unit Y1 and the second unit Y2 are limited to this circuit. It is not something to be done.

The third unit Y3 of the present embodiment is a circuit to which the circuit of the second embodiment is applied. The third and fourth input terminals Vi3 and Vi4 and the third and fourth output terminals Vo3. , V
o4, a second full differential amplifier AMP2,
A third capacitor C7 connected between the third input terminal Vi3 and the third output terminal Vo3 of the full differential amplifier AMP2, and a third input terminal of the second full differential amplifier AMP2. A second voltage terminal TD to which a sixth voltage VB2 serving as a reference for operation of the terminal Vi3 and the third input terminal Vi3 is supplied.
7, a third switch SW7 capable of selecting the second full differential amplifier AMP2, a third output terminal Vo3 of the second full differential amplifier AMP2, and a first output terminal Vo1 of the first full differential amplifier AMP1.
Switch SW8, an eighth capacitor C8 connected between the eighth switch SW8 and the seventh switch SW7, and a third switch of the second full differential amplifier AMP2. Input terminal Vi3 and the third input terminal Vi3
And a ninth switch SW9 for selecting a second voltage terminal TD2 to which a sixth voltage VB2 serving as a reference of the operation is supplied, and for selecting a terminal on a side different from the seventh switch SW7. And the second full differential amplifier AMP2
The third output terminal Vo3 and the first full differential amplifier A
A tenth switch SW10 for selecting a first output terminal Vo1 of MP1 and selecting a terminal on a side different from the eighth switch SW8;
Ninth capacitor C9 connected between the zeroth and ninth switches SW9 and having the same capacitance as the eighth capacitor C8
And a first terminal connected between a fourth input terminal Vi4 and a fourth output terminal Vo4 of the second full differential amplifier AMP2.
0 capacitor C10, the fourth input terminal Vi4 of the second full differential amplifier AMP2, and the fourth input terminal Vi4.
Eleventh switch S that can select a second voltage terminal TD2 to which a sixth voltage VB2 serving as a reference for the operation of
W11 and the fourth of the second full differential amplifier AMP2.
Output terminal Vo4 and the first full differential amplifier AMP1
Twelfth switch S capable of selecting the second output terminal Vo2
W12, an eleventh capacitor C11 connected between the twelfth switch SW12 and the eleventh switch SW11, and a fourth one of the second full differential amplifier AMP2.
Input terminal Vi4 and a second voltage terminal T to which a sixth voltage VB2 serving as a reference for operation of the fourth input terminal Vi4 is supplied.
D2 and the eleventh switch SW
Thirteenth switch S for selecting a terminal on the side different from 11
W13 and the fourth of the second full differential amplifier AMP2.
Output terminal Vo4 and the first full differential amplifier AMP1
Of the second output terminal Vo2 can be selected.
To select a terminal on the side different from the switch SW12
4th switch SW14 and the fourteenth switch SW14
And the thirteenth switch SW13.
And a twelfth capacitor C12 having the same capacitance as the first capacitor C11.

Next, the operation of this embodiment will be described. Note that the operations of the first unit Y1 and the second unit Y2 are the same as those of the conventional example, and therefore, the overlapping description will be briefly shown. (Also, for the sake of simplicity of description, only the operation of generating one of two output voltages generated by this circuit is shown.)
The clock timing CLK1 corresponding to the driving of each switch of the first unit Y1 and the second unit Y2 and the two clock timings CLK2-1 and CLK2-2 corresponding to the driving of each switch of the third unit Y3. The outline of the timing is shown.

First, in the first unit Y1, two bipolar transistors Q1, Q2 having different emitter areas are used.
By controlling so that a current approximately equal to
The voltages V1, V2 are applied to their emitters E1, E2, respectively.
Occurs. Due to the nature of the emitter-base voltage of the bipolar transistor, the emitter voltage V1 of the first bipolar transistor Q1 and the emitter voltage V2 of the second bipolar transistor Q2 are approximately 2 m with temperature.
It decreases at V / ° C. (the voltage value and the rate of change are slightly different between V1 and V2). On the other hand, the difference between the emitter voltages of the two bipolar transistors Q1 and Q2 (V1-V
2) is about 0.198 mV / ° C. (however, A2 / A1
-10).

The voltage V generated in the first unit Y1
1 and V2, the second unit Y2 first
During the first operation period T1 indicated by CLK1, the first and second capacitors C1 and C2 are both (VR1 + Vos1 / 2) -V
It is charged to a voltage of 1. At this time, the fifth capacitor C5
Is charged to a voltage of (VR1 + Vos1 / 2) -Vcm. The first output terminal Vo1 is connected to the first input terminal Vi1 via the fifth switch SW5, and the voltage thereof is
VR1 + Vos1 / 2, the same as the input terminal Vi1.

Next, when the selection of the first, second, fifth, and fifteenth switches is switched to enter a second operation period T2, the first and second capacitors C1 and C2 are switched to the first and second capacitors, respectively. , And the second switches SW1 and SW2 are connected to the ground potential and the second terminal T2 which is the emitter voltage V2 of the second bipolar transistor Q2, respectively. At this time, the voltage of the first input terminal Vi1 of the full differential amplifier AMP1 keeps the same VR1 + Vos1 / 2 as in the first operation period T1. At this time, the terminal of the fifth capacitor C5 on the side opposite to the first input terminal Vi1 of the full differential amplifier AMP1 is connected to the first output terminal Vo1 of the full differential amplifier AMP1. .

Here, during the first operation period T1 and the second operation period T2, the charge of the node connected to the first input terminal Vi1 of the full differential amplifier AMP1 is preserved, so that the second differential amplifier AMP1 has the second operational period. When the voltage Vout11 of the output terminal Vo1 is obtained, the above equation (1) is obtained. This value is the capacitance Cx1 and Cx2
By appropriately selecting the ratio Cx2 / Cx1, a stable value almost independent of temperature can be obtained. That is, a reference voltage is obtained.

Here, in the first operation period T1, the voltage V1, V2 or the ground potential is sampled into each of the first to fourth capacitors. This is because the capacitance of the first to fourth capacitors is very small. Since the operation is completed in a short time, by selecting an appropriate operation cycle, the ratio (duty ratio) of the first operation period T1 in the clock cycle is smaller than 50% as shown in the timing chart of CLK1 in FIG. It is possible to

Then, in the second operation period T2, immediately after the switching from the first operation period T1, the second unit Y
The outputs Vo1 and Vo2 output a certain amount of fluctuation due to the charging and discharging of the capacitor, but the load in this case is sufficiently small and the voltage value is quickly stabilized to a predetermined reference voltage value.

In the third unit Y3, first, when the output of the second unit is stabilized at the predetermined reference voltage value in the second operation period T2 as described above, the voltage is changed to the eighth voltage.
Is sampled on the capacitor C8 of At this time, one terminal of the eighth capacitor C8 is connected to the first output terminal Vo1 of the first full differential amplifier AMP1 by the eighth switch SW8. The other terminal of the eighth capacitor C8 is supplied with a sixth voltage VB2 serving as a reference for the operation of the third input terminal Vi3 of the second full differential amplifier AMP2 by a seventh switch SW7. Voltage terminal TD2
Connected to. At this time, both ends of the ninth capacitor C9 are connected to the third input terminal Vi3 and the third output terminal Vo3 of the second full differential amplifier AMP2 by the ninth and tenth switches SW9 and SW10. ing. Such a connected state period is referred to as a third operation period T3.

From the third operation period T3 to the seventh to tenth operations
Are switched to a state of selecting a terminal on the opposite side to the third operation period T3 (this is called a fourth operation period T4), the above-described eighth capacitor C8 and ninth capacitor
And the capacitor C9 is replaced with the third operation period T3, and the operation state of the circuit is basically the same as the third operation period T3. Therefore, almost the same operation state / characteristics are ensured in the third operation period T3 and the fourth operation period T4.

By the repetition of the third operation period T3 and the fourth operation period T4, the third input terminal Vi3 of the second full differential amplifier AMP2 becomes the sixth reference terminal for its operation. The voltage VB2 is charged to the third output terminal Vo3 of the first full differential amplifier AMP1.
Is charged to the output voltage Vout11 of the output terminal Vo1, ie, a predetermined reference voltage value. As a result, a predetermined reference voltage value is obtained as the voltage Vout21 of the third output terminal of the third unit Y3.

Here, in order to obtain exactly the same output voltage value in the third operation period T3 and the fourth operation period T4, the first output of the first full differential amplifier AMP1 is controlled by the eighth capacitor C8. The same voltage value is sampled when the output voltage Vout11 of the terminal Vo1 is sampled and when the output voltage Vout11 of the first output terminal Vo1 of the first full differential amplifier AMP1 is sampled by the ninth capacitor C9. It is necessary to perform the sampling if the output voltage Vout11 of the first output terminal Vo1 of the first full differential amplifier AMP1 is sufficiently settled in the second operation period T2 of the second unit. The third operation period T3 and the fourth operation period
In the operation period T4, the output voltage difference is almost negligible, and a constant output voltage / output characteristic can be obtained almost continuously. As described above, the output voltage Vout11 of the first output terminal Vo1 of the first full differential amplifier AMP1 is always in the second operation period T2 of the second unit.
In order for the sampling to be performed in a state where is sufficiently settled, the operating cycle F1 of the second unit Y2 and the operating cycle F2 of the third unit Y3 are determined by K *
It is necessary that F1 = F2.

As such a drive timing, as shown by CLK2-1 in FIG. 6, the same second operation period T
2 within the third operation period T3 → the fourth operation period T4, the fourth operation period
The method of switching both the operation period T4 and the third operation period T3, and the third operation period T3 and the fourth operation period in one second operation period T2 as shown by CLK2-2 in FIG. Switching of the operation period T4 is performed, and another second operation period T2 is performed.
Then, there is a method of switching from the fourth operation period T4 to the third operation period T3. In particular, the switching from the third operation period T3 to the fourth operation period T4 and the switching from the next fourth operation period T4 to the third operation period T3 are performed in another second operation period like CLK2-2. , The third operation period T3 and the fourth operation period T4 are completely equivalent operations.

In each case, as described above, C
The ratio (duty ratio) of the first operation period T1 to the clock cycle of LK1 is made smaller than 50%, and the duty ratio of the third operation period T3 and the fourth operation period T4 of the third unit Y3 is changed. By not making it extremely close to either, the third unit Y3
Completing the sampling of the second unit output voltage (reference voltage) during the third or fourth one operation period,
Does not affect the output of the unit Y3.

Under the above conditions, the third operation period T3 and the fourth operation period T4 can have almost the same circuit state / characteristics, and the switching between the operation periods is completed in a very short time. Therefore, the frequency of connection between the reference voltage generating circuit and the load can be significantly increased as compared with the conventional example.

As described above, in the first embodiment, for the sake of simplicity, the first unit Y1 and the second unit Y2 have been described using the same units as those in the conventional example shown in FIG. However, these may be circuits having the functions described above, and are not limited to the circuits shown in FIG. For example, for the second unit Y2, using a switched capacitor circuit as in the third unit Y3,
An appropriate reference voltage may be applied to the two input terminals Vi1 and Vi2.

The ratio Cx2 / Cx1 of the capacitors Cx1 and Cx2 is a value to be appropriately selected according to the characteristics of the bipolar transistors Q1 and Q2, and is not limited to the value "10" as described above. The third embodiment is described above.
Described the full differential type reference voltage generation circuit,
It goes without saying that the same concept can be applied to a single output type reference voltage generating circuit.

[Embodiment 4] FIG. 7 shows a configuration diagram of a fourth embodiment of the present invention. In the third embodiment, the first,
Although the second and third units are configured one by one, in the present embodiment, a plurality of third units Y3 are arranged in parallel with each of the first and second units Y1 and Y2. It is connected to the second unit Y2. Each of the first, second, and third units Y1, Y2, and Y3 can be basically the same as in the first embodiment. According to this embodiment, a stable reference voltage can be supplied even to a larger load than in the second embodiment.

[0058]

As described above, according to the present invention,
A sample / hold circuit for applying a DC or very low frequency reference voltage to a load, in which the sample mode and the hold mode operate completely equivalently, and have almost the same output voltage / output characteristics as a DC Can be provided.

Further, by applying this sample / hold circuit to a reference voltage generation circuit using a switched capacitor, it is possible to greatly increase the frequency of connection between the reference voltage generation circuit and the load as compared with the conventional example. It is possible to provide a reference voltage generation circuit. In such a reference voltage generating circuit, a plurality of driving stages (third
By providing the unit Y3), it becomes easy to obtain a predetermined reference voltage and a good settling characteristic for a large load.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram according to a second embodiment of the present invention.

FIG. 3 is a circuit configuration diagram according to a third embodiment of the present invention.

FIG. 4 is a circuit configuration diagram of a conventional sample / hold circuit.

FIG. 5 is a circuit configuration diagram of a conventional reference voltage generation circuit.

FIG. 6 is a diagram illustrating a timing example of a driving clock according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of a fourth embodiment of the present invention.

[Explanation of symbols]

 Vin-p: First signal input terminal Vin-n: Second signal input terminal Vi-a: First input terminal of full differential amplifier AMP-b Vi-b: Full differential amplifier AMP-b The second input terminal Vo-a: the first output terminal of the full differential amplifier AMP-b Vo-b: the second output terminal of the full differential amplifier AMP-b Ca1: the first capacitor Ca2: Fourth capacitor Cb1: Second capacitor Cb2: Fifth capacitor Cc1: Third capacitor Cc2: Sixth capacitor SW-a1: First switch SW-b1: Second switch SW-c1: Third capacitor SW-d1: Fourth switch SW-a2: Fifth switch SW-b2: Sixth switch SW-c2: Seventh switch SW-d2: Eighth switch TD2: First voltage supply terminal B1: First circuit block B2: Second circuit block

Claims (12)

[Claims] An operational amplifier having an input terminal and an output terminal; a first capacitor connected between an input terminal and an output terminal of the operational amplifier; an input terminal of the operational amplifier and a reference for operation of the input terminal; A first switch capable of selecting a first voltage terminal to which a given voltage is supplied; a second switch capable of selecting an output terminal of the operational amplifier and a signal voltage input terminal;
A second capacitor connected between the first switch and the second switch, an input terminal of the operational amplifier, and a first voltage terminal to which a reference voltage for operation of the input terminal is supplied. A third switch for selecting a terminal on a side different from the first switch, and an output terminal of the operational amplifier and the signal voltage input terminal for selecting the second switch. A fourth switch for selecting a terminal on a different side, and a third switch connected between the third switch and the fourth switch and having the same capacitance as the second capacitor.
A sample / hold circuit, comprising: a capacitor; 2. A full differential amplifier having first and second two input terminals and first and second two output terminals, a first input terminal of the full differential amplifier and a first A first capacitor connected between the first input terminal and the first input terminal of the full differential amplifier, and a first voltage which is a reference for operation of the first input terminal. A first switch capable of selecting a first voltage terminal; a second switch capable of selecting a first output terminal and a first signal voltage input terminal of the full differential amplifier; A second capacitor connected between the first switch and the second switch; a first input terminal of the full differential amplifier; and a first voltage serving as a reference for operation of the first input terminal. And a first voltage terminal to which the first switch is supplied, and a terminal on a side different from the first switch. And a first output terminal and a first signal voltage input terminal of the full differential amplifier, and a terminal on a side different from the second switch can be selected. A fourth switch to be selected, a third capacitor connected between the third switch and the fourth switch, the third capacitor having the same capacitance as the second capacitor, and a second capacitor of the full differential amplifier. A fourth capacitor connected between the input terminal and the second output terminal of the full differential amplifier; a second input terminal of the full differential amplifier; and a first capacitor serving as a reference for operation of the second input terminal. A fifth switch capable of selecting a first voltage terminal to which a voltage is supplied, and a sixth switch capable of selecting a second output terminal and a second signal voltage input terminal of the full differential amplifier Connected between the fifth switch and the sixth switch. A fifth capacitor, a second input terminal of the full differential amplifier, and a first voltage terminal to which a first voltage serving as a reference for operation of the second input terminal is supplied. Wherein a seventh switch for selecting a terminal on a side different from the fifth switch, and a second output terminal and a second signal voltage input terminal of the full differential amplifier can be selected. An eighth switch for selecting a terminal on a side different from the sixth switch, and a sixth switch connected between the seventh switch and the eighth switch and having the same capacitance as the fifth capacitor. A sample / hold circuit, comprising: a capacitor; 3. A reference voltage generating circuit for generating one or more voltages stable with respect to fluctuations in ambient temperature based on a first voltage, wherein each of the circuit blocks includes It has at least two circuit blocks including at least one switched capacitor element to which a switched capacitor is connected, the first circuit block having a first operation period driven by a first clock and a second operation block. The second circuit block has two operation periods of a third operation period and a fourth operation period driven by a second clock, and the first circuit block has at least two operation periods of the first operation period. Is a circuit block that generates and outputs a predetermined reference voltage during the second operation period by driving with a first clock, wherein the second circuit block is The predetermined reference voltage output during the second operation period of the first circuit block is sampled by driving by the second clock, and the predetermined reference voltage is sampled during both of the third and fourth operation periods. 3. A reference voltage generating circuit that outputs a predetermined reference voltage, wherein the second circuit block includes the sample / hold circuit according to claim 1 or 2. 4. A reference voltage generating circuit that generates a second voltage that is stable with respect to fluctuations in ambient temperature based on a first voltage, wherein the first circuit block includes a first circuit block. Generating at least two voltages, a third voltage and a fourth voltage.
And a second unit for calculating and amplifying the third voltage and the fourth voltage to generate the second voltage, wherein the second circuit block comprises at least the second And a third unit for stabilizing a second voltage to be supplied between the first unit and the load for supplying the second voltage, wherein the second unit has a first input terminal. A first operational amplifier having a first output terminal and a first output terminal; a first switch capable of selecting a first terminal for generating the third voltage of the first unit and a ground terminal;
A first capacitor connected between the first switch and a first input terminal of the first operational amplifier; a first terminal of the first unit for generating the third voltage; A second switch capable of selecting between the first terminal and the second terminal of the first unit that generates the fourth voltage;
A second capacitor connected between the second switch and a first input terminal of the first operational amplifier, further comprising at least a second capacitor of the first operational amplifier. A third switch capable of selecting a first output terminal and a first voltage terminal for supplying the first voltage, between the third switch and a first input terminal of the first operational amplifier; A third capacitor connected to the second operational amplifier having a second input terminal and a second output terminal; and a second operational amplifier having a second input terminal and a second output terminal. A fourth capacitor connected between the input terminal and the second output terminal; a second input terminal of the second operational amplifier; and a fifth voltage serving as a reference for operation of the second input terminal. A fourth switch capable of selecting the supplied second voltage terminal; A second output terminal of the second operational amplifier; a fifth switch capable of selecting a first output terminal of the first operational amplifier; and a fifth switch connected between the fourth switch and the fifth switch. A fifth capacitor, a second input terminal of the second operational amplifier, and a second voltage terminal to which a fifth voltage serving as a reference for operation of the second input terminal is supplied. A sixth switch for selecting a terminal different from the fourth switch; a second output terminal of the second operational amplifier; and a first output terminal of the first operational amplifier. A seventh switch for selecting a terminal on a side different from the fifth switch, and a capacitor connected between the seventh switch and the sixth switch having the same capacitance as the fifth capacitor. And a sixth capacitor having: 4. The reference voltage generating circuit according to claim 3, wherein 5. A second unit comprising: a first operation period having a length of t1 for selecting a first voltage terminal for supplying the first voltage, wherein the third switch selects a first voltage terminal for supplying the first voltage; A second operation period having a length t2 for selecting a terminal on the opposite side to the first operation period, wherein the second operation period is alternately repeated by repeating the first operation period and the second operation period. In the operation period, the unit that generates the second voltage at the first output terminal, wherein the length t1 of the first operation period and the length t2 of the second operation period are t1 < t3, the third unit is such that the fourth switch selects a second input terminal of the second operational amplifier, and the fifth switch is a second output of the second operational amplifier. Select a terminal, wherein the sixth switch is connected to a second terminal of the second operational amplifier. A second voltage terminal to which a fifth voltage serving as a reference of the operation of the input terminal is supplied; and a seventh switch for selecting a first output terminal of the first operational amplifier. A third operation period; and a fourth operation period having a length t4 in which each of the fourth to seventh switches selects a terminal opposite to the third operation period. A unit for generating the second voltage at the second output terminal in each of the third and fourth operation periods by alternately repeating a period and a fourth operation period; The length t1 of the operation period, the length t3 of the third operation period, and the length t4 of the fourth operation period have a relationship of t1 <t3 t1 <t4. Reference voltage generation circuit. 6. A method according to claim 1, further comprising:
A reference voltage generation circuit that generates two voltages, a second voltage and a third voltage, which have substantially equal voltage differences on the sides and are stable against fluctuations in ambient temperature; A first circuit block configured to generate at least two voltages of a fourth voltage and a fifth voltage;
And a second unit that calculates and amplifies the fourth voltage and the fifth voltage to generate the second voltage and the third voltage, and wherein a second circuit block includes: At least a second voltage to be supplied between the second unit and the load that supplies the second voltage and the third voltage;
A third unit for stabilizing a third voltage, wherein the second unit has a first and second two input terminals and a first and a second two output terminals; A full differential amplifier; a first switch capable of selecting a first terminal of the first unit that generates the fourth voltage and a ground terminal;
The first switch and a first switch of the first full differential amplifier
A first capacitor connected between an input terminal of the first unit, a first terminal of the first unit for generating the fourth voltage, and a fifth terminal of the first unit for generating the fifth voltage A second switch that can select a second terminal that is
The second switch and a first switch of the first full differential amplifier;
A second capacitor connected between the input terminal of the first unit and a third switch capable of selecting a first terminal of the first unit that generates the fourth voltage and a ground terminal;
The third switch and a second switch of the first full differential amplifier
A third capacitor connected between an input terminal of the first unit, a first terminal of the first unit for generating the fourth voltage, and a fifth terminal of the first unit for generating the fifth voltage A fourth switch that can select a second terminal that is
The fourth switch and a first switch of the first full differential amplifier
And a fourth capacitor connected between the input terminal of the first full differential amplifier and the first output terminal of the first full differential amplifier. A fifth voltage terminal which can select a first voltage terminal for supplying a voltage;
And a fifth capacitor connected between the fifth switch and a first input terminal of the first full differential amplifier; and a second capacitor of the first full differential amplifier. And a first voltage terminal for supplying the first voltage.
And a sixth capacitor connected between the sixth switch and a second input terminal of the first full differential amplifier, wherein the third unit comprises: A second full differential amplifier having third and fourth two input terminals and third and fourth two output terminals; a third input terminal of the second full differential amplifier and a third A seventh capacitor connected between the second full differential amplifier and a third input terminal of the second full differential amplifier;
A seventh switch capable of selecting a second voltage terminal to which a sixth voltage serving as a reference of operation of the input terminal of the second terminal is supplied;
An eighth switch capable of selecting a third output terminal of the second full differential amplifier and a first output terminal of the first full differential amplifier, the seventh switch and the eighth switch. An eighth capacitor connected between the second full differential amplifier and a third input terminal of the second full differential amplifier;
A second voltage terminal to which a sixth voltage serving as a reference for the operation of the input terminal is supplied, and a ninth switch that selects a terminal on a side different from the seventh switch. A third output terminal of the second full differential amplifier and a first output terminal of the first full differential amplifier, the terminal being different from the eighth switch. And a ninth capacitor connected between the ninth switch and the tenth switch, the ninth capacitor having the same capacitance as the eighth capacitor, and the second full differential type. A tenth capacitor connected between a fourth input terminal and a fourth output terminal of the amplifier; a fourth input terminal of the second full differential amplifier;
An eleventh switch capable of selecting a second voltage terminal to which a sixth voltage serving as a reference for the operation of the input terminal of the second input terminal is supplied; a fourth output terminal of the second full differential amplifier; A twelfth switch capable of selecting a second output terminal of the first full differential amplifier, an eleventh capacitor connected between the eleventh switch and the twelfth switch, A fourth input terminal of the second full differential amplifier and the fourth input terminal;
And a second voltage terminal to which a sixth voltage serving as a reference for the operation of the input terminal is supplied.
A thirteenth switch for selecting a terminal on a side different from the first switch, a fourth output terminal of the second full differential amplifier, and a second output terminal of the first full differential amplifier A fourteenth switch for selecting a terminal on a side different from the twelfth switch, and the same capacitance as the eleventh capacitor connected between the thirteenth switch and the fourteenth switch. The reference voltage generation circuit according to claim 3, further comprising: a twelfth capacitor. 7. A second unit, wherein the fifth switch selects a first voltage terminal for supplying the first voltage, and wherein the sixth switch selects the first voltage terminal.
A first operation period having a length t1 for selecting a first voltage terminal for supplying the first voltage, and a length for each of the fifth and sixth switches to select a terminal opposite to the first operation period. And a second operation period of t2. The first operation period and the second operation period are alternately repeated, so that the second output period is applied to the first output terminal in the second operation period. A unit for generating a voltage and the third voltage at the second output terminal, wherein a relationship between the length t1 of the first operation period and the length t2 of the second operation period is t1 <t2. In the third unit, the seventh switch selects a third input terminal of the second full differential amplifier, and the eighth switch selects the second full differential amplifier. And the ninth switch is the third output terminal of the second full differential amplifier. Selects a second voltage terminal to which a sixth voltage serving as a reference for the operation of the input terminal is supplied, and the tenth switch selects a first output terminal of the first full differential amplifier. The eleventh switch selects a fourth input terminal of the second full differential amplifier, and the twelfth switch selects a fourth output terminal of the second full differential amplifier. The thirteenth switch selects a second voltage terminal to which a sixth voltage serving as a reference for operation of a fourth input terminal of the second full differential amplifier is supplied, In which a third switch selects a second output terminal of the first full differential amplifier, and a third operation period of length t3, and wherein the seventh to fourteenth switches each include the third operation period. A fourth operation period of a length t4 for selecting an opposite terminal, and the third operation period And the fourth operation period are alternately repeated so that in each of the third and fourth operation periods, the third output terminal has the second voltage, and the fourth output terminal has the third voltage. Wherein the length of the first operation period t1, the length of the third operation period t3, and the length of the fourth operation period t4 are t1 <t3 t1 <t4 7. The reference voltage generating circuit according to claim 6, wherein: 8. In the second circuit block, switching from the third operation period to the fourth operation period and the fourth operation period are performed.
8. The reference voltage generation circuit according to claim 3, wherein the switching from the operation period to the third operation period is performed during a second operation period of the first circuit block. 9. A method according to claim 1, wherein the first voltage and the first voltage are changed with respect to a fluctuation width generated with respect to an output terminal voltage of the first circuit block when the first operation period is switched to the second operation period.
When an allowable error with respect to a difference between a voltage at an output terminal of the first circuit block and a predetermined reference voltage, which is a value that has reached a steady state value during the second operation period, is X, in the first circuit block, The longer time from when the period is switched from the first operation period to the second operation period until the fluctuation range of the output voltage generated at the output terminal of the first circuit block falls below the allowable error X is defined as t0. In the second circuit block, from the third operation period to the fourth operation period,
The switching to the third operating period and the switching from the fourth operating period to the third operating period are within the second operating period and are performed in the first circuit block.
4. The operation is performed after a lapse of time t0 or more after switching from the operation period to the second operation period.
9. The reference voltage generation circuit according to any one of claims 8 to 8. 10. When the switching period of the operation period of the first circuit block is F1 and the switching period of the operation period of the second circuit block is F2, K * F1 = F2, where K is an integer. 10. The reference voltage generation circuit according to claim 3, wherein: 11. The frequency of a second clock for driving a second circuit block is f2, and the frequency at which a circuit serving as a load of the reference voltage generation circuit is electrically connected to the second circuit block is fload. 11. The reference voltage generating circuit according to claim 3, wherein fload ≧ f2. 12. The reference voltage generating circuit according to claim 3, wherein a plurality of second circuit blocks are formed for one first circuit block.