JP2010193332A - Switched capacitor amplification circuit, sensor device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve increase in an amplification factor of a switched capacitor amplification circuit or acceleration without increasing power consumption and to vary the amplification factor continuously over a wide range. <P>SOLUTION: A switched capacitor amplification circuit includes: an operational amplifier OP1; a first input capacitor C1; switches (SW1(A), SW2(B), SW3(A)) for controlling charging/discharging of the first input capacitor and a switch SW4(B) for changing over connection/disconnection with the operational amplifier; a first feedback capacitor C2; switches (SW5(C), SW6(D)) for changing over charging/discharging of the first feedback capacitor C2; a second feedback capacitor C3; a switch SW7(C) for changing over connection/disconnection with the first feedback capacitor and the second feedback capacitor; and a reset switch SW8(D) for the second feedback capacitor. A frequency of a switch control clock CKLC is set to 1/(2×n) frequency of CKLA. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a switched capacitor amplifier circuit, a sensor device, an electronic device, and the like.

  1A and 1B are diagrams for explaining the basic operation of a switched capacitor amplifier circuit (SC amplifier, SC integrator circuit). The SC amplifier operates with an externally input clock. There are roughly two operation phases, and the sampling operation and the amplification operation are performed alternately.

  As shown in FIG. 1A, at the time of the sampling operation, the switch SW10 is turned on, the switch SW20 is turned off, the switch SW30 is turned on, and the electric charge corresponding to the input voltage Vin is stored in the input capacitor C1. That is, since the inverting input terminal of the operational amplifier OP10 is virtually grounded, the voltage applied to both ends of the input capacitor C1 is equal to the input voltage Vin. At this time, both poles of the feedback capacitor C20 are short-circuited by turning on the switch SW30, and therefore, the feedback capacitor C20 is in a reset state (state without charge).

As shown in FIG. 1B, during the amplification operation, the switch SW10 is turned off, the switch SW20 is turned on, and the switch SW30 is turned off. As a result, the charge stored in the input capacitor C10 during sampling is transferred to the feedback capacitor C20, and the output voltage Vout is generated according to the amount of the charge. The output voltage Vout is expressed by the following equation (1). However, in the equation (1), C10 and C20 are capacitance values of the input capacitor C10 and the feedback capacitor C20, respectively.
Vout = Vin (C10 / C20) (1)
As apparent from the equation (1), the amplification factor (Vout / Vin) of the SC amplifier is determined by the capacitance ratio of the input capacitor C10 and the feedback capacitor C20. For example, the gain (gain) of the SC amplifier circuit can be changed by variably controlling the capacitance value of the feedback capacitor C20, whereby the SC variable gain amplifier circuit (SC type PGA (Programmable Gain Amplifier)). Is realized.

  The SC type PGA is described in Patent Document 1, for example. In the technique described in Patent Document 1, the gain of the SC type PGA is switched by switching the capacitance value of the feedback capacitor (integral capacitor). Patent Document 1 focuses on the relationship between the gain of the SC type PGA, the usable frequency band and the power consumption, and controls the bias current supplied to the operational amplifier variably according to the gain, thereby suppressing the current consumption. Techniques to do this are disclosed.

JP 2007-19821 A

(1) Difficulty of realizing a high gain, wide band, low power consumption PGA amplifier Actually, when an SC type PGA is operated at a high magnification, the usable frequency band is significantly reduced. In order to operate the SC type PGA at a high magnification, an operational amplifier capable of high speed operation is used as an operational amplifier to be used. Generally, current consumption increases as the operational amplifier operates at high speed. That is, an amplifier capable of operating at a high magnification inevitably increases current consumption. This will be specifically described below.

  FIG. 2 is a diagram illustrating an example of the relationship between the frequency band and the gain (dB) of the operational amplifier. In the drawing, a characteristic PT1 indicated by a dotted line is an open loop gain characteristic of the operational amplifier, and characteristics PT2 and PT3 indicated by a solid line are gain characteristics at the time of negative feedback. Assuming that the unity gain frequency f0 (frequency at which the gain becomes 0 dB) does not change so much during open loop and negative feedback, the gain characteristics PT2 and PT3 during negative feedback follow the open loop gain characteristic PT1. It can be thought of as changing.

  As apparent from FIG. 2, the usable frequency band of the gain characteristic PT2 (for example, in the case of the gain 5 (relative value, corresponding to about 3.5 dB)) is f1, and the gain characteristic PT3 (for example, the gain of 10 The frequency band that can be used (in the case of a relative value and corresponding to 10 dB) is f2. That is, as the gain of the operational amplifier increases, the frequency band of signals that can be handled becomes narrower. Therefore, it is difficult to realize a high gain and wideband amplifier. In general, in order to realize a high gain and wideband amplifier, it is necessary to increase the current consumption of the amplifier. In this case, there is a problem that the power consumption increases.

  In the technique of Patent Document 1, wasteful power consumption may occur if the current consumption of the SC-type PGA is maintained at a high level. Therefore, the bias current of the operational amplifier is changed according to the gain of the SC-type PGA. Is used to reduce power consumption.

  However, since the technique described in Patent Document 1 is a method of reducing the bias current when the gain of the amplifier is low, when the gain of the amplifier is maintained at the maximum gain, the effect of low power consumption is achieved. I can't get it. That is, it is difficult to realize an amplifier having characteristics such as a high gain, a wide band, and low power consumption. In addition, when it is attempted to increase the gain of the SC amplifier, there is a disadvantage that the capacitance value of the switched capacitor circuit increases and the circuit area increases.

(2) Difficulties in continuous and wide-range gain adjustment As in the technique described in Patent Document 1, when the gain of the amplifier is adjusted by changing the capacitance value of the feedback capacitor, a variable capacitor is used as the feedback capacitor. Must. The variable capacitor has, for example, a configuration in which a plurality of capacitors are provided in parallel and the number of capacitors connected in parallel by a switch is switched. When a PGA is configured with this variable capacitor, the settable magnification of the PGA is limited to several stages. In practice, it is extremely difficult to change the magnification continuously and over a wide range. Increasing the PGA magnification step increases the capacity used, increases the occupied area of the capacity, increases the mismatch between the used capacities, and makes it difficult to ensure the specific accuracy. .

  According to some embodiments of the present invention, for example, an increase or speedup of the switched capacitor amplifier circuit can be achieved without increasing power consumption, and for example, the gain can be increased continuously. For example, it is possible to reduce the size of the switched capacitor amplifier circuit.

  (1) According to one aspect of the switched capacitor amplifier circuit of the present invention, an operational amplifier, a first input capacitor provided between a signal input node and an input node of the operational amplifier, and charging / discharging of the first input capacitor are performed. A first input unit comprising: a plurality of switches for switching; and a switch for switching connection / disconnection between the first input capacitor and the input node of the operational amplifier; an output node of the operational amplifier; and the input node; A first feedback capacitor provided between the first feedback capacitor, a plurality of switches for switching charge / discharge of the first feedback capacitor, and an output node and an input node of the operational amplifier. A second feedback capacitor provided in parallel to the second feedback capacitor, at least one switch for switching charge / discharge of the second feedback capacitor, A switch for switching connection / disconnection between the first feedback capacitor and the second feedback capacitor, wherein charge is stored in the first input capacitor, and the charge stored in the first input capacitor is A period in which the operation transferred to the first feedback capacitor is executed n times (n is a natural number) is a sampling integration period, and a period in which the charge accumulated in the first feedback capacitor is transferred to the second feedback capacitor. A plurality of switches for switching charge / discharge of the first input capacitor and a switch for switching connection / disconnection between the input node of the operational amplifier and the first input capacitor in the amplification period In the sampling integration period, a plurality of switches that operate with a clock of a first frequency and switch charge / discharge of the first feedback capacitor, the first feedback capacitor, and the first feedback capacitor The switch for switching connection / disconnection between the feedback capacitor and the plurality of switches for switching charge / discharge for the second feedback capacitor have a frequency value of the first frequency during the amplification period. For switching the connection / disconnection between the first feedback capacitor and the second feedback capacitor in the sampling integration period. The switch maintains an open state, and the plurality of switches for switching charge / discharge of the second feedback capacitor maintain a state of discharging the charge of the second feedback capacitor, and during the amplification period, the switch A switch for switching connection / disconnection between one input capacitor and the input node of the operational amplifier maintains an open state and resets the second feedback capacitor Remains open.

  The switched capacitor amplifier circuit (SC amplifier) of this aspect includes a first input unit including a plurality of switches operating with a first input capacitance and a clock having a first frequency, an operational amplifier, and a frequency value 1 / ( 2 · n) (n is a natural number), a plurality of switches operating with a clock of the second frequency, and a first feedback capacitor and a second feedback capacitor. In addition, the term “first input capacitor” or “first input unit” refers to providing two input units in parallel as an input unit for inputting a signal to the same input terminal of the operational amplifier in a modification described later. There is an example, and in the modified mode, since two input capacitors are used, it is necessary to distinguish between the two. In principle, only one “first input capacitor” is required.

  The plurality of switches that operate with the clock of the first frequency include a switch that switches charging / discharging of the first input capacitor and a switch that switches electrical connection / disconnection between the first input capacitor and the operational amplifier. The plurality of switches operating with the clock of the second frequency include at least one switch (also referred to as a reset switch for the second feedback capacitor) for switching charging / discharging of the second feedback capacitor, and the first feedback capacitor. And a switch for switching an electrical connection between the second feedback capacitor and the second feedback capacitor (also referred to as an electrical isolation switch).

  The basic operation of the SC amplifier of this aspect includes a sampling / integration operation (operation in which sampling and integration are repeated n times) and an amplification operation. In this aspect, sampling and integration are performed n times by opening / closing (ON / OFF) control of a plurality of switches by the clock of the first frequency, and as a result, the charge due to sampling and integration for n times is stored in the first feedback capacitor. Is accumulated (sampling / integration phase). When n times of sampling and integration are completed, the charge accumulated in the first feedback capacitor is transferred to the second feedback capacitor (amplification phase). In the sampling / integration phase, for example, the charge accumulation and transfer are repeated n times using a clock (first frequency clock) that is 2 · n times faster than the conventional operation clock, so that n Double charge can be transferred, so that the capacitance value of the input capacitance is apparently n times. Also. The amplifying operation is executed with a period corresponding to 2.n clocks of the first frequency, for example, based on the clock of the second frequency (for example, the same frequency as the clock frequency conventionally used) (that is, , Once every 2 · n clocks of the first frequency).

Here, when the capacitance value of the first input capacitor is C1, the capacitance value of the first feedback capacitor is C2, and the capacitance value of the second feedback capacitor is C3, the SC amplifier when the sampling / integration is performed n times is performed. The amplification factor G1 is expressed by the following equation (2). However, in the equation (2), Vin is an input voltage, and Vout1 is an output voltage of the SC amplifier in the sampling / integration phase.
G1 = Vout1 / Vin = n · (C1 / C2) (2)
In the sampling / integration phase, the SC amplifier operates with negative feedback of C1 / C2 times. If C1 / C2 is set to a low gain (for example, about 1), the frequency band of the operational amplifier can be sufficiently secured, and the problem of the trade-off between the bandwidth and the gain in the operational amplifier does not occur.

Further, in the amplification phase, C2 · Vout1 = C3 · Vout2 is established from the charge conservation law (where Vout2 is the output voltage of the SC amplifier in the amplification phase), and therefore the amplification factor G2 in the amplification phase is 3) It is expressed by the formula.
G2 = Vout2 / Vout1 = C2 / C3 (3)
Therefore, the final gain G3 of the SC amplifier according to this aspect is expressed by the following equation (4).
G3 = n. (C1 / C2). (C2 / C3) = n (C1 / C3) (4)
As apparent from the equation (4), the amplification factor G3 of the SC amplifier according to this embodiment is determined by the variable (parameter) n and the capacitance ratio of the second feedback capacitor C3 and the first input capacitor C1. In the amplification phase, the SC amplifier operates with negative feedback of C2 / C3 times. The value of (C2 / C3) is set to a reasonable magnification in consideration of the gain to be realized, the maximum frequency of the input signal, the value of n described above, and the characteristics of the operational amplifier. For example, if the maximum gain of the SC amplifier to be realized is 20, C1 / C2 = 1 (that is, C1 = C2) and n is “4”, C2 / C3 (= C1 / C3) is set to “5”. can do.

  In the conventional example, when the amplification factor of the SC amplifier is set to 20 (relative value, no unit), C1 / C3 = 20, and the capacitance value of the input capacitor C1 is set to 20 times the capacitance value of the feedback capacitor C3. (Total capacity value = 21 · C3) If you try to handle high-frequency signals while securing a gain of 20 times, you can increase the amount of bias current to increase the bandwidth of the operational amplifier. I had to. On the other hand, in this embodiment, for example, if n = 4 and C1 = C2, C1 / C3 (= C2 / C3) = 5, the total capacity value may be (11 · C3), and negative. It suffices if a gain of 5 times can be ensured at the time of feedback, and the frequency band of the operational amplifier that can be used is greatly expanded as compared with the conventional example due to the decrease of the gain. In recent integrated circuits, for example, a high-speed clock of about several M to several tens of MHz is generally used as a system clock. Therefore, a high-speed clock necessary for realizing about n = 4 (switched capacitor drive) There is no particular problem with respect to obtaining the clock. Therefore, it is easy to realize the SC amplifier of this aspect.

  In the sampling integration period, charges are transferred from the first input capacitor to the first feedback capacitor and accumulated, and the second feedback capacitor is not involved in the charge accumulation. Therefore, in the sampling integration period, the switch (electrical isolation switch) that switches connection / disconnection between the first feedback capacitor and the second feedback capacitor is maintained in the open state (off state). Further, in the sampling integration period, it is preferable that the second feedback capacitor is maintained in a state in which the electric charge is zero. Therefore, at least one switch (second feedback capacitor) for switching charge / discharge of the second feedback capacitor. The reset switch is maintained in the closed state (on state).

  On the other hand, if the sampling integration operation is continued during the amplification period, the charge to be transferred from the first feedback capacitor to the second feedback capacitor flows backward to the input portion of the amplifier. Therefore, in order to prevent this, a switch (electrical isolation switch) for switching connection / disconnection between the first feedback capacitor and the input node of the operational amplifier is in an open state (off state) during the amplification period. The input of the operational amplifier is disconnected from the operational amplifier body. In addition, during the amplification period, charges are accumulated in the second feedback capacitor, so the switch for switching charge / discharge of the second feedback capacitor (second feedback capacitor reset switch) is in the open state (off state). Maintained.

  As described above, according to this aspect, for example, it is possible to increase or increase the speed of the switched capacitor amplifier circuit without increasing the power consumption. For example, it is possible to reduce the size of the switched capacitor amplifier circuit.

  (2) According to another aspect of the switched capacitor amplifier circuit of the present invention, a first clock and a second clock having a phase opposite to the first clock are prepared as the first frequency clock, and the first frequency A period in which a third clock and a fourth clock having a phase opposite to that of the third clock are prepared as the second frequency clock having a frequency of 1 / (2.n), and the fourth clock is at an active level. Corresponds to the sampling integration period, the period during which the third clock is at the active level corresponds to the amplification period, and the first clock and the second clock are maintained at the inactive level during the amplification period. The switched capacitor amplifier circuit is provided between a first node and a second node which are the signal input nodes, and is supplied with the first clock. A first switch that is controlled to be turned on / off; a second switch that is provided between the second node and a reference potential; and that is controlled to be turned on / off by the second clock; the second node; A first switch connected between the first node, a third switch provided between the third node and a reference potential and controlled to be turned on / off by the first clock; and the third node And a fourth node which is an input node of the operational amplifier, and is provided between the fourth node and the fifth node, and a fourth switch whose on / off is controlled by the second clock. The first feedback capacitor is provided between the fifth node and a reference potential, and is turned on / off by a third clock of the second frequency that is 1 / (2.n) of the first frequency. Controlled fifth switch A sixth switch provided between the fifth node and a sixth node that is an output node of the operational amplifier, the on / off control of which is controlled by a fourth clock having a phase opposite to that of the third clock; A seventh switch provided between the fourth node and the seventh node and controlled to be turned on / off by the third clock; and the second feedback provided between the seventh node and the sixth node. A capacitor and an eighth switch provided in parallel with the second feedback capacitor between the seventh node and the sixth node and controlled to be turned on / off by the fourth clock.

  In this aspect, a first clock and a second clock having a phase opposite to the first clock are prepared as the first frequency clock, and the second frequency is 1 / (2 · n) of the first frequency. As the clock, a third clock and a fourth clock having a phase opposite to that of the third clock are prepared. Further, the period in which the fourth clock is at the active level (for example, H) corresponds to the sampling integration period, the period in which the third clock is at the active level (for example, H) corresponds to the amplification period, and the first clock and the first clock Two clocks are maintained at an inactive level (for example, L) during the amplification period.

  The plurality of switches that operate with the clock of the first frequency include the first switch to the fourth switch, the first switch and the third switch operate with the first clock, and the second switch and the fourth switch Operates with the second clock. Each of the first switch to the third switch functions as a switch for switching charging / discharging of the input capacitance, and the fourth switch functions as a switch for switching connection / disconnection between the first feedback capacitance and the input node of the operational amplifier. To do.

  The plurality of switches that operate with the clock of the second frequency include the fifth switch to the eighth switch, the fifth switch and the seventh switch operate with the third clock, and the sixth switch and the eighth switch Operates with the fourth clock. The fifth switch and the sixth switch function as switches that switch charging / discharging of the first feedback capacitor, and the seventh switch functions as a switch that switches connection / disconnection between the first feedback capacitor and the second feedback capacitor, The eighth switch functions as a switch for switching charge / discharge of the second feedback capacitor (a reset switch for resetting the second feedback capacitor).

  If the sampling integration operation is continued during the amplification period, the charge to be transferred from the first feedback capacitor to the second feedback capacitor flows backward to the input portion of the amplifier. Also, during the amplification period, it is not necessary to operate the switch of the input unit, and if a plurality of switches for switching charging / discharging of the first input capacitor are kept on / off, power is wasted. Therefore, in this aspect, the first frequency clock (the first clock and the second clock) is maintained at the inactive level during the amplification period in order to prevent backflow and reduce unnecessary power consumption. That is, in this aspect, during the amplification period, each of the first switch to the fourth switch included in the input unit is maintained in the open state.

  (3) In another aspect of the switched capacitor amplifier circuit of the present invention, the operational amplifier is a two-input two-output operational amplifier having a first input node and a second input node, and a first output node and a second output node. And a first circuit configuration for the first input node and the first output node of the two-input two-output operational amplifier, and a second input node and the second output node of the two-input two-output operational amplifier. The second circuit configuration is the same, and the size of each of the plurality of switches and the capacitance values of the plurality of capacitors used in the first circuit configuration are used in the second circuit configuration. The size of each switch corresponding to each switch included in the first circuit configuration, and each capacity corresponding to each capacitor included in the first circuit configuration And the capacitance value of, as same, constitutes the amplifying circuit of the fully differential type.

  A fully-differential SC amplifier circuit (fully-differential SC amplifier) is configured using the invention of the aspect described in the above (1) and (2). The fully-differential amplifier has an input signal and an output signal as differential signals, each circuit related to each of the two input signals has the same configuration, and each circuit related to each of the two output signals has the same configuration. This is a symmetrical differential amplifier circuit. In this aspect, in order to realize the symmetry of the circuit, the first input units having the same configuration are provided in parallel, and the sizes of the corresponding switches in each of the two first input units are set to be the same. The capacity value of the capacity is also set to be the same. Similarly, a set of integration / amplification circuits (including a feedback capacitor and a plurality of switches) are provided, and the sizes of the corresponding switches in the two circuits are set to be the same, and the capacitance values of the capacitors are also the same. Set to

  In the fully differential SC amplifier, the common-mode noise superimposed on each of the pair of signal lines is canceled out, so that an effect that low noise characteristics are realized is obtained.

  (4) In another aspect of the switched capacitor amplifier circuit of the present invention, a second input unit is provided in parallel with the first input unit between the signal input node and the input node of the operational amplifier. The second input unit includes a second input capacitor provided between the signal input node and an input node of the operational amplifier, a plurality of switches for switching charge / discharge of the second input capacitor, and the second A switch for switching connection / disconnection between an input capacitor and an input node of the operational amplifier, and each of the plurality of switches included in the second input unit is a corresponding switch in the first input unit. Are complementarily turned on / off.

  In this aspect, for example, a second input unit is provided in parallel with the first input unit between a signal input node and one input node of the operational amplifier (for example, a node connected to the inverting terminal). Similarly to the configuration of the first input unit, the second input unit includes “second input capacitor, a plurality of switches for switching charge / discharge of the second input capacitor, and connection / connection between the second input capacitor and the input node of the operational amplifier. A switch for switching non-connection.

  Each switch in the first input unit and each switch in the second input unit correspond to 1: 1. However, each switch included in the second input unit is turned on / off in a complementary manner to the corresponding switch included in the first input unit. That is, the on / off control clock for each switch included in the second input unit is a clock having a phase opposite to that of the on / off control clock in the corresponding switch included in the first input unit.

  According to this aspect, when charge is accumulated in the first input capacitor in the first input unit (sampling operation), transfer of charge from the second input capacitor of the second input unit to the first feedback capacitor (integration) Operation) is performed, and charge transfer (integration operation) from the first input capacitor to the first feedback capacitor in the first input unit is performed, the charge to the second input capacitor in the second input unit Is accumulated (sampling operation).

That is, in this aspect, in the sampling integration period, the sampling operation and the integration operation are always performed. Therefore, compared with the configuration in which only the first input unit is provided, the input capacity per unit time (first The amount of charge transferred from the first input capacitor and the second input capacitor to the first feedback capacitor is doubled. Therefore, the final gain G4 of the SC amplifier according to this aspect is expressed by the following equation (5).
G4 = (2n · C1 / C2) · (C2 / C3) = 2n · C1 / C3 (5)
Therefore, according to this aspect, an SC amplifier with a higher magnification can be realized without difficulty.

  (5) According to another aspect of the switched capacitor amplifying circuit of the present invention, a ninth aspect is provided between a first node and a twelfth node that are the signal input nodes, and is controlled to be turned on / off by the second clock. A switch, a tenth switch provided between the twelfth node and a reference potential and controlled to be turned on / off by the first clock, and connected between the twelfth node and the thirteenth node; An input switch; an eleventh switch provided between the thirteenth node and a reference potential and controlled to be turned on / off by the second clock; the thirteenth node; and an input node of the operational amplifier. And a twelfth switch provided between the fourth node and controlled to be turned on / off by the one clock.

  The switches included in the second input unit include a ninth switch to a twelfth switch, and each switch corresponds to each of the first switch to the fourth switch in the first input unit. However, as described above, the two switches corresponding to each other are complementarily turned on / off, so that when one is on, the other is off. Such switch control can be easily realized by using the first clock and the second clock described above.

  (6) In another aspect of the switched capacitor amplifier circuit of the present invention, the operational amplifier is a two-input two-output operational amplifier having a first input node and a second input node, and a first output node and a second output node. Yes, a third circuit configuration for the first input node and the first output node of the operational amplifier with two inputs and two outputs, and the second input node and the second output node of the operational amplifier with two inputs and two outputs The fourth circuit configuration is the same, and the size of each of the plurality of switches and the capacitance values of the plurality of capacitors used in the third circuit configuration are used in the fourth circuit configuration. Each switch size corresponding to each switch included in the third circuit configuration, and each size corresponding to each capacitor included in the third circuit configuration. And the capacitance value of the amount, as the same, constitutes the amplifying circuit of the fully differential type.

  A fully differential SC amplifier circuit (fully differential SC amplifier) is configured using the invention of the aspect described in (4) or (5) above. The fully-differential amplifier has an input signal and an output signal as differential signals, each circuit related to each of the two input signals has the same configuration, and each circuit related to each of the two output signals has the same configuration. This is a symmetrical differential amplifier circuit. In this aspect, in order to realize the symmetry of the circuit, in the first input unit and the second input unit, the sizes of two switches corresponding to each other are set to be the same, and the capacitance values of the capacitors are also set to be the same. The

  In the fully differential SC amplifier, the common-mode noise superimposed on each of the pair of signal lines is canceled out, so that an effect that low noise characteristics are realized is obtained.

  (7) According to another aspect of the switched capacitor amplifier circuit of the present invention, in the above (3) or (6), the first input node of the 2-input 2-output operational amplifier and the 2-input 2-output operational amplifier Provided between the first offset cancel capacitor provided between the first input terminal and the second input node of the 2-input 2-output operational amplifier and the second input terminal of the 2-input 2-output operational amplifier. And a first short-circuit switch connected between the first input terminal and the first output node of the two-input / two-output operational amplifier and controlled to be turned on / off by a short-circuit control signal. The second short circuit is connected between the second input terminal and the second output node of the two-input two-output operational amplifier and is controlled to be turned on / off by the short-circuit control signal. The 2-input 2-output operational amplifier is configured so that a common potential between the switch and the first output node and the second output node of the 2-input 2-output operational amplifier is fixed to a certain voltage (second reference voltage). A common mode feedback circuit for performing a common potential stabilization operation by supplying a control signal (common control signal) to the operational amplifier, and an offset cancellation and common mode feedback period after the sampling integration period and the amplification period In the offset cancellation and common mode feedback period, the first short-circuit switch and the second short-circuit switch are turned on, and the first input node of the 2-input 2-output operational amplifier and the 2-input 2-output operational amplifier Both of the second input nodes are maintained at a common potential, and The common potential stabilization operation is performed by the common mode feedback circuit.

  In the fully differential amplifier, the input signal and the output signal are differential signals, and an adjustment operation is required to stabilize the potential (common potential) at the operating point of each signal line of the output signal at an arbitrary potential. For this reason, a common mode feedback circuit (CMFB circuit) is generally provided in a fully differential amplifier. The common mode feedback (CMFB) operation is performed by the following procedure, for example. That is, for example, the first output node and the second output node of the operational amplifier are short-circuited through a voltage dividing resistor, the divided voltage and the reference potential as a reference are compared by a comparator, and the comparison result is fed back to the operational amplifier. Then, with this feedback signal, the potential (common potential) of the operating point of each signal line in the operational amplifier is adjusted, for example, so that the potential (common potential) of the operating point becomes the reference potential.

  Although it is necessary to perform CMFB also in the fully differential SC amplifier according to the present invention, the fully differential amplifier according to the present invention is not in the conventional SC amplifier in which the sampling integration operation and the amplification operation are repeated as described above. Since it is necessary to execute a characteristic operation, when and how to execute this CMFB is an important issue. Considering this, first, it is necessary that the CMFB does not affect the sampling integration operation and the amplification operation described above. From this viewpoint, the CMFB is executed in parallel with the sampling integration operation and the amplification operation. Should be avoided.

  Next, in order to perform CMFB, it is necessary to maintain each of the two output voltages of the operational amplifier at substantially the same level of DC voltage (DC voltage), and it is preferable that this operation can be performed efficiently.

  From these viewpoints, in this embodiment, CMFB is performed in parallel during the offset cancel operation period of the operational amplifier (a period provided separately from the sampling integration period and the amplification period).

  In other words, in the fully differential amplifier, it is preferable to remove the DC offset of the operational amplifier in order to achieve circuit symmetry. As an offset canceling method, for example, there is a method of providing an offset canceling capacitor (having the same voltage value as the DC offset of the operational amplifier) in the offset canceling capacitor by providing offset canceling capacitors at two input terminals of the operational amplifier. In this method, when the offset cancel voltage is generated, one pole of the offset cancel capacitor is fixed to a reference potential (for example, ground) (the other pole is connected to the input terminal of the operational amplifier). At this point, attention is paid to the potentials of the two input terminals (inverting terminal and non-inverting terminal) of the operational amplifier. In other words, at that time, the potential of each of the two input terminals (inverting terminal and non-inverting terminal) of the operational amplifier has a difference corresponding to the offset voltage, but the difference between the offsets is negligible. If the difference between the offsets is ignored, it can be said that the potentials of the two input terminals (inverting terminal and non-inverting terminal) of the operational amplifier are almost the reference potential (for example, ground). Therefore, at the time of offset cancellation, a switch for short-circuiting the input terminal and the output terminal of the operational amplifier is turned on. Then, the potential of each of the two output terminals of the operational amplifier becomes the same potential as the potential of each of the two input terminals (that is, almost GND potential), and thus the two output voltages of the operational amplifier necessary for the CMFB are obtained. The condition of “maintain substantially the same DC voltage” is satisfied. In this state, the CMFB circuit is operated to execute CMFB.

  Thus, in this aspect, since CMFB is executed in parallel with the offset cancel operation, an efficient operation is realized. Further, since CMFB is performed separately from the sampling integration operation and amplification operation, there is no possibility that the influence of the load connected to the operational amplifier during the CMFB affects the sampling integration operation and amplification operation. By efficiently executing the offset cancel operation and the CMFB, the symmetry of the circuit of the fully differential SC amplifier in the actual operation is guaranteed. Therefore, a novel fully differential SC amplifier that can sufficiently withstand practical use is realized.

  (8) In another aspect of the switched capacitor amplifier circuit of the present invention, the gain of the switched capacitor amplifier circuit is variably controlled by changing the parameter n.

  In this aspect, the gain of the SC amplifier is freely adjusted by variably controlling the variable (parameter) n. Thereby, a variable gain amplifier circuit (SC type PGA) using a switched capacitor can be realized. The variable n can be adjusted relatively freely, continuously, and over a wide range by adjusting the frequency relationship between the first frequency and the second frequency. Therefore, according to this aspect, it is possible to realize a novel SC-type PGA capable of changing the amplification factor continuously and over a wide range.

  (9) In another aspect of the switched capacitor amplifier circuit of the present invention, the second frequency clock is generated based on a clock obtained by dividing the first frequency clock by n by a frequency dividing circuit.

  In this aspect, as a method for freely setting the variable n, a method of generating a clock of the second frequency based on a clock obtained by dividing the clock of the first frequency by n by the frequency divider circuit is employed. By variably controlling the frequency dividing ratio in the frequency dividing circuit, the variable n can be freely changed. Since the configuration is simple, implementation is easy.

  (10) In another aspect of the switched capacitor amplifier circuit of the present invention, the second frequency clock synchronized with the first frequency clock is generated based on the clock output from the voltage controlled oscillator.

  In this aspect, as a method for freely setting the variable n, a method of generating a second frequency clock synchronized with the first frequency clock based on the output clock of the voltage controlled oscillator (VCO) is employed. By changing the input voltage level of the VCO, the frequency of the second frequency clock can be changed, and therefore the variable n can be set freely. Further, for example, by synchronizing the operation clock of the VCO with the first frequency clock using, for example, a PLL, a second frequency clock having a desired frequency synchronized with the first frequency clock can be obtained. it can.

  (11) According to another aspect of the switched capacitor amplifier circuit of the present invention, a voltage comparison circuit that compares a voltage of an output signal of the switched capacitor amplifier circuit with a predetermined voltage, and an output voltage of the voltage comparison circuit is converted into a frequency signal. And generating a clock of the second frequency based on a clock signal output from the voltage / frequency conversion circuit.

  In this aspect, an SC type PGA that makes the amplitude of the output signal constant is configured without depending on the amplitude of the input signal. For example, when the output voltage of the SC-type PGA is used for high-definition display control, the output voltage level of the SC-type PGA is set to a desired level with high accuracy and the voltage level is maintained. There is a need to. Therefore, in this aspect, a negative feedback control circuit for maintaining the output voltage of the SC type PGA at a constant value is configured, and a second frequency clock (CKLC, CKLD) is generated based on the output clock of the negative feedback control circuit. To do.

  That is, a voltage comparison circuit that compares the voltage of the output signal of the SC type PGA with a predetermined voltage and a voltage / frequency conversion circuit (such as a VCO) that converts the output voltage of the voltage comparison circuit into a frequency signal are provided. A method of generating a second frequency clock (CKLC, CKLD) based on a clock signal output from a conversion circuit (VCO, etc.) is employed. Thereby, it is possible to obtain an SC type PGA capable of maintaining the output voltage level at a desired level with high accuracy.

  (12) One aspect of the sensor device of the present invention includes a motion sensor and any one of the switched capacitor amplification circuits to which a detection signal output from the motion sensor is input.

  In this aspect, the SC amplifier (including the SC type PGA) according to the present invention is used for amplification of the detection signal output from the motion sensor in the sensor device. The SC amplifier (including the SC type PGA) according to the present invention has excellent effects such as small size, low power consumption, high amplification factor, wide usable frequency band, low noise, and variable amplification factor. Therefore, a sensor device equipped with an SC amplifier can obtain the same effect.

  (13) One aspect of the electronic device of the present invention includes the switched capacitor amplifier circuit according to any one of the above.

  The SC amplifier (including the SC type PGA) according to the present invention has excellent effects such as small size, low power consumption, high amplification factor, wide usable frequency band, low noise, and variable amplification factor. Therefore, an electronic device equipped with an SC amplifier can obtain the same effect.

  Thus, according to some embodiments of the present invention, for example, an increase in gain or speed-up of a switched capacitor amplifier circuit can be achieved without increasing power consumption. The rate can be changed continuously and over a wide range, and for example, the switched capacitor amplifier circuit can be reduced in size (reduction of the area occupied by the capacitor). Improvement can be realized and the error of the magnification of the SC amplifier can be suppressed small.

1A and 1B are diagrams for explaining the basic operation of a switched capacitor amplifier circuit (SC amplifier, SC integrator circuit). The figure which shows an example of the relationship between the frequency band of an operational amplifier, and a gain (dB) 3A and 3B are diagrams for explaining the circuit configuration and operation of the switched capacitor amplifier circuit (SC amplifier) according to the first embodiment of the present invention. FIGS. 4A and 4B are diagrams showing operations (switch on / off state, etc.) in the sampling integration period in the SC amplifier shown in FIG. 3B. FIGS. 5A and 5B are diagrams showing operations (switch ON / OFF states, etc.) in the amplification period of the SC amplifier shown in FIG. 3B. The figure for demonstrating an example of the magnification setting in SC amplifier concerning 1st Embodiment 7A and 7B are diagrams for explaining the circuit configuration and operation of a switched capacitor amplifier circuit (SC amplifier) according to the second embodiment of the present invention. FIGS. 8A and 8B are diagrams showing operations (switch ON / OFF state, etc.) in the sampling integration period in the SC amplifier shown in FIG. 7B. FIGS. 9A and 9B are diagrams showing operations (switch ON / OFF states, etc.) during the amplification period of the SC amplifier shown in FIG. 7B. 10A and 10B are diagrams for explaining the circuit configuration and operation of the switched capacitor amplifier circuit (SC amplifier) according to the third embodiment of the present invention. FIGS. 11A and 11B are diagrams showing operations (switch ON / OFF state, etc.) in the sampling integration period in the SC amplifier shown in FIG. 10B. 12 (A) and 12 (B) are diagrams showing operations (switch on / off states, etc.) during the amplification period of the SC amplifier shown in FIG. 10 (B). 13A and 13B are diagrams for explaining the circuit configuration and operation of a switched capacitor amplifier circuit (SC amplifier) according to the fourth embodiment of the present invention. FIGS. 14A and 14B are diagrams showing operations (switch on / off state, etc.) in the sampling integration period in the SC amplifier shown in FIG. 13B. FIGS. 15A and 15B are diagrams showing operations (switch ON / OFF states, etc.) in the amplification period of the SC amplifier shown in FIG. 13B. FIGS. 16A and 16B are diagrams showing the configuration of an SC amplifier according to the fifth embodiment of the present invention. FIGS. 17A and 17B are diagrams showing operations (switch ON / OFF state, etc.) in the sampling integration period in the fully differential SC amplifier shown in FIG. 18 (A) and 18 (B) show the operation (a switch on / off state, etc.) during the amplification period of the fully differential SC amplifier shown in FIG. 16, and the offset cancel / CMFB operation (switch on / off). / Off state etc.) FIG. 19 is a diagram for explaining an offset cancel operation using an offset cancel capacitor. FIG. 20 is a diagram showing an example of the internal configuration of the CMFB circuit 500 The figure which shows an example of a specific structure of a CMFB circuit The figure which shows the other example of the concrete structure of a CMFB circuit. 23A and 23B are diagrams for explaining the operation of the CMFB circuit shown in FIG. 24A and 24B are diagrams showing a configuration of a variable capacitor. The figure which shows an example of the circuit structure for controlling the variable n variably The figure which shows the other example of the circuit structure for controlling the variable n variably The figure which shows the structural example of SC type | mold PGA which makes the amplitude of an output signal constant regardless of the magnitude | size of the amplitude of an input signal. The figure which shows the structural example of the sensor apparatus and electronic device carrying the SC amplifier of this invention

  Next, embodiments of the present invention will be described with reference to the drawings. Note that the present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are as means for solving the present invention. It is not always essential.

(First embodiment)
3A and 3B are diagrams for explaining the circuit configuration and operation of the switched capacitor amplifier circuit (SC amplifier) according to the first embodiment of the present invention.

  As shown in FIG. 3A, in this embodiment, a first clock (CKLA) having a first frequency is used as an operation clock (switch on / off control clock) of the switched capacitor circuit (SC circuit), A second clock (CKLB) having a phase opposite to that of the clock, a second frequency having a frequency value 1 / (2 · n) of the first frequency, and being synchronized with the first clock and the second clock. Three clocks (CKLC) and a fourth clock (CKLD) having a phase opposite to that of the third clock are used.

  Further, the period in which the fourth clock (CKLD) is at the active level (for example, H) corresponds to the sampling integration period (TD: time t0 to t8), and the period in which the third clock is at the active level (for example, H) is the amplification period. This corresponds to (TC: times t8 to t9). A period TA (time t0 to t1) in which the first clock (CKLA) is at the active level (H level) corresponds to a sampling period, and a period TB (in which the second clock (CKLB) is at the active level (H level). Time t1 to t2) corresponds to an integration period.

  The first clock (CKLA) and the second clock (CKLB) are maintained at an inactive level (for example, L) during the amplification period (CKLC).

  The period of the first clock (CKLA) and the second clock (CKLB) is T, and the period of the third clock (CKLC) and the fourth clock (CKLD) is 8T. Therefore, the third clock (CKLC) and the second clock (CKLC) The frequency (second frequency) of 4 clocks (CKLD) is 1/8 of the frequency (first frequency) of the first clock (CKLA) and the second clock (CKLB), and therefore the value of the variable (parameter) n Is set to “4”. The sampling integration period TD corresponds to 4T (that is, corresponds to nT). Therefore, sampling and integration are repeated four times during the sampling integration period TD.

As shown in FIG. 3B, the switched capacitor amplifier circuit (SC amplifier) of this embodiment includes a first input unit AIN1, an operational amplifier OP1, and an integration / amplification circuit BP1. Specifically, the switched capacitor amplifier circuit (SC amplifier) of this embodiment is
A first switch (SW1 (A)) provided between a first node (N1) and a second node (N2) which are signal input nodes and controlled to be turned on / off by a first clock (CKLA); A second switch (SW2 (B)) provided between the second node (N2) and the reference potential and controlled to be turned on / off by the second clock (CKLB), the second node (N2), and the third node The first input capacitor (C1) connected between the node (N3) and the third node (N3) and the reference potential are provided, and ON / OFF is controlled by the first clock (CKLA). Provided between the third switch (SW3 (A)), the third node (N3), and the fourth node (N4) that is the input node of the operational amplifier (OP1), and is turned on / off by the second clock (CKLB). The 4th switch whose off is controlled (SW4 (B)), a first feedback capacitor (C2) provided between the fourth node (N4) and the fifth node (N5), and provided between the fifth node (N5) and the reference potential. A fifth switch (SW5 (C)) that is controlled to be turned on / off by a third clock (CKLC) having a second frequency that is 1 / (2 · n) of the first frequency, and a fifth node ( N5) and a sixth node (N6) that is an output node of the operational amplifier (OP1), and the sixth clock (CKLD) that is opposite in phase to the third clock is controlled on / off. A switch (SW6 (D)) and a seventh switch (SW7 (C)) provided between the fourth node (N4) and the seventh node (N7) and controlled to be turned on / off by the third clock; , Between the seventh node (N7) and the sixth node node (N6) Is provided in parallel with the second feedback capacitor (C3) between the second feedback capacitor (C3) and the seventh node (N7) and the sixth node (N6), and is turned on / off by the fourth clock. And an eighth switch (SW8 (D)) to be controlled.

  Note that the description “SW1 (A)” regarding the first switch means “the first switch operating with the first clock CKLA”. The description about other switches is also the same.

  The first switch (SW1 (A)) to the fourth switch (SW4 (B)) correspond to a plurality of switches that operate with a clock of the first frequency, and the first switch (SW1 (A)) and the third switch ( SW3 (A)) operates with the first clock CKLA, and the second switch (SW2 (B)) and the fourth switch (SW4 (B)) operate with the second clock CKLB.

  Each of the first switch (SW1 (A)) to the third switch (SW3 (A)) functions as a switch for switching charging / discharging of the input capacitance, and the fourth switch (SW4 (B)) is a first feedback capacitance. It functions as a switch for switching connection / disconnection between C2 and the input node N4 of the operational amplifier OP1.

  The fifth switch (SW5 (C)) to the eighth switch (SW8 (D)) operate with a clock having a second frequency (frequency value is 1 / (2 · n) of the first frequency). It corresponds to the switch. The fifth switch (SW5 (C)) and the seventh switch (SW7 (C)) operate with the third clock CKLC, and the sixth switch (SW6 (D)) and the eighth switch (SW8 (D)) Operates with the fourth clock CKLD. The fifth switch (SW5 (C)) and the sixth switch (SW6 (D)) function as a switch for switching charge / discharge of the first feedback capacitor C2, and the seventh switch (SW7 (C)) is the first feedback. The eighth switch (SW8 (D)) functions as a switch for switching connection / disconnection between the capacitor (C2) and the second feedback capacitor (C3), and the eighth switch (SW8 (D)) is at least for switching charge / discharge of the second feedback capacitor C3. It functions as one switch (reset switch for the second feedback capacitor).

  The basic operation of the SC amplifier shown in FIG. 3B includes a sampling / integrating operation (operation in which sampling and integration are repeated n times) and an amplifying operation. In the present embodiment, sampling and integration are executed n times by opening / closing (on / off) control of the plurality of switches (SW1 (A) to SW4 (B)) by the clocks (CKLA, CKLB) of the first frequency, As a result, n times of sampling / integration charges are accumulated in the first feedback capacitor C2 (sampling / integration phase).

  When n times of sampling and integration are completed (time t8 in FIG. 3A), the charge accumulated in the first feedback capacitor C2 is transferred to the second feedback capacitor C3 (amplification phase: FIG. 3). (A) times t8 to t9). In the sampling / integration phase, for example, the charge accumulation and transfer are repeated n times using a clock (first frequency clock) that is 2 · n times faster than the conventional operation clock, so that n Double charge can be transferred, so that the capacitance value of the input capacitance is apparently n times. Also. The amplifying operation is executed with a period corresponding to 2.n clocks of the first frequency, for example, based on the clock of the second frequency (for example, the same frequency as the clock frequency conventionally used) (that is, , Once every 2 · n clocks of the first frequency).

Here, when the capacitance value of the first input capacitor is C1, the capacitance value of the first feedback capacitor is C2, and the capacitance value of the second feedback capacitor is C3, the SC amplifier when the sampling / integration is performed n times is performed. The amplification factor G1 is expressed by the following equation (2). However, in the equation (2), Vin is an input voltage, and Vout1 is an output voltage of the SC amplifier in the sampling / integration phase.
G1 = Vout1 / Vin = n · (C1 / C2) (2)
In the sampling / integration phase, the SC amplifier operates with negative feedback of C1 / C2 times. If C1 / C2 is set to a low gain (for example, about 1), the frequency band of the operational amplifier can be sufficiently secured, and the problem of the trade-off between the bandwidth and the gain in the operational amplifier does not occur.

Further, in the amplification phase, C2 · Vout1 = C3 · Vout2 is established from the charge conservation law (where Vout2 is the output voltage of the SC amplifier in the amplification phase), and therefore the amplification factor G2 in the amplification phase is 3) It is expressed by the formula.
G2 = Vout2 / Vout1 = C2 / C3 (3)
Therefore, the final gain G3 of the SC amplifier according to this aspect is expressed by the following equation (4).
G3 = n. (C1 / C2). (C2 / C3) = n (C1 / C3) (4)
As apparent from the equation (4), the amplification factor G3 of the SC amplifier according to this embodiment is determined by the variable (parameter) n and the capacitance ratio of the second feedback capacitor C3 and the first input capacitor C1. In the amplification phase, the SC amplifier operates with negative feedback of C2 / C3 times. The value of (C2 / C3) is set to a reasonable magnification in consideration of the gain to be realized, the maximum frequency of the input signal, the value of n described above, and the characteristics of the operational amplifier.

  In the SC amplifier of FIG. 3B, if the sampling integration operation is continued during the amplification period TC, the charge to be transferred from the first feedback capacitor C2 to the second feedback capacitor C3 is provided in the first stage of the operational amplifier. It flows backward to the input unit AIN1. In the amplification period TC, it is not necessary to operate a plurality of switches (SW1 (A) to SW3 (A)) included in the first input unit AIN1 for switching charging / discharging of the first input capacitor C1, If these switches are kept on / off, power is wasted. Therefore, in the circuit of FIG. 3B, the first frequency clock (the first clock CKLA and the second clock CKLB) is set to the inactive level during the amplification period TC in order to prevent backflow and reduce unnecessary power consumption. (L level). That is, in the circuit of FIG. 3B, each of the first to fourth switches (SW1 (A) to SW4 (B)) included in the first input unit (AIN1) is open during the amplification period TC. The state (off state) is maintained.

  In the amplification period TC, the charge is transferred from the first feedback capacitor C2 to the second feedback capacitor C3, and the charge is accumulated in the second feedback capacitor C3. Therefore, the third clock CKLC is at the active level (H level). Thus, the switch (SW7 (C)) for switching the connection / disconnection between the first feedback capacitor C2 and the second feedback capacitor C3 is maintained in the closed state (ON state), and the fourth clock CKLD is inactive. The switch for switching charge / discharge of the second feedback capacitor C3 (reset switch of the second feedback capacitor C3) SW8 (D) at level (L) is maintained in the open state (off state).

  In the sampling integration period TD, charges are transferred from the first input capacitor C1 to the first feedback capacitor C2 and stored, and the second feedback capacitor C3 is not involved in charge storage. Therefore, in the sampling integration period TD, the third clock CKLC becomes inactive level (L level), and the switch (SW7 (C) for switching between connection / disconnection between the first feedback capacitor C2 and the second feedback capacitor C3. ) Is maintained in the open state (off state). Further, in the sampling integration period TD, it is preferable that the second feedback capacitor C3 is maintained in a state in which the electric charge is zero. Therefore, the fourth clock CKLD is maintained at the active level (H level), and the second feedback capacitor A switch (reset switch for the second feedback capacitor C3) SW8 (D) for switching charging / discharging of C3 is maintained in a closed state (on state).

  4 (A) and 4 (B) are diagrams showing the operation (switch on / off state, etc.) during the sampling integration period in the SC amplifier shown in FIG. 3 (B). FIG. 4A shows an operation in the sampling period TA (time t0 to t1) (on / off state of each switch and movement of the charge Q). As is clear from FIG. 4A, the first switch (SW1 (A)) and the third switch (SW3 (A)) are in the on state, and the charge Q is accumulated in the first input capacitor C1. The second switch (SW2 (B)), the fourth switch (SW4 (B)), the fifth switch (SW5 (C)), and the seventh switch (SW7 (C)) are in the off state, and the sixth switch (SW6 (D)) and the eighth switch (SW8 (D)) are on.

  FIG. 4B shows an operation in the integration period TB (time t1 to t2) (on / off state of each switch and movement of the charge Q). As apparent from FIG. 4B, the first switch (SW1 (A)) and the third switch (SW3 (A)) are turned off, while the second switch (SW2 (B)) and the fourth switch (SW4 (B)) is turned on. The fifth switch (SW5 (C)) and the seventh switch (SW7 (C)) are kept off, and the sixth switch (SW6 (D)) and the eighth switch (SW8 (D)) are kept on. To do. The charge Q accumulated in the first input capacitor C1 is transferred to the second feedback capacitor C2.

  The sampling / integration operation shown in FIGS. 4A and 4B is repeated n times. Therefore, in the sampling integration period TD, nQ (here, 4Q) charges are accumulated in the first feedback capacitor C2.

  FIG. 5 is a diagram showing an operation (switch ON / OFF state, etc.) during the amplification period of the SC amplifier shown in FIG. FIG. 5 shows operations in the amplification period TC (time t8 to t9) (on / off state of each switch and how the charge Q moves).

  5, each of the first switch (SW1 (A)) to the fourth switch (SW4 (B)) is maintained in the off state, and the fifth switch (SW5 (C)) and the seventh switch The switch (SW7 (C)) is turned on, and the sixth switch (SW6 (D)) and the eighth switch (SW8 (D)) are turned off, so that they were accumulated in the first feedback capacitor C2. The charge nQ (here, 4Q) is transferred to the second feedback capacitor C3, thereby generating an output voltage Vout at the output node N6, and the final gain of the SC amplifier is expressed by the above equation (4). Thus, n (C1 / C3).

  FIG. 6 is a diagram for explaining an example of magnification setting in the SC amplifier according to the first embodiment. In FIG. 6, it is assumed that the maximum gain of the SC amplifier to be realized is 20, C1 / C2 = 1 (that is, C1 = C2), and n is “4”. In this case, C2 / C3 (= C1 / C3) can be set to “5”.

  When C2 / C3 (= C1 / C3) is set to “5”, the maximum usable frequency of the operational amplifier OP1 is f1. In the conventional example (see FIGS. 1A and 1B), when the amplification factor of the SC amplifier is set to 20, C1 / C3 = 20 must be set, and the capacitance value of the input capacitor C1 is fed back. The capacitance value must be set to 20 times the capacitance value of the capacitance C3 (total capacitance value = 21 · C3), and the maximum usable frequency of the operational amplifier OP1 is f2. Also, if a high frequency signal is to be handled while securing a gain of 20 times (that is, if the maximum usable frequency is set near f1), the bias current amount is increased in order to widen the operational amplifier OP1. Had to be increased.

  On the other hand, in this embodiment, as described above, if n = 4 and C1 = C2, C1 / C3 (= C2 / C3) = 5, the total capacity value may be (11 · C3). In addition, it is only necessary to secure a gain of 5 times at the time of negative feedback, and because the gain is reduced, the maximum frequency of the operational amplifier that can be used is f1, and the usable frequency band is greatly expanded as compared with the conventional example. (That is, it is expanded from f2 to f1). In recent integrated circuits, for example, a high-speed clock of about several M to several tens of MHz is generally used as a system clock. Therefore, a high-speed clock necessary for realizing about n = 4 (switched capacitor drive) There is no particular problem with respect to obtaining the clock. Therefore, it is easy to realize the SC amplifier of this embodiment.

  As described above, according to the present embodiment, for example, an increase in the gain of the switched capacitor amplifier circuit or an increase in speed can be achieved without increasing the power consumption. In addition, it is possible to change in a wide range, and, for example, downsizing of the switched capacitor amplifier circuit can be realized.

(Second Embodiment)
FIGS. 7A and 7B are diagrams for explaining the circuit configuration and operation of a switched capacitor amplifier circuit (SC amplifier) according to the second embodiment of the present invention.

  In the present embodiment, the circuit configuration of the SC amplifier shown in FIG. 3B is developed and a fully differential SC amplifier circuit (fully differential SC amplifier) is configured. The fully-differential amplifier has an input signal and an output signal as differential signals, each circuit related to each of the two input signals has the same configuration, and each circuit related to each of the two output signals has the same configuration. This is a symmetrical differential amplifier circuit. In this embodiment, in order to realize the symmetry of the circuit, two first input units (AIN1a, AIN1b) having the same configuration are provided, and the size of the corresponding switch in each first input unit (AIN1a, AIN1b). Are set to be the same, and the capacitance values of the input capacitors are also set to be the same.

  In addition, a set of integration / amplification circuits (including feedback capacitors and a plurality of switches) BP1a and BP1b are provided, and the sizes of the corresponding switches in each of the two circuits (BP1a and BP1b) are set to be the same. The capacitance value of the feedback capacitor is also set to be the same. As the operational amplifier, an operational amplifier OP2 corresponding to a fully differential configuration with 2 inputs and 2 outputs is used.

  Since the fully differential SC amplifier has a differential configuration, the common-mode noise superimposed on each of the pair of signal lines is canceled out, so that an effect of realizing low noise characteristics can be obtained.

  In FIG. 7B, a component of one circuit of a pair of symmetrically arranged circuits constituting the fully differential SC amplifier is given a suffix a, and a component of the other circuit. Is appended with a subscript b so that each component can be distinguished.

  FIG. 8A and FIG. 8B are diagrams showing the operation (switch on / off state, etc.) in the sampling integration period in the SC amplifier shown in FIG. 7B. FIG. 9 is a diagram showing an operation (switch ON / OFF state, etc.) in the amplification period of the SC amplifier shown in FIG. 7B. The circuit operation shown in FIGS. 8 and 9 is basically the same as the circuit operation shown in FIGS. 4 and 5. However, in the SC amplifiers of FIGS. 8 and 9, each of a set of circuits simultaneously performs the same operation.

(Third embodiment)
FIGS. 10A and 10B are diagrams for explaining the circuit configuration and operation of a switched capacitor amplifier circuit (SC amplifier) according to the third embodiment of the present invention.

  In the present embodiment, for example, between the signal input node N1 and one input node (for example, a node connected to the inverting terminal) N4 of the operational amplifier OP1, the second input unit AIN2 is in parallel with the first input unit AIN1. Provided. Similarly to the configuration of the first input unit AIN1, the second input unit AIN2 is “a plurality of switches (SW9 (B), SW10 (A) for switching charge / discharge of the second input capacitor C4 and the second input capacitor C4”. , SW11 (B)), and a switch SW12 (A) for switching connection / disconnection between the second input capacitor C4 and the input node N4 of the operational amplifier OP1.

  Each switch in the first input unit AIN1 and each switch in the second input unit AIN2 correspond to 1: 1. However, the switches (SW10 (A) to SW12 (A)) included in the second input unit AIN2 are the same as the switches (SW1 (A) to SW4 (B)) included in the first input unit AIN1. On / off complementary to each). That is, the on / off control clocks (CKLB, CKLA) for the switches (each of SW10 (A) to SW12 (A)) included in the second input unit AIN2 are included in the first input unit AIN1. The on / off control clocks (CKLA, CKLB) in the switches (each of SW1 (A) to SW4 (B)) are clocks of opposite phase.

  According to the present embodiment, when charge is accumulated in the first input capacitor C1 in the first input unit AIN1 (during sampling operation), the second input capacitor C4 of the second input unit AIN2 shifts to the first feedback capacitor C2. Charge transfer (integration operation) is performed, and when charge transfer (integration operation) from the first input capacitor to the first feedback capacitor in the first input unit is performed, the second input unit performs the second transfer. Charge accumulation (sampling operation) in the two input capacitors is executed.

That is, in the present embodiment, the sampling operation and the integration operation are always executed in the sampling integration period TD. Therefore, compared with the configuration in which only the first input unit AIN1 is provided, the input per unit time The amount of charge transferred from the capacitor (including the first input capacitor C1 and the second input capacitor C4) to the first feedback capacitor C2 is doubled. Therefore, the final gain G4 of the SC amplifier according to this aspect is expressed by the following equation (5).
G4 = (2 · nC1 / C2) · (C2 / C3) = 2 · nC1 / C3 (5)
Therefore, according to the present embodiment, an SC amplifier with a higher magnification can be realized without difficulty.

  FIGS. 11A and 11B are diagrams illustrating the operation (switch ON / OFF state, etc.) in the sampling integration period in the SC amplifier shown in FIG. 10B. FIG. 12 is a diagram showing an operation (switch on / off state, etc.) in the amplification period of the SC amplifier shown in FIG. 10 (B).

  In FIG. 11A, the charge Q is accumulated in the first input capacitor C1, and the charge Q accumulated in the second input capacitor C4 is transferred to the first feedback capacitor C2. In FIG. 11B, the charge Q is accumulated in the second input capacitor C4, and the charge Q accumulated in the first input capacitor C1 is transferred to the first feedback capacitor C2. In FIG. 12, a charge of 2nQ (8Q because n = 4 in this case) is transferred from the first feedback capacitor C2 to the second feedback capacitor C3.

(Fourth embodiment)
FIGS. 13A and 13B are diagrams for explaining the circuit configuration and operation of a switched capacitor amplifier circuit (SC amplifier) according to the fourth embodiment of the present invention.

  In the present embodiment, the circuit configuration of the SC amplifier (the SC amplifier according to the third embodiment) shown in FIG. 10B is developed, and a fully differential SC amplifier circuit (fully differential SC amplifier) is applied. Configure. As described above, the fully-differential amplifier uses the input signal and the output signal as differential signals, the circuits related to each of the two input signals have the same configuration, and the circuits related to each of the two output signals. Are symmetrical differential amplifier circuits having the same configuration.

  As in the case of the SC amplifier of FIG. 7B, the SC amplifier of FIG. 13B includes an operational amplifier OP2 corresponding to a fully differential format with two inputs and two outputs, and one input terminal and one of the operational amplifier OP2 One circuit related to the output terminal and the other input terminal of the operational amplifier OP2 and the other circuit related to the other output terminal have the same configuration, and the same switch size is used. The capacity value of the capacity to be used is set to be the same.

  As described above, since the fully differential SC amplifier has a differential configuration, the common-mode noise superimposed on each of the pair of signal lines is canceled out, so that an effect of realizing low noise characteristics can be obtained.

  In FIG. 13B, a component of one circuit of a pair of symmetrically arranged circuits constituting the fully differential SC amplifier is given a suffix a, and a component of the other circuit. Is appended with a subscript b so that each component can be distinguished.

  FIG. 14A and FIG. 14B are diagrams showing the operation (switch on / off state, etc.) in the sampling integration period in the SC amplifier shown in FIG. 13B. FIG. 15 is a diagram showing an operation (switch ON / OFF state, etc.) in the amplification period of the SC amplifier shown in FIG.

  In FIG. 14A, the charge Q is accumulated in the first input capacitor C1a, the charge Q accumulated in the second input capacitor C4a is transferred to the first feedback capacitor C2, and the charge is accumulated in the second input capacitor C4b. Q is accumulated, and the charge Q accumulated in the first input capacitor C1b is transferred to the first feedback capacitor C2.

  In FIG. 14B, the charge Q is accumulated in the second input capacitor C4a, the charge Q accumulated in the first input capacitor C1a is transferred to the first feedback capacitor C2, and the charge is accumulated in the first input capacitor C1b. Q is accumulated, and the charge Q accumulated in the second input capacitor C4b is transferred to the first feedback capacitor C2.

  In FIG. 15, a charge of 2nQp (here, 8Qp because n = 4 because n = 4) is transferred from the first feedback capacitor C2a to the second feedback capacitor C3a, and the second feedback capacitor C3b is transferred from the first feedback capacitor C2b. In addition, a charge of 2nQn (here, 8Qn because n = 4) is transferred.

(Fifth embodiment)
FIG. 16 is a diagram showing a configuration of an SC amplifier according to the fifth embodiment of the present invention. In the present embodiment, an offset cancel operation and a common mode feedback (CMFB) operation are executed in parallel in a fully differential SC amplifier.

  In addition to the configuration of the fully differential SC amplifier shown in FIG. 13B, the fully differential SC amplifier of FIG. 16 further includes a first input node (N4a) of a 2-input 2-output operational amplifier (OP2). And a first offset cancel capacitor (CS1a) provided between a first input terminal (here, an inverting terminal) of a two-input two-output operational amplifier (OP2) and a second input of the two-input two-output operational amplifier (OP2). A second offset cancel capacitor (CS1b) provided between the input node (N4b) and the second input terminal (here, non-inverting terminal) of the 2-input 2-output operational amplifier (OP2), and a 2-input 2-output operational amplifier A first short-circuit switch (CM1a (CM1a () connected between the first input terminal (inverting terminal) and the first output node (N6a) of (OP2) and controlled to be turned on / off by a short-circuit control signal (RES). RES)) and a second input terminal (non-inverting terminal) of a two-input two-output operational amplifier (OP2) and a second output node (N6b), which are turned on / off by a short-circuit control signal (RES). The difference between the common potential of the second output node (N6b) and the second short-circuit switch (CM1b (RES)) to be controlled, the first output node (N6a) of the operational amplifier (OP2) with two inputs and two outputs. A common mode feedback circuit (CMFB: reference numeral 500) that performs a common potential common operation by supplying a common control signal (NFB) to the operational amplifier (OP2) having two inputs and two outputs so that the voltage is reduced; Have

  Then, an offset cancellation / common mode feedback period (TRES) is provided after the sampling integration period (TD) and amplification period (TC). In the offset cancellation / common mode feedback period (TRES), the first short-circuit switch ( CM1a (RES)) and the second short circuit switch (CM1b (RES)) are turned on, and the first input node (N4a) of the two-input two-output operational amplifier (OP2) and the second operational amplifier (OP2) of the two-input two-output operational amplifier (OP2). The two input nodes (N4b) are both maintained at a common potential, and a common potential sharing operation is performed by the common mode feedback circuit (CMFB: reference numeral 500). This will be specifically described below.

  In the fully differential amplifier, the input signal and the output signal are differential signals, and in order to ensure the symmetry of the circuit, the potentials (common potentials) of the operating points of the pair of signal lines are set to arbitrary potentials. Adjustment operation is necessary. For this reason, a common mode feedback circuit (CMFB circuit) is generally provided in a fully differential amplifier. The common mode feedback (CMFB) operation is performed by the following procedure, for example. That is, for example, the first output node and the second output node of the operational amplifier are short-circuited through a voltage dividing resistor, the divided voltage and the reference potential as a reference are compared by a comparator, and the comparison result is fed back to the operational amplifier. Then, with this feedback signal, the potential (common potential) of the operating point of each signal line in the operational amplifier is adjusted, for example, so that the potential (common potential) of the operating point becomes the reference potential.

  Although it is necessary to perform CMFB also in the fully differential SC amplifier according to the present invention, the fully differential amplifier according to the present invention is not in the conventional SC amplifier in which the sampling integration operation and the amplification operation are repeated as described above. Since it is necessary to execute a characteristic operation, when and how to execute this CMFB is an important issue. Considering this, first, it is necessary that the CMFB does not affect the sampling integration operation and the amplification operation described above. From this viewpoint, the CMFB is executed in parallel with the sampling integration operation and the amplification operation. Should be avoided.

  Next, in order to perform CMFB, it is necessary to maintain each of the two output voltages of the operational amplifier at substantially the same level of DC voltage (DC voltage), and it is preferable that this operation can be performed efficiently.

  From these viewpoints, in the present embodiment, CMFB is performed in parallel during the offset cancel operation period of the operational amplifier (a period provided separately from the sampling integration period and the amplification period).

  In other words, in the fully differential amplifier, it is preferable to remove the DC offset of the operational amplifier in order to achieve circuit symmetry. As an offset canceling method, for example, there is a method of providing an offset canceling capacitor (having the same voltage value as the DC offset of the operational amplifier) in the offset canceling capacitor by providing offset canceling capacitors at two input terminals of the operational amplifier.

  Here, FIG. 19 and FIG. 20 are referred. FIG. 19 is a diagram for explaining an offset cancel operation using an offset cancel capacitor. FIG. 20 is a diagram illustrating an example of the internal configuration of the CMFB circuit 500.

  As shown in FIG. 19, when the offset cancel voltage (Voff) is generated in each of the offset cancel capacitors CS1a and CS1b, one pole (that is, the electrodes P1a and P1b) of each offset cancel capacitor (CS1a and CS1b) It is fixed to a reference potential (for example, ground) (the other pole is connected to the input terminal of the operational amplifier).

  At this time, attention is paid to the potentials of the two input terminals (inverting terminal and non-inverting terminal) of the operational amplifier OP2. In other words, at that time, there is a difference corresponding to the offset voltage (that is, offset cancel voltage Voff) between the two input terminals (the inverting terminal and the non-inverting terminal) of the operational amplifier OP2. Therefore, if the difference of the offset is ignored, the potential of each of the two input terminals (inverting terminal and non-inverting terminal) of the operational amplifier OP2 is almost the reference potential (for example, ground). It can be said that

  Therefore, as shown in FIG. 20, at the time of offset cancellation, the first short-circuit switch CS1a and the second short-circuit switch CS1b are turned on. Then, the potential of each of the two output terminals of the operational amplifier OP2 becomes the same potential as the potential of each of the two input terminals (that is, almost the GND potential), whereby “the two output voltages of the operational amplifier necessary for the CMFB” Are maintained at substantially the same DC voltage ". In this state, the CMFB circuit 500 shown in FIG. 20 is operated to execute common mode feedback (CMFB).

  That is, the common mode feedback (CMFB circuit) 500 detects and detects the common potential (operating point potential) of the two output terminals of the operational amplifier OP2, for example, when the common potential is stabilized at Vref by the common voltage detection circuit 502. The compared common potential is compared with a reference potential (Vref: Vref = GND here) by the comparator 504, the comparison result is input to the amplifier 506 for gain adjustment, and the output of the amplifier 506 for gain adjustment The signal is fed back to the common control terminal of the operational amplifier OP2, for example, as the common control signal NFB. By such negative feedback control, the common potential is always adjusted so as to match the reference potential (Vref: Vref = GND here).

  Here, a series of operations of the fully differential SC amplifier according to the present embodiment will be described with reference to FIGS. 17 (A), 17 (B), 18 (A), and 18 (B). FIGS. 17A and 17B are diagrams illustrating the operation (switch on / off state, etc.) in the sampling integration period in the fully differential SC amplifier shown in FIG. 18A and 18B show operations during the amplification period of the fully differential SC amplifier shown in FIG. 16 (switch on / off state, etc.), as well as offset cancellation and CMFB operation (switch FIG.

  The operations at the time of sampling integration shown in FIGS. 17A and 17B and the operation at the time of amplification shown in FIG. 18A are shown in FIGS. 14A, 14B, and 15. Same operation as shown. In the present embodiment, as shown in FIG. 18B, after sampling integration and amplification are performed, an offset cancel / CMFB operation is performed. The contents of the offset cancel / CMFB operation are as described with reference to FIG.

  FIG. 21 is a diagram illustrating an example of a specific configuration of the CMFB circuit. In FIG. 21, the two output voltages (Voutp and Voutn) of the operational amplifier OP2 are divided by the voltage dividing resistors R1 and R2 to obtain a common voltage. The common voltage is compared with the reference voltage Vref by the comparator 506, and the output of the comparator 506 is fed back to, for example, the common voltage adjustment terminal of the operational amplifier OP2.

  Next, another embodiment of the common mode feedback circuit (CMFB circuit) will be described with reference to FIGS. FIG. 22 is a diagram illustrating another example of a specific configuration of the CMFB circuit. In the CMFB circuit of FIG. 22, the CMFB operation is executed using switched capacitors (a plurality of switches SWAa, SWAb, SWBa, SWBb, SWC, SWD and capacitors CX, CY). The capacitance values of the capacitor CX and the capacitor CY are set to the same value.

  The two switches SWAa and SWAb are turned on / off in conjunction with each other, and the two switches SWBa and switch SWBb are turned on / off in conjunction with each other. Further, the switch SWAa and the switch SWAb and the switch SWBa and the switch SWBb are turned on complementarily (that is, when one switch pair is turned on, the other switch pair is turned off). Further, the switches SWC and SWD are complementarily turned on.

In FIG. 22, the voltages at the two output terminals OUTP and OUTN are V (OUTP) and V (OUTN), respectively. Here, the common mode voltage VOUTCM of V (OUTP) and V (OUTN) is expressed by the following equation (6).
VOUTCM = (V (OUTP) + V (OUTN)) / 2 (6)
The CMFB circuit in FIG. 22 performs feedback to the fully differential OP amplifier OP2 so that the common mode voltage VOUTCM is close to an arbitrary voltage VCM. “VCM” and “reference voltage Vref” in the figure are not the same. “VCM” is a target value of VOUTCM. On the other hand, the “reference voltage Vref” gives a voltage approximately close to the “feedback voltage Vfb”. This reference voltage Vref varies depending on the OP amplifier used, and is determined by the circuit configuration inside the OP amplifier.

  In FIG. 22, the switches SWAa and SWAb are turned off, the switches SWBa and SWBb are turned on, the switch SWD is turned on, and the switch SWC is turned off. This circuit state can be called a common voltage detection state. On the other hand, the on / off state of each switch is opposite to the state shown in FIG. 22 (switches SWAa and SWAb are turned on, switches SWBa and SWBb are turned off, switch SWD is turned off, and switch SWC is turned on. Can be called a feedback state. The circuit of FIG. 22 repeats the common voltage detection state and the feedback state alternately several tens of times and several hundreds of times. Initially, the movement of charge across the capacitor occurs as the state is switched, but eventually the movement of the charge decreases, and when the state is switched, there is no charge movement across the capacitor (steady state). Stabilize. FIG. 23A and FIG. 23B show the capacity state at that time (steady state).

In FIGS. 23A and 23B, Q indicates the amount of charge charged at the node. As is clear from FIGS. 23A and 23B, the following expression (7) is established, and therefore the following expression (8) is obtained.
VCM−Vfb = {(V (OUTP) + V (OUTN)) / 2} −Vref (7)
VOUTCM = (V (OUTP) + V (OUTN)) / 2 = VCM + (Vref−Vfb) (8)
Since the reference voltage Vref is set to a voltage close to the feedback voltage Vfb, in the equation (8), Vref−Vfb≈0, and therefore, the common mode voltage VOUTCM is substantially equal to an arbitrary voltage VCM that is a target value. Become. That is, the common mode voltage is fixed to an arbitrary voltage VCM, and the common mode voltage stabilization operation is executed.

  Thus, in this embodiment, since common mode feedback (CMFB) is performed in parallel with the offset cancel operation, an efficient operation is realized. Further, since CMFB is performed separately from the sampling integration operation and amplification operation, there is no possibility that the influence of the load connected to the operational amplifier during the CMFB affects the sampling integration operation and amplification operation. By efficiently executing the offset cancel operation and the CMFB, the symmetry of the circuit of the fully differential SC amplifier in the actual operation is guaranteed. Therefore, a novel fully differential SC amplifier that can sufficiently withstand practical use is realized.

(Sixth embodiment)
In the present embodiment, the amplification factor of the switched capacitor amplifier circuit (SC amplifier) is variably controlled by changing the parameter n. In other words, the gain of the SC amplifier is freely adjusted by variably controlling the variable (parameter) n. Thereby, a variable gain amplifier circuit (SC type PGA) using a switched capacitor can be realized. The variable n can be adjusted relatively freely, continuously, and over a wide range by adjusting the frequency relationship between the first frequency and the second frequency.

  24A and 24B are diagrams showing the configuration of the variable capacitor. If this variable capacitor is used, the gain of the SC amplifier can be variably controlled. The variable capacitor shown in FIG. 24A can be realized by the circuit configuration shown in FIG.

  In FIG. 24B, a plurality of capacitors (CP1 to CP4) are provided, and a switch (analog switch or the like) corresponding to each capacitor is provided. By controlling on / off of the switch, the capacitance value is It is controlled in stages. However, the capacitance value of the variable capacitor can be changed only in steps, and it is difficult to control the capacitance value over a wide range.

  On the other hand, the SC amplifier according to the present invention can change the variable n continuously in a circuit and over a wide range, and can easily change n. Therefore, according to the present embodiment, it is possible to realize a novel SC type PGA capable of continuously and widely changing the amplification factor of the SC amplifier.

  FIG. 25 is a diagram illustrating an example of a circuit configuration for variably controlling the variable n. In FIG. 25, the SC type PGA is described as a PGA core 600. In FIG. 25, the circuit configuration shown in FIG. 3B is adopted as the circuit configuration of the PGA core 600.

  In the circuit of FIG. 25, in order to variably control the variable n, the clock having the second frequency (the third clock is based on the clock obtained by dividing the clock CLK having the first frequency by n by the frequency dividing circuit 410. CKLC, fourth clock CKLD). That is, the clock signal output from the frequency dividing circuit 410 is used as the third clock CKLC, and the clock signal obtained by inverting the level of the clock output from the frequency dividing circuit 410 by the inverter INV2 is used as the fourth clock CKLD. The

  In the circuit of FIG. 25, the first frequency clock CLK is used as it is as the first clock (CKLA), and the clock signal obtained by inverting the level of the first frequency clock CLK by the inverter INV1 is used as the second clock CKLB. used. If the circuit shown in FIG. 25 is used, the variable n can be freely changed by variably controlling the frequency dividing ratio in the frequency dividing circuit 410. Since the configuration is simple, implementation is easy.

  FIG. 26 is a diagram illustrating another example of a circuit configuration for variably controlling the variable n. In the circuit shown in FIG. 26, based on the output clock of the voltage controlled oscillator (VCO) 412, the second frequency clocks (the third clock CKLC and the fourth clock CKLD) synchronized with the first frequency clock CLK are generated. . The frequency of the output clock of the VCO 412 can be variably controlled by the input control voltage CTL. Therefore, the variable n can be set freely.

  In the circuit of FIG. 26, the output clock of the VCO 412 is used as it is as the third clock CKLC, and the clock obtained by inverting the level of the output clock of the VCO 412 by the inverter INV2 is used as the fourth clock CKLD.

  Further, for example, by synchronizing the operation clock in the VCO 412 with the first frequency clock CLK using, for example, a PLL, a second frequency clock (CKLC) having a desired frequency synchronized with the first frequency clock CLK. , CKLD).

(Seventh embodiment)
FIG. 27 is a diagram illustrating a configuration example of an SC-type PGA that makes the amplitude of the output signal constant without depending on the amplitude of the input signal.

  In the present embodiment, an SC type PGA that makes the amplitude of the output signal constant is configured without depending on the amplitude of the input signal. For example, when the output voltage of the SC-type PGA is used for high-definition display control, the output voltage level of the SC-type PGA is set to a desired level with high accuracy and the voltage level is maintained. There is a need to. Therefore, in this aspect, a negative feedback control circuit for maintaining the output voltage of the SC type PGA at a constant value is configured, and a second frequency clock (CKLC, CKLD) is generated based on the output clock of the negative feedback control circuit. To do.

  That is, a voltage comparison circuit 435 (including the voltage detection circuit 420 and the voltage comparator 430) that compares the voltage of the output signal of the SC type PGA with a predetermined voltage, and a voltage that converts the output voltage of the voltage comparison circuit 435 into a frequency signal. / Frequency conversion circuit 450 (including gain adjustment amplifier 440 and VCO 410), and based on the clock signal output from voltage / frequency conversion circuit 450, the second frequency clock (CKLC, CKLD) ) Is generated. Thereby, it is possible to obtain an SC type PGA capable of maintaining the output voltage level at a desired level with high accuracy.

  The magnification of the SC type PGA (PGA core 600) can be obtained from the ratio of the first frequency clock (CKLA or CKLB) and the second frequency clock (CKLC or CKLD) inside the PGA core 600. . Therefore, for example, an analog / digital conversion circuit (A / D conversion circuit) is connected to the output terminal PN2 of the PGA core 600, and, for example, the power supply voltage is adaptively changed according to the magnification inside the PGA core 600. A high dynamic range A / D conversion circuit can also be realized.

(Eighth embodiment)
FIG. 28 is a diagram showing a configuration example of a sensor device and an electronic device on which the SC amplifier of the present invention is mounted.

  A sensor device 700 is mounted on the electronic device 800 shown in FIG. The sensor device 700 includes a motion sensor 710 and an analog front end (AFE: IC) 720.

  The analog front end (AFE) 720 receives the detection signal output from the motion sensor 710, and the switched capacitor amplifier circuit (that is, the PGA core 600) of any of the above embodiments, and the A / D converter 610. And having.

  In the present embodiment, the SC amplifier (PGA core 600) is used for amplification of the detection signal output from the motion sensor in the sensor device. The SC amplifier (including the SC type PGA) according to the present invention has excellent effects such as small size, low power consumption, high amplification factor, wide usable frequency band, low noise, and variable amplification factor. Therefore, the sensor device 700 equipped with the SC amplifier and the electronic device 800 can obtain the same effect.

  Thus, according to some embodiments of the present invention, for example, an increase in gain or speed-up of a switched capacitor amplifier circuit can be achieved without increasing power consumption. The rate can be changed continuously and over a wide range, and for example, the switched capacitor amplifier circuit can be reduced in size (reduction of the area occupied by the capacitor). Improvement can be realized and the error of the magnification of the SC amplifier can be suppressed small.

  The present invention is useful as an amplifier circuit (including a variable gain amplifier) using a switched capacitor. The present invention is applicable to all analog semiconductor integrated circuits.

  In addition, although this embodiment was explained in full detail, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Therefore, all such modifications are included in the present invention.

SW1 (A) to SW8 (D) 1st switch to 8th switch,
OP1 operational amplifier (single-ended output), C1 input capacitance (first input capacitance)
OP2 Fully differential operational amplifier (2 inputs and 2 outputs), C2 first feedback capacitor,
C3 second feedback capacitance, C4 input capacitance (second input capacitance),
CS1a, CS1b offset cancellation capacity,
410 frequency divider (frequency divider), 412, 450 VCO,
420 voltage level detection circuit, 430 comparator, 440 gain adjustment circuit,
500 common mode feedback circuit (CMFB circuit),
CM1a, CM1b Fully differential operational amplifier switches that short-circuit the input terminal and output terminal,
600 PGA core, 610 A / D conversion circuit, 700 sensor device,
710 motion sensor, 720 analog front end (AFE)

Claims (13)

An operational amplifier,
A first input capacitor provided between a signal input node and an input node of the operational amplifier; a plurality of switches for switching charge / discharge of the first input capacitor; and the input of the first input capacitor and the operational amplifier A first input unit having a switch for switching connection / disconnection with a node;
A first feedback capacitor provided between an output node of the operational amplifier and the input node;
A plurality of switches for switching charge / discharge of the first feedback capacitor;
A second feedback capacitor provided in parallel with the first feedback capacitor between the output node of the operational amplifier and the input node;
At least one switch for switching charge / discharge of the second feedback capacitor;
A switch for switching connection / disconnection between the first feedback capacitor and the second feedback capacitor;
Including
A period in which an operation in which charges are accumulated in the first input capacitor and the charges accumulated in the first input capacitor are transferred to the first feedback capacitor is executed n times (n is a natural number) is a sampling integration period, When the period during which the charge accumulated in the first feedback capacitor is transferred to the second feedback capacitor is an amplification period,
In the sampling integration period, a plurality of switches for switching charging / discharging for the first input capacitance and a switch for switching connection / disconnection between the input node of the operational amplifier and the first input capacitance are: Operates with a first frequency clock,
A plurality of switches for switching charging / discharging of the first feedback capacitor; a switch for switching connection / disconnection between the first feedback capacitor and the second feedback capacitor; and the second feedback capacitor. A plurality of switches for switching charging / discharging with respect to the first frequency, the frequency value is 1 / (2 · n) of the first frequency in the amplification period,
In the sampling integration period, the switch for switching connection / disconnection between the first feedback capacitor and the second feedback capacitor is kept open, and charging / discharging of the second feedback capacitor is performed. A plurality of switches for switching between the two maintain a state of discharging the charge of the second feedback capacitor,
In the amplification period, a switch for switching connection / disconnection between the first input capacitor and the input node of the operational amplifier is maintained in an open state, and a switch for resetting the second feedback capacitor is in an open state. To maintain the
A switched capacitor amplifier circuit. The switched capacitor amplifier circuit according to claim 1,
A first clock and a second clock having a phase opposite to the first clock are prepared as the first frequency clock,
As a clock of the second frequency that is 1 / (2 · n) of the first frequency, a third clock and a fourth clock having a phase opposite to the third clock are prepared,
A period in which the fourth clock is at an active level corresponds to the sampling integration period, a period in which the third clock is at an active level corresponds to the amplification period,
The first clock and the second clock are maintained at an inactive level during the amplification period,
The switched capacitor amplifier circuit includes:
A first switch provided between a first node and a second node which are the signal input nodes and controlled to be turned on / off by the first clock;
A second switch provided between the second node and a reference potential and controlled to be turned on / off by the second clock;
The first input capacitance connected between the second node and a third node;
A third switch provided between the third node and a reference potential and controlled to be turned on / off by the first clock;
A fourth switch provided between the third node and a fourth node that is an input node of the operational amplifier, the on / off of which is controlled by the second clock;
The first feedback capacitor provided between the fourth node and the fifth node;
A fifth switch provided between the fifth node and a reference potential and controlled to be turned on / off by a third clock of the second frequency that is 1 / (2 · n) of the first frequency; ,
A sixth switch that is provided between the fifth node and a sixth node that is an output node of the operational amplifier, the on / off control of which is controlled by a fourth clock having a phase opposite to that of the third clock;
A seventh switch provided between the fourth node and the seventh node and controlled to be turned on / off by the third clock;
The second feedback capacitor provided between the seventh node and the sixth node;
An eighth switch provided in parallel with the second feedback capacitor between the seventh node and the sixth node and controlled to be turned on / off by the fourth clock;
A switched capacitor amplifier circuit comprising: A switched capacitor amplifier circuit according to claim 1 or 2,
The operational amplifier is a 2-input 2-output operational amplifier having a first input node and a second input node, and a first output node and a second output node;
A first circuit configuration for the first input node and the first output node of the 2-input 2-output operational amplifier, and a second circuit configuration for the second input node and the second output node of the 2-input 2-output operational amplifier. 2 circuit configuration is the same,
The size of each of the plurality of switches used in the first circuit configuration and the capacitance value of each of the plurality of capacitors and the first circuit configuration used in the second circuit configuration are included. A fully differential amplifier circuit is configured by setting the size of each switch corresponding to each switch and the capacitance value of each capacitor corresponding to each capacitor included in the first circuit configuration to be the same. A switched capacitor amplifier circuit. The switched capacitor amplifier circuit according to claim 1,
A second input unit is provided in parallel with the first input unit between the signal input node and the input node of the operational amplifier,
The second input unit includes:
A second input capacitor provided between the signal input node and the input node of the operational amplifier; a plurality of switches for switching charge / discharge of the second input capacitor; the second input capacitor and the operational amplifier; A switch for switching connection / disconnection with the input node,
Each of the plurality of switches included in the second input unit is turned on / off in a complementary manner to each of the corresponding switches in the first input unit. The switched capacitor amplifier circuit according to claim 2, further comprising:
A ninth switch provided between the first node and the twelfth node as the signal input nodes and controlled to be turned on / off by the second clock;
A tenth switch provided between the twelfth node and a reference potential and controlled to be turned on / off by the first clock;
The second input capacitance connected between the twelfth node and the thirteenth node;
An eleventh switch provided between the thirteenth node and a reference potential and controlled to be turned on / off by the second clock;
A twelfth switch provided between the thirteenth node and the fourth node that is an input node of the operational amplifier, the on / off of which is controlled by the one clock;
A switched capacitor amplifier circuit comprising: A switched capacitor amplifier circuit according to claim 4 or 5,
The operational amplifier is a 2-input 2-output operational amplifier having a first input node and a second input node, and a first output node and a second output node;
A third circuit configuration for the first input node and the first output node of the 2-input 2-output operational amplifier, and a second circuit configuration for the second input node and the second output node of the 2-input 2-output operational amplifier. 4 circuit configuration is the same,
And the size of each of the plurality of switches used in the third circuit configuration and the capacitance value of each of the plurality of capacitors, and the third circuit configuration used in the fourth circuit configuration. A fully differential amplifier circuit is configured by setting the size of each switch corresponding to each switch and the capacitance value of each capacitor corresponding to each capacitor included in the third circuit configuration to be the same. A switched capacitor amplifier circuit. The switched capacitor amplifier circuit according to claim 3 or 6, further comprising:
A first offset cancellation capacitor provided between the first input node of the 2-input 2-output operational amplifier and the first input terminal of the 2-input 2-output operational amplifier;
A second offset cancellation capacitor provided between the second input node of the 2-input 2-output operational amplifier and the second input terminal of the 2-input 2-output operational amplifier;
A first short-circuit switch connected between the first input terminal and the first output node of the two-input two-output operational amplifier and controlled to be turned on / off by a short-circuit control signal;
A second short-circuit switch connected between the second input terminal and the second output node of the two-input two-output operational amplifier and controlled to be turned on / off by the short-circuit control signal;
Common control is performed on the two-input two-output operational amplifier so that a differential voltage between a common potential between the first output node and the second output node of the two-input two-output operational amplifier is reduced. A common mode feedback circuit that performs a common potential stabilization operation for stabilizing a common potential to the second reference potential by supplying a signal;
Have
An offset cancellation and common mode feedback period is provided after the sampling integration period and the amplification period,
In the offset cancellation and common mode feedback period,
The first short-circuit switch and the second short-circuit switch are turned on, and the first input node of the 2-input 2-output operational amplifier and the second input node of the 2-input 2-output operational amplifier are both maintained at a common potential,
And, the common potential stabilization operation by the common mode feedback circuit is executed.
A switched capacitor amplifier circuit. The switched capacitor amplifier circuit according to any one of claims 1 to 6,
A switched capacitor amplifier circuit, wherein the parameter n is changed to variably control the gain of the switched capacitor amplifier circuit. The switched capacitor amplifier circuit according to claim 8,
2. A switched capacitor amplifier circuit, wherein the second frequency clock is generated based on a clock obtained by dividing the first frequency clock by n by a frequency divider circuit. The switched capacitor amplifier circuit according to claim 8,
A switched capacitor amplifier circuit characterized in that the second frequency clock synchronized with the first frequency clock is generated based on a clock output from a voltage controlled oscillator. The switched capacitor amplifier circuit according to claim 8,
A voltage comparison circuit that compares a voltage of the output signal of the switched capacitor amplifier circuit with a predetermined voltage, and a voltage / frequency conversion circuit that converts the output voltage of the voltage comparison circuit into a frequency signal,
A switched capacitor amplifier circuit that generates a clock of the second frequency based on a clock signal output from the voltage / frequency converter circuit. A motion sensor,
The switched capacitor amplifier circuit according to any one of claims 1 to 11, wherein a detection signal output from the motion sensor is input;
A sensor device comprising:   An electronic apparatus comprising the switched capacitor amplifier circuit according to claim 1.

Images