JP2013153246A - Fully-differential amplifier circuit, comparator circuit, a/d conversion circuit, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fully-differential amplifier circuit, a comparator circuit, an A/D conversion circuit, an electronic apparatus, and the like capable of realizing a high-speed response at lower power consumption without an additional circuit.SOLUTION: A fully-differential amplifier circuit 10 includes a differential operational amplifier circuit 12, a common mode feedback circuit 14, and a reset circuit 16. The differential operational amplifier circuit 12 outputs a pair of differential output signals NOUT and POUT corresponding to a pair of differential input signals PIN and NIN to a pair of output nodes Nd1 and Nd2. The common mode feedback circuit 14 supplies voltage VC generated on the basis of the pair of differential output signals NOUT and POUT to a common mode feedback input node Nc of the differential operational amplifier circuit 12. The reset circuit 16 short-circuits the pair of output nodes Nd1 and Nd2 and the common mode feedback input node Nc.

Description

  The present invention relates to a fully differential amplifier circuit, a comparator circuit, an A / D conversion circuit, an electronic device, and the like.

  In recent years, various applications using sensing technology using sensors have appeared, and more accurate sensing technology is required. Therefore, an A / D conversion circuit that converts a physical quantity detected by a sensor into a digital value is required to have higher resolution. Various A / D conversion methods performed by the A / D conversion circuit have been proposed. Among them, a successive approximation type A / D conversion circuit or the like is known as an A / D conversion circuit capable of reducing power consumption and achieving higher resolution.

  This type of A / D conversion circuit includes a comparator circuit, and has a preamplifier circuit configured using a fully differential operational amplifier, thereby speeding up the response while providing noise immunity. be able to. In order to speed up the high-accuracy comparison operation of this comparator circuit, the history of the previous comparison operation remaining at each node can be reset at high speed each time the comparison operation is completed and the next comparison operation is started. desirable.

  In order to reset the comparator circuit, it is necessary to short-circuit the differential output of the preamplifier circuit to a predetermined intermediate potential. For example, Patent Document 1 discloses a technique in which the fluctuation of the initial potential due to the history of the next stage sampling capacitance is reset to 0 by short-circuiting the differential output of the differential operational amplifier for a short time.

JP 2010-74636 A

  However, when the differential output of the preamplifier circuit is short-circuited to a predetermined intermediate potential, it is necessary to prepare a replica circuit separately, which increases the area. Further, when a replica circuit is prepared separately, power consumption increases due to an increase in bias current.

  On the other hand, even if the technique disclosed in Patent Document 1 is used, the speed cannot be sufficiently increased only by short-circuiting the differential output of the differential operational amplifier, and can be fixed to a predetermined intermediate voltage. desirable. At this time, it is desirable that the intermediate voltage can be fixed without providing an additional circuit as much as possible.

  The present invention has been made in view of the above technical problems. According to some aspects of the present invention, a fully differential amplifier circuit, a comparator circuit, an A / D converter circuit, an electronic device, and the like that can respond at high speed with low power consumption without providing an additional circuit are provided. can do.

  (1) In a first aspect of the present invention, the fully differential amplifier circuit outputs a pair of differential output signals corresponding to the pair of differential input signals to a pair of output nodes; A common mode feedback circuit for supplying a voltage generated based on a pair of differential output signals to a common mode feedback input node of the differential operational amplifier circuit; and the pair of output nodes and the common mode A reset circuit that short-circuits the feedback input node is included.

  In this aspect, the reset circuit can short-circuit the pair of output nodes of the differential operational amplifier circuit and the common mode feedback input node of the differential operational amplifier circuit. By doing this, at the time of resetting, the common mode feedback input node of the differential operational amplifier circuit is fixed to a predetermined voltage without largely changing the operating point of the differential operational amplifier circuit with feedback applied. Can do. At this time, for example, the common mode feedback input node of the differential operational amplifier circuit can be fixed to a predetermined voltage without using a resistance element constituting the common mode feedback circuit. This eliminates the need to add a new configuration in addition to the common mode feedback circuit required in the fully differential amplifier circuit. Therefore, for example, it is not necessary to prepare a separate replica circuit, and it is possible to provide a fully differential amplifier circuit that can respond at high speed with low power consumption without causing an increase in area or power consumption. .

  (2) In the fully differential amplifier circuit according to the second aspect of the present invention, in the first aspect, the common mode feedback circuit includes a resistance divider circuit that resistance-divides the voltage between the pair of output nodes. And a voltage obtained by resistance-dividing the voltage between the pair of output nodes by the resistor divider circuit is output to the common mode feedback input node.

  In this aspect, the common mode feedback circuit outputs the voltage obtained by resistance-dividing the voltage between the pair of output nodes of the differential operational amplifier circuit to the common mode feedback input node. Thereby, in addition to the above effects, the following effects can be obtained. First, compared to the case where the common mode feedback circuit is realized by a switched capacitor circuit, the configuration is simplified and a special start-up sequence is not required, and it is easy to perform intermittent operation in the fully differential amplifier circuit. Become. Second, the common mode feedback circuit is connected to the output of the differential operational amplifier circuit. Therefore, although it becomes a load resistance and the gain of the fully differential amplifier circuit is lowered, it works effectively in an application where it is desired to keep the gain low, and output noise can be suppressed when used in an open loop.

  (3) In a third aspect of the present invention, the fully differential amplifier circuit outputs a pair of differential output signals corresponding to the pair of differential input signals to a pair of output nodes; A common mode feedback circuit for supplying a voltage generated based on a pair of differential output signals to a common mode feedback input node of the differential operational amplifier circuit, the common mode feedback circuit comprising: A resistance dividing circuit for resistance-dividing between the pair of output nodes, and a voltage obtained by amplifying a voltage corresponding to a difference between a voltage obtained by the resistance dividing circuit and a given reference voltage, and the common mode feedback input An amplifier circuit that outputs to the node; and a reset circuit that short-circuits the pair of output nodes and the input node of the amplifier circuit.

  In this aspect, the common mode feedback circuit generates a given voltage based on the voltage between the pair of output nodes of the differential operational amplifier circuit. The amplifier circuit can amplify a voltage corresponding to the difference between the voltage and the reference voltage, and apply feedback to the common mode feedback input node of the differential operational amplifier circuit. The reset circuit can short-circuit the pair of output nodes and the input node of the amplifier circuit. By doing this, at the time of resetting, the common mode feedback input node of the differential operational amplifier circuit is fixed to a predetermined voltage without largely changing the operating point of the differential operational amplifier circuit with feedback applied. Can do. At this time, for example, the common mode feedback input node of the differential operational amplifier circuit can be fixed to a predetermined voltage without using a resistance element constituting the common mode feedback circuit. This eliminates the need to add a new configuration in addition to the common mode feedback circuit required in the fully differential amplifier circuit. Therefore, for example, it is not necessary to prepare a separate replica circuit, and it is possible to provide a fully differential amplifier circuit that can respond at high speed with low power consumption without causing an increase in area or power consumption. .

  (4) In the fully differential amplifier circuit according to the fourth aspect of the present invention, in any one of the first aspect to the third aspect, the reset circuit includes the pair of output nodes, the common mode circuit, A feedback input node or the input node of the amplifier circuit is shorted during a given reset period.

  In this aspect, the reset circuit is provided between the pair of output nodes of the differential operational amplifier circuit and the common mode feedback input node or between the pair of output nodes of the differential operational amplifier circuit and the amplifier circuit only during the reset period. Short-circuit between input nodes. Therefore, in the amplifying operation period which is a non-reset period, it can be operated as a conventional fully differential amplifier circuit. Therefore, it is possible to provide a fully-differential amplifier circuit that can respond at high speed with low power consumption without greatly adding a new configuration.

  (5) According to a fifth aspect of the present invention, in the comparator circuit, the fully differential amplifier circuit according to any one of the first to fourth aspects and the pair of differentials of the fully differential amplifier circuit are provided. A dynamic latch comparator circuit to which an output signal is input.

  According to this aspect, since the above-described fully differential amplifier circuit is applied, it is possible to provide a comparator circuit that can respond at high speed with low power consumption.

  (6) According to a sixth aspect of the present invention, a comparator circuit includes a first fully differential amplifier circuit and a second fully differential amplifier circuit connected to the output of the first fully differential amplifier circuit. And a dynamic latch comparator circuit connected to the output of the second fully differential amplifier circuit, and at least one of the first fully differential amplifier circuit and the second fully differential amplifier circuit includes: A fully differential amplifier circuit according to any one of the first to fourth aspects.

  According to this aspect, since the signal input to the dynamic latch comparator circuit is amplified by the plurality of fully differential amplifier circuits, it is not necessary to significantly increase the gain of each fully differential amplifier circuit. Thereby, each fully differential amplifier circuit can suppress the amplification of noise, and can provide a comparator circuit that can operate at high speed with high accuracy.

  (7) According to a seventh aspect of the present invention, in the A / D conversion circuit, the register value is updated according to the comparison result between the comparator circuit of the fifth aspect or the sixth aspect and the comparator circuit. A comparison approximation register; a D / A conversion circuit that outputs an analog signal corresponding to the register value; and a sample-and-hold circuit that samples and holds an input signal. The comparator circuit is held by the sample-and-hold circuit. The generated signal is compared with the analog signal.

  According to this aspect, it is possible to provide an A / D conversion circuit that can respond at high speed with low power consumption without providing an additional circuit.

  (8) According to an eighth aspect of the present invention, an electronic device includes the fully differential amplifier circuit according to any one of the first to fourth aspects.

  According to this aspect, it is possible to provide an electronic apparatus to which a fully differential amplifier circuit capable of high-speed response with low power consumption is provided without providing an additional circuit.

  (9) In a ninth aspect of the present invention, an electronic device includes the A / D conversion circuit of the seventh aspect.

  According to this aspect, it is possible to provide an electronic device to which an A / D conversion circuit capable of high-speed response with low power consumption is provided without providing an additional circuit.

The figure which shows the structural example of the fully differential amplifier circuit in 1st Embodiment based on this invention. The circuit diagram of the example of composition of the fully differential amplifier circuit in a 1st embodiment. The figure which shows the structural example of the fully differential amplifier circuit in the comparative example of 1st Embodiment. The figure which shows an example of the simulation result of the fully differential amplifier circuit in the comparative example of 1st Embodiment. The figure which shows an example of the simulation result of the fully differential amplifier circuit in 1st Embodiment. The circuit diagram of the example of composition of the fully differential amplifier circuit in the modification of a 1st embodiment. The figure which shows the structural example of the fully differential amplifier circuit in 2nd Embodiment which concerns on this invention. The figure which shows the structural example of the comparator circuit in one Embodiment which concerns on this invention. The figure which shows the structural example of the A / D conversion circuit in one Embodiment which concerns on this invention. FIG. 5 is an operation explanatory diagram of an A / D conversion circuit. FIG. 11A is a diagram illustrating an example of timings of the reference clock CLK, the conversion clock SC, the switch control signal RES, and the latch signal LATCH. FIG. 11B is an enlarged view of a portion of a range WD in FIG. The block diagram of the hardware structural example of the electronic device in one Embodiment which concerns on this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, all of the configurations described below are not necessarily indispensable configuration requirements for solving the problems of the present invention.

[Fully differential amplifier circuit]
[First Embodiment]
FIG. 1 shows a configuration example of a fully differential amplifier circuit according to the first embodiment of the present invention.

  The fully differential amplifier circuit 10 in the first embodiment includes a differential operational amplifier circuit 12, a common mode feedback (hereinafter referred to as CMFB) circuit 14, and a reset circuit 16. The differential operational amplifier circuit 12 amplifies the difference between the pair of differential input signals PIN and NIN, and converts the pair of differential output signals NOUT and POUT corresponding to the differential input signals PIN and NIN into a pair of output nodes Nd1 and Nd2. Output to. The CMFB circuit 14 supplies a voltage VC generated based on the pair of differential output signals NOUT and POUT to the common mode feedback input node Nc of the differential operational amplifier circuit 12. In the differential operational amplifier circuit 12, the operating point of the differential operational amplifier circuit 12 is determined according to the voltage of the common mode feedback input node Nc. The reset circuit 16 short-circuits the pair of output nodes Nd1 and Nd2 and the common mode feedback input node Nc during a reset period provided before the amplification operation period.

  The CMFB circuit 14 includes a resistance dividing circuit 15 that performs resistance division between the pair of output nodes Nd1 and Nd2. The resistance dividing circuit 15 includes resistance elements R1 and R2. One end of the resistor element R1 is connected to the output node Nd1, and the other end is connected to the common mode feedback input node Nc. One end of the resistance element R2 is connected to the common mode feedback input node Nc, and the other end is connected to the output node Nd2. The CMFB circuit 14 having such a configuration outputs a voltage VC obtained by resistance dividing the voltage between the pair of output nodes Nd1 and Nd2 by the resistance dividing circuit 15 to the common mode feedback input node Nc.

  Since the CMFB circuit 14 is realized by the resistance dividing circuit 15, the configuration is simplified and a special activation sequence is not required as compared with the case where the CMFB circuit 14 is realized by a switched capacitor circuit. It becomes easy to perform an intermittent operation in. In addition, since the CMFB circuit 14 is connected to the output of the differential operational amplifier circuit 12, it becomes a load resistance and reduces the gain of the fully differential amplifier circuit 10. However, the CMFB circuit 14 works effectively in applications where it is desired to keep the gain low. When used in an open loop, output noise can be suppressed.

  The reset circuit 16 includes switch elements SW1 and SW2. One end of the switch element SW1 is connected to the output node Nd1, and the other end is connected to the common mode feedback input node Nc. One end of the switch element SW2 is connected to the common mode feedback input node Nc, and the other end is connected to the output node Nd2. The switch elements SW1 and SW2 are switch-controlled so as to be simultaneously turned on during the reset period, and are controlled to be simultaneously turned off during the amplification operation period. The switch elements SW1 and SW2 are switch-controlled by a switch control signal RES.

  FIG. 2 shows a circuit diagram of a configuration example of the fully differential amplifier circuit 10 in the first embodiment. In FIG. 2, the same parts as those in FIG.

  The fully differential amplifier circuit 10 includes P-type metal oxide semiconductor (hereinafter referred to as MOS) transistors QP1, QP2, and QP3, and N-type MOS transistors QN1 and QN2. The differential operational amplifier circuit 12 of FIG. 1 is configured by the MOS transistors QP1, QP2, QP3, QN1, and QN2.

  The MOS transistor QP1 has a source connected to the high potential side power supply, a drain connected to the sources of the MOS transistors QP2 and QP3, and a gate supplied with the gate signal Vb. The voltage of the high potential side power supply is the voltage VDDA. In the MOS transistor QP2, the output node Nd1 is connected to the drain, and the differential input signal PIN is supplied to the gate. In the MOS transistor QP3, the output node Nd2 is connected to the drain, and the differential input signal NIN is supplied to the gate.

  The MOS transistor QN1 has a source connected to the low potential side power supply, a drain connected to the output node Nd1, and a gate connected to the common mode feedback input node Nc. The voltage of the low potential side power supply is assumed to be the voltage GND. The MOS transistor QN2 has a source connected to the low potential side power supply, a drain connected to the output node Nd2, and a gate connected to the common mode feedback input node Nc.

  The resistance elements R1 and R2 constituting the CMFB circuit 14 of FIG. 1 and the switch elements SW1 and SW2 constituting the reset circuit 16 are connected as shown in FIG.

  In the fully differential amplifier circuit 10 having the above-described configuration, the differential operational amplifier circuit 12 constituted by the MOS transistors QP1, QP2, QP3, QN1, and QN2 is a known differential operational amplifier circuit. Therefore, description of the operation of the differential operational amplifier circuit 12 is omitted. In such a differential operational amplifier circuit 12, during the amplification operation period, feedback is applied by the CMFB circuit 14 so as to be a signal in the vicinity of the intermediate voltage between the pair of differential output signals NOUT and POUT. In this state, the differential operational amplifier circuit 12 outputs differential output signals NOUT and POUT corresponding to the difference between the differential input signals PIN and NIN.

  In the first embodiment, in order to repeat the amplification operation at high speed, a reset period is provided so that the state of the previous amplification operation (history remaining in each node) is reset at the start timing of each amplification operation period. It is done. In this reset period, in the reset circuit 16, the switch elements SW1 and SW2 are turned on by the switch control signal RES. As a result, the output nodes Nd1 and Nd2 are short-circuited, and the output nodes Nd1 and Nd2 are connected to the common mode feedback input node Nc of the differential operational amplifier circuit 12. Therefore, the common mode feedback input node Nc of the differential operational amplifier circuit 12 can be fixed to a predetermined voltage without largely changing the operating point of the differential operational amplifier circuit 12 in a state where feedback is applied. At this time, the common mode feedback input node Nc of the differential operational amplifier circuit 12 can be fixed to a predetermined voltage without passing through the resistance elements R1 and R2 constituting the CMFB circuit 14.

  When the amplification operation period is started after the reset period, in the reset circuit 16, the switch elements SW1 and SW2 are turned off by the switch control signal RES, and the output nodes Nd1 and Nd2 are electrically cut off. Therefore, in the amplification operation period, the differential operational amplifier circuit 12 determines the difference between the differential input signals PIN and NIN while the voltage VC generated by the CMFB circuit 14 is supplied to the common mode feedback input node Nc. Corresponding differential output signals NOUT and POUT are output.

[Comparative example]
Here, a fully differential amplifier circuit in a comparative example of the first embodiment will be described.

  FIG. 3 shows a configuration example of a fully differential amplifier circuit in a comparative example of the first embodiment. In FIG. 3, the same parts as those in FIG.

  The fully differential amplifier circuit 10a in the comparative example of the first embodiment includes a differential operational amplifier circuit 12, a CMFB circuit 14, and a reset circuit 18a. The differential operational amplifier circuit 12 includes, for example, the MOS transistors QP1, QP2, QP3, QN1, and QN2 of FIG. Reset circuit 18a includes a switch element SWa inserted between a pair of output nodes Nd1 and Nd2. For example, the switch element SWa is switch-controlled to be turned on during the reset period, and is controlled to be turned off during the amplification operation period. The switch element SWa is switch-controlled by a switch control signal RES.

  The configuration of the fully differential amplifier circuit 10a is different from the configuration of the fully differential amplifier circuit 10 in that the reset circuit 16 is replaced with a reset circuit 18a. Therefore, the fully differential amplifier circuit 10a is generated by the CMFB circuit 14 at the common mode feedback input node Nc of the differential operational amplifier circuit 12 during the reset period and the amplification operation period. A voltage VC is supplied.

  That is, in this comparative example, when the reset period is started, the switch element SWa is turned on by the switch control signal RES, and the voltage of the output nodes Nd1 and Nd2 is divided by resistance through the resistance elements R1 and R2. Feedback is applied by voltage. At this time, the voltage change of the common mode feedback input node Nc is delayed by a predetermined time. This time corresponds to a time constant determined by the resistance element R1 or the resistance element R2 constituting the CMFB circuit 14 and the gate capacitance of the MOS transistor connected to the common mode feedback input node Nc.

  In the amplification operation period after the reset period, the switch element SWa is turned off by the switch control signal RES, and the output nodes Nd1 and Nd2 are electrically cut off. At this time, with the common mode feedback input node Nc supplied with the voltage VC obtained by resistance-dividing the voltages of the output nodes Nd1 and Nd2, the differential operational amplifier circuit 12 receives the differential input signals PIN and NIN. Differential output signals NOUT and POUT corresponding to the difference are output.

  FIG. 4 shows an example of a simulation result of the fully-differential amplifier circuit 10a in the comparative example of the first embodiment. FIG. 4 shows an example of changes in voltage VC and differential output signals NOUT and POUT, with the vertical axis representing voltage and the horizontal axis representing time. FIG. 4 shows a simulation result when the voltage between the high potential side power supply voltage and the low potential side power supply voltage is 3.0V.

  It is assumed that the switch element SWa of the reset circuit 18a is turned on when the switch control signal RES is at H level. In the amplifying operation period, the switch control signal RES becomes L level, and the differential operational amplifier circuit 12 outputs differential output signals NOUT and POUT corresponding to the difference between the differential input signals PIN and NIN. For example, as shown in FIG. 4, when the potential of the differential output signal NOUT increases, the potential of the differential output signal POUT decreases, and the amplification operation period ends, the reset period starts before the next amplification operation period. The

  In this reset period, the switch control signal RES is at H level and the switch element SWa is turned on. Then, the output nodes Nd1 and Nd2 are short-circuited, and the differential output signals NOUT and POUT become signals having the same potential. At this time, the CMFB circuit 14 supplies, to the common mode feedback input node Nc, a voltage VC obtained by resistance-dividing the voltages of the differential output signals NOUT and POUT. However, a voltage is supplied to the common mode feedback input node Nc via the resistance elements R1 and R2 constituting the CMFB circuit. Therefore, it takes time, for example, time T1 in FIG. 4 until the voltage change of the common mode feedback input node Nc settles.

  In contrast, in the first embodiment, the common mode feedback input node Nc of the differential operational amplifier circuit 12 is fixed to a predetermined voltage without passing through the resistance elements R1 and R2 constituting the CMFB circuit 14. be able to.

  FIG. 5 shows an example of a simulation result of the fully differential amplifier circuit 10 according to the first embodiment. FIG. 5 shows an example of changes in voltage VC and differential output signals NOUT and POUT, with the vertical axis representing voltage and the horizontal axis representing time. FIG. 5 shows a simulation result when the voltage between the high potential side power supply voltage and the low potential side power supply voltage is 3.0V.

  It is assumed that the switch elements SW1 and SW2 of the reset circuit 16 are turned on when the switch control signal RES is at H level. In the amplifying operation period, the switch control signal RES becomes L level, and the differential operational amplifier circuit 12 outputs differential output signals NOUT and POUT corresponding to the difference between the differential input signals PIN and NIN. For example, as shown in FIG. 5, when the potential of the differential output signal NOUT increases, the potential of the differential output signal POUT decreases, and the amplification operation period ends, a reset period is started before the next amplification operation period. The

  In this reset period, the switch control signal RES is at the H level, and the switch elements SW1 and SW2 are turned on. Then, the output nodes Nd1 and Nd2 are short-circuited, the differential output signals NOUT and POUT become signals of the same potential, and the output nodes Nd1 and Nd2 are connected to the common mode feedback input node Nc of the differential operational amplifier circuit 12. Connected to. Therefore, in the first embodiment, the voltage is fixed to a given intermediate voltage without passing through the resistance elements R1 and R2 constituting the CMFB circuit 14. This intermediate potential is an intermediate potential between the differential output signals NOUT and POUT obtained by the common mode feedback input node Nc short-circuiting the output nodes Nd1 and Nd2. As a result, the potential of the common mode feedback input node Nc is substantially fixed, for example, at time T2 in FIG. 5, and the reset period can be shortened when compared with this comparative example.

  As described above, according to the first embodiment, the common operation of the differential operational amplifier circuit 12 can be performed without significantly adding a new configuration in addition to the CMFB circuit necessary for the fully differential amplifier circuit. The mode feedback input node Nc can be fixed at a predetermined voltage at high speed. As a result, for example, there is no need to separately prepare a replica circuit, and a fully differential amplifier circuit capable of high-speed response with low power consumption without causing an increase in area or power consumption can be provided. Become.

[Modification]
In the first embodiment, the differential operational amplifier circuit 12 has been described in which the differential input signals PIN and NIN are supplied to the gates of the P-type MOS transistors. However, the first embodiment is limited to this. Is not to be done.

  FIG. 6 shows a circuit diagram of a configuration example of a fully differential amplifier circuit in a modification of the first embodiment. In FIG. 6, the same parts as those in FIG.

  The fully differential amplifier circuit 20 in the modification of the first embodiment includes N-type MOS transistors QN10, QN11, and QN12, and P-type MOS transistors QP10 and QP11. The differential operational amplifier circuit 12 of FIG. 1 is configured by the MOS transistors QN10, QN11, QN12, QP10, and QP11.

  The MOS transistor QN10 has a source connected to the low potential power source, a drain connected to the sources of the MOS transistors QN11 and QN12, and a gate supplied with the gate signal Vb ′. In the MOS transistor QN11, the output node Nd1 is connected to the drain, and the differential input signal PIN is supplied to the gate. In the MOS transistor QN12, the output node Nd2 is connected to the drain, and the differential input signal NIN is supplied to the gate.

  The MOS transistor QP10 has a source connected to the high potential side power supply, a drain connected to the output node Nd1, and a gate connected to the common mode feedback input node Nc. The MOS transistor QP11 has a source connected to the high potential side power supply, a drain connected to the output node Nd2, and a gate connected to the common mode feedback input node Nc.

  The resistance elements R1 and R2 constituting the CMFB circuit 14 of FIG. 1 and the switch elements SW1 and SW2 constituting the reset circuit 16 are connected as shown in FIG.

  In the fully differential amplifier circuit 20 having the above-described configuration, the differential operational amplifier circuit 12 including the MOS transistors QN10, QN11, QN12, QP10, and QP11 is a known differential operational amplifier circuit. Accordingly, during the amplifying operation period, the differential operational amplifier circuit 12 is fed back by the CMFB circuit 14 so as to become a signal in the vicinity of the intermediate voltage between the pair of differential output signals NOUT and POUT. In this state, the differential operational amplifier circuit 12 outputs differential output signals NOUT and POUT corresponding to the difference between the differential input signals PIN and NIN.

  Therefore, in the present modification, as in the first embodiment, in the reset period, the switch control signal RES is at the H level and the switch elements SW1 and SW2 are turned on. Then, the output nodes Nd1 and Nd2 are short-circuited, the differential output signals NOUT and POUT become signals of the same potential, and the output nodes Nd1 and Nd2 are connected to the common mode feedback input node Nc of the differential operational amplifier circuit 12. Connected to. Therefore, in the present modification, as in the first embodiment, the common mode feedback input node Nc is connected to the differential output signals NOUT and POUT without using the resistance elements R1 and R2 constituting the CMFB circuit 14. Fixed to an intermediate voltage. As a result, the common mode feedback input node Nc is fixed at a predetermined voltage at a high speed, and the reset period can be shortened as in the first embodiment.

  As described above, according to the present modification, the common mode circuit of the differential operational amplifier circuit 12 can be obtained without significantly adding a new configuration in addition to the CMFB circuit necessary for the fully differential amplifier circuit. The feedback input node Nc can be fixed at a predetermined voltage at high speed. As a result, for example, there is no need to separately prepare a replica circuit, and a fully differential amplifier circuit capable of high-speed response with low power consumption without causing an increase in area or power consumption can be provided. Become.

[Second Embodiment]
In the first embodiment or the modification thereof, the example in which the CMFB circuit 12 is configured by a resistance divider circuit has been described, but the configuration of the CMFB circuit is not limited to this.

  FIG. 7 shows a configuration example of a fully differential amplifier circuit according to the second embodiment of the present invention. 7, parts that are the same as those in FIG. 1 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

  The fully differential amplifier circuit 30 in the second embodiment includes a differential operational amplifier circuit 12 and a CMFB circuit 40. The differential operational amplifier circuit 12 is configured by MOS transistors QP1, QP2, QP3, QN1, and QN2 as in the first embodiment. Further, the differential operational amplifier circuit 12 may be configured by MOS transistors QN10, QN11, QN12, QP10, and QP11 as in the modification of the first embodiment. The CMFB circuit 40 supplies a voltage VC generated based on the pair of differential output signals NOUT and POUT to the common mode feedback input node Nc of the differential operational amplifier circuit 12.

  The CMFB circuit 40 includes a resistance dividing circuit 15, an amplifier circuit 42, and a reset circuit 44. The resistance dividing circuit 15 includes resistance elements R1 and R2 as in the first embodiment (or a modification thereof), and each resistance element is connected in the same manner as in the first embodiment (or a modification thereof). . The amplifying circuit 42 outputs a voltage obtained by amplifying a voltage corresponding to the difference between the voltage obtained by the resistance dividing circuit 15 and a given reference voltage Vcm to the common mode feedback input node Nc.

  The reset circuit 44 includes switch elements SW1 and SW2, and short-circuits the pair of output nodes Nd1 and ND2 and the input node Ne of the inverting input terminal of the amplifier circuit 42. The switch element SW1 is provided between the output node Nd1 and the input node Ne. The switch element SW2 is provided between the output node Nd2 and the input node Ne. The switch elements SW1 and SW2 are switch-controlled so as to be simultaneously turned on during the reset period, and are controlled to be simultaneously turned off during the amplification operation period. The switch elements SW1 and SW2 are switch-controlled by a switch control signal RES.

  Note that the CMFB circuit 40 does not have to be configured to include the resistance dividing circuit 15 and the reset circuit 44, as shown in FIG. For example, the reset circuit 44 may be provided outside the CMFB circuit 40.

  In the second embodiment, during the reset period, in the reset circuit 44, the switch elements SW1 and SW2 are turned on by the switch control signal RES. Thereby, the output nodes Nd1 and Nd2 are short-circuited. The amplifier circuit 42 amplifies a voltage corresponding to the difference between the intermediate voltage of the differential output signals NOUT and POUT and the reference voltage Vcm, and applies feedback to the common mode feedback input node Nc of the differential operational amplifier circuit 12. be able to. Therefore, the common mode feedback input node Nc of the differential operational amplifier circuit 12 can be fixed to a predetermined voltage without largely changing the operating point of the differential operational amplifier circuit 12 in a state where feedback is applied. At this time, the common mode feedback input node Nc of the differential operational amplifier circuit 12 can be fixed to a predetermined voltage without passing through the resistance elements R1 and R2 constituting the CMFB circuit 14.

  When the amplification operation period is started after the reset period, in the reset circuit 44, the switch elements SW1 and SW2 are turned off by the switch control signal RES, and the output nodes Nd1 and Nd2 are electrically cut off. Accordingly, during the amplification operation period, the CMFB circuit 40 can apply feedback to the common mode feedback input node Nc according to the difference between the voltage obtained by resistance-dividing the differential output signals NOUT and POUT and the reference voltage Vcm. . Thereby, the average voltage of the differential output signals NOUT and POUT can be made near the reference voltage Vcm.

  Therefore, according to the second embodiment, the common mode feedback input node Nc of the differential operational amplifier circuit 12 can be set without significantly adding a new configuration except that the amplifier circuit 42 is provided in addition to the CMFB circuit. It can be fixed at a predetermined voltage at high speed. As a result, for example, there is no need to separately prepare a replica circuit, and a fully differential amplifier circuit capable of high-speed response with low power consumption without causing an increase in area or power consumption can be provided. Become.

[Comparator circuit]
The fully differential amplifier circuit according to the first embodiment or the modification thereof and the second embodiment can be applied to a comparator circuit that can operate at high speed with low power consumption.

  FIG. 8 shows a configuration example of a comparator circuit in one embodiment according to the present invention. In FIG. 8, the same parts as those in FIG.

  The comparator circuit 50 includes a first fully differential amplifier circuit 52, a second fully differential amplifier circuit 54, a dynamic latch comparator circuit 60, offset cancel capacitors C1 and C2, and switch elements SW10 and SW11. It has. The first fully differential amplifier circuit 52 and the second fully differential amplifier circuit 54 operate as a preamplifier circuit.

  The first fully differential amplifier circuit 52 has the same configuration as any of the above-described fully differential amplifier circuits 10, 20, and 30. Similarly, the second fully differential amplifier circuit 54 has the same configuration as any of the fully differential amplifier circuits 10, 20, and 30 described above. In the following, it is assumed that each of the first fully differential amplifier circuit 52 and the second fully differential amplifier circuit 54 has the same configuration as the fully differential amplifier circuit 10.

  A pair of differential input signals PIN and NIN are input to the first fully differential amplifier circuit 52. The second fully differential amplifier circuit 54 is connected to the output of the first fully differential amplifier circuit 52 in cascade. Specifically, the pair of output nodes (Nd1, Nd2) of the first fully-differential amplifier circuit 52 is connected to the second fully-differential so that the polarity is inverted via the offset cancel capacitors C1, C2, respectively. A pair of input nodes of the amplifier circuit 54 are connected. Each of the switch elements SW10 and SW11 is provided between an input node of the second fully differential amplifier circuit 54 and an output node corresponding thereto.

  The offset cancel capacitors C1 and C2 cancel the difference in offset between the first fully differential amplifier circuit 52 and the second fully differential amplifier circuit 54. Specifically, the switch elements SW10 and SW11 are turned on to charge each offset cancel capacitor in advance with a charge corresponding to the offset difference between the first fully differential amplifier circuit 52 and the second fully differential amplifier circuit 54. Let me. Then, with the switch elements SW10 and SW11 turned off, the differential output signal of the first fully differential amplifier circuit 52 is transmitted to the second fully differential amplifier circuit 54 via the offset cancel capacitors C1 and C2. Thus, the offset difference between the first fully differential amplifier circuit 52 and the second fully differential amplifier circuit 54 is canceled, and a more accurate differential output is output from the second fully differential amplifier circuit 54. A signal can be obtained.

  The dynamic latch comparator circuit 60 includes a comparator circuit that compares a potential difference between a pair of differential output signals of the second fully differential amplifier circuit 54 and a latch circuit that holds a comparison result of the comparator circuit. . This comparator circuit has two inverter circuits and has a latch structure in which one input and the other output are connected. The current that drives these inverter circuits is applied to the positive and negative input terminals of the comparator. The configuration is controlled by voltage. When the latch signal LATCH is at L level, the output of each inverter circuit is at H level and is in a reset state. At the moment when the latch signal LATCH becomes H level, the output of the inverter circuit having the higher driving ability of the two inverter circuits first changes to L level, and the other inverter circuit becomes L level input. It is latched in this state without changing from the level. The output of the inverter circuit of the comparator circuit is input to the latch circuit and plays a role of holding the state for one cycle of the latch signal LATCH.

  In FIG. 8, both the first fully differential amplifier circuit 52 and the second fully differential amplifier circuit 54 include the fully differential amplifier circuit 10 according to the first embodiment and the fully differential amplifier according to the modification. It has been described that the circuit 20 or the fully-differential amplifier circuit 30 in the second embodiment is applied. However, only one of the first fully differential amplifier circuit 52 and the second fully differential amplifier circuit 54 includes the fully differential amplifier circuit 10 in the first embodiment, the fully differential amplifier circuit 20 in the modification, Alternatively, the fully-differential amplifier circuit 30 in the second embodiment may be applied.

  In FIG. 8, the comparator circuit 50 has been described as an example in which the first fully differential amplifier circuit 52 and the second fully differential amplifier circuit 54 are provided before the dynamic latch comparator circuit 60. It is not limited. The comparator circuit 50 may have a configuration in which only the first fully differential amplifier circuit 52 or the second fully differential amplifier circuit 54 is provided before the dynamic latch comparator circuit 60. However, when the differential input signal is amplified by two fully differential amplifier circuits before the dynamic latch comparator circuit 60, it is not necessary to significantly increase the gain of each fully differential amplifier circuit. Thereby, each fully differential amplifier circuit can suppress the amplification of noise, and can provide a comparator circuit that can operate at high speed with high accuracy.

[A / D conversion circuit]
The comparator circuit 50 in FIG. 8 can be applied to an A / D conversion circuit that can operate at high speed with low power consumption.

  FIG. 9 shows a configuration example of an A / D conversion circuit according to an embodiment of the present invention. 9, parts that are the same as those in FIG. 8 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

  The A / D conversion circuit 100 in this embodiment is a so-called successive approximation type A / D conversion circuit. The A / D conversion circuit 100 includes a sample hold circuit 70, a comparator circuit 50, a comparison / approximation register 72, and a D / A conversion circuit 74. The sample hold circuit 70 samples and holds the input signal IN.

  The comparator circuit 50 compares the input signal after sampling held by the sample hold circuit 70 with the analog signal output from the D / A conversion circuit 74. As the differential input signal PIN of the comparator circuit 50, for example, a signal from the sample hold circuit 70 is input. For example, an analog signal output from the D / A conversion circuit 74 is input as the differential input signal NIN of the comparator circuit 50.

  In the comparison approximation register 72, the register value is updated according to the comparison result of the comparator circuit 50. The D / A conversion circuit 74 outputs an analog signal corresponding to the register value of the comparison approximation register 72. The register value of the comparison approximation register 72 after a series of A / D conversion operations is output as an output signal OUT that is a digital value corresponding to the input signal IN.

  FIG. 10 shows an operation explanatory diagram of the A / D conversion circuit 100. FIG. 10 schematically shows changes in the output signal P1 of the sample hold circuit 70 and the output signal P2 of the D / A conversion circuit 74 input to the comparator circuit 50, with time on the horizontal axis and voltage on the vertical axis. It is a representation.

  As shown in FIG. 10, it is assumed that the input signal IN is an analog signal (P2) having a predetermined voltage level. First, the D / A conversion circuit 74 outputs an analog signal corresponding to the initial value (P1) of the comparison approximation register 72, and the comparator circuit 50 compares the two analog signals. Based on the comparison result of the comparator circuit 50, the most significant bit of the register value of the comparison approximation register 72 is updated. Thereafter, the D / A conversion circuit 74 outputs an analog signal corresponding to the updated register value of the comparison approximation register 72, and the comparator circuit 50 compares the two analog signals. In this way, the comparator circuit 50 is operated by a predetermined number of bits, and the A / D conversion circuit 100 can output the output signal OUT that is a digital value corresponding to the input signal IN.

  11A and 11B show an example of operation timing of the A / D conversion circuit 100 in FIG. FIG. 11A shows an example of the timing of the reference clock CLK, the conversion clock SC, the switch control signal RES, and the latch signal LATCH. FIG. 11B is an enlarged view of the range WD in FIG. 11A, and the conversion clock SC is not shown. The conversion clock SC, the switch control signal RES, and the latch signal LATCH are generated based on the reference clock CLK.

  The A / D conversion circuit 100 outputs an output signal OUT corresponding to the input signal IN, which is an analog signal, within an A / D conversion operation period of one cycle period of the conversion clock SC. When the conversion clock SC is at the H level and the reference clock CLK rises, a transition is made from a sampling period in which the signal input IN is sampled to a comparison operation period in which the comparator circuit 50 operates. In the comparison operation period, the comparator circuit 50 performs the comparison operation at the rising timing of the latch signal LATCH by the same number of times as the resolution of the A / D conversion circuit 100. In the comparison operation period, the switch control signal RES changes from the H level to the L level after the wait period W0 and after the reset period W1 of the fully differential amplifier circuit elapses at the rising edge of the reference clock CLK.

  When the switch control signal RES is at the H level, the fully differential amplifier circuit constituting the comparator circuit 50 is initialized as described above. At this time, a pair of output nodes of the differential operational amplifier circuit is connected to the common mode feedback input node Nc of the differential operational amplifier circuit constituting the fully differential amplifier circuit without passing through the resistance element of the CMFB circuit. A shorted voltage is supplied. Therefore, the common mode feedback input node Nc of the differential operational amplifier circuit constituting the fully differential amplifier circuit can be fixed at a predetermined voltage at high speed, and the reset period W1 can be shortened. .

  When the switch control signal becomes L level, the LATCH signal also changes from H level to L level, and the amplification operation period W2 of the fully differential amplifier circuit is started. In this amplification operation period, the comparator circuit 50 performs an amplification operation corresponding to the difference between the signal from the sample hold circuit 70 and the analog signal from the D / A conversion circuit 74.

  At timing W3, the comparator circuit 50 latches the comparison result between the signal from the sample hold circuit 70 and the analog signal from the D / A conversion circuit 74 in the dynamic latch comparator circuit. Timing W3 is a timing at which the latch signal LATCH changes from the L level to the H level.

  After that, the comparison approximation register 72 captures the comparison result of the comparator circuit 50 at the next rising timing W4 of the reference clock CLK. Thereafter, the comparison / approximation register 72 outputs to the D / A conversion circuit 74 the register value updated by the comparison result fetched at the timing W4.

  Thereafter, similarly, the A / D conversion operation is repeated a predetermined number of times, and the A / D conversion circuit 100 can output the output signal OUT which is a digital value corresponding to the input signal IN.

  As described above, according to the A / D conversion circuit 100 of FIG. 9, it is possible to provide an A / D conversion circuit that can respond at high speed with low power consumption without providing an additional circuit. .

〔Electronics〕
The A / D conversion circuit 100 can be mounted on the following electronic device. According to such an electronic device, processing using an analog signal can be realized at high speed with low power consumption.

  FIG. 12 shows a block diagram of a hardware configuration example of an electronic device according to an embodiment of the present invention. In FIG. 12, the same parts as those in FIG.

  The electronic device 200 includes a sensor circuit 110, an A / D conversion circuit 100, a clock generation circuit 120, a processing unit 130 such as a central processing unit, a memory 140, an operation unit 150, and a display unit 160. ing. Each part which comprises the electronic device 200 is mutually connected by the bus | bath (BUS). The A / D conversion circuit 100 may be built in the processing unit 130.

  For example, the processing unit 130 executes processing in accordance with a program read from the memory 140, the sensor circuit 110 detects an angular velocity signal, outputs the detection signal at a voltage level, and converts it into a digital value by the A / D conversion circuit 100. Converted. The processing unit 130 performs integration using the digital value. In this way, the rotation angle is calculated. And the process part 130 performs the process corresponding to an angular velocity or the calculated rotation angle, produces | generates the display data corresponding to this process, and performs the process displayed on the display part 160. FIG.

  As described above, the fully-differential amplifier circuit, the comparator circuit, the A / D conversion circuit, the electronic device, and the like according to the present invention have been described based on the above-described embodiment or a modification thereof. It is not limited to the modification. The present invention can be implemented in various modes without departing from the gist thereof, and for example, the following modifications are possible.

  (1) In the above-described embodiment or its modification, the CMFB circuit is described as an example including a resistor divider circuit, but the present invention is not limited to this.

  (2) In the above-described embodiment or its modification, the differential operational amplifier circuit having the configuration shown in FIG. 2 or 6 has been described as an example, but the present invention is not limited to this. .

  (3) In the above-described embodiment or its modification, the comparator circuit having the configuration shown in FIG. 8 has been described as an example, but the present invention is not limited to this.

  (4) In the above embodiment or its modification, the example in which the fully differential amplifier circuit is applied to the comparator circuit has been described, but the present invention is not limited to this.

  (5) In the above embodiment or its modification, the example in which the comparator circuit is applied to the A / D conversion circuit has been described. However, the present invention is not limited to this.

  (6) In the above-described embodiment or its modification, the A / D conversion circuit having the configuration shown in FIG. 9 has been described as an example, but the present invention is not limited to this. For example, the fully differential amplifier circuit or the comparator circuit according to the present invention may be applied to a pipeline type A / D conversion circuit and other types of A / D conversion circuits.

10, 10a, 20, 30 ... fully differential amplifier circuit, 12 ... differential operational amplifier circuit,
14, 40 ... CMFB circuit, 15 ... resistance divider circuit,
16, 18a, 44 ... reset circuit, 42 ... amplifier circuit, 50 ... comparator circuit,
52 ... 1st fully differential amplifier circuit, 54 ... 2nd fully differential amplifier circuit,
60 ... Dynamic latch comparator circuit, 70 ... Sample hold circuit,
72: Comparison approximation register, 74: D / A conversion circuit, 100 ... A / D conversion circuit,
110 ... sensor circuit, 120 ... clock generation circuit, 130 ... processing section,
140 ... Memory, 150 ... Operation part, 160 ... Display part, 200 ... Electronic device,
BUS ... bus, C1, C2 ... offset cancellation capacity, LATCH ... latch signal,
Nc: Common mode feedback input node, Nd1, Nd2: Output node,
Ne ... input node, NIN, PIN ... differential input signal,
NOUT, POUT ... differential output signal,
QN1, QN2, QN10, QN11, QN12 ... MOS transistors (N type),
QP1, QP2, QP3, QP10, QP11 ... MOS transistors (P type),
R1, R2 ... resistance elements, RES ... switch control signals,
SW1, SW2, SW10, SW11, SWa ... switch element, VC ... voltage,
Vcm ... reference voltage

Claims (9)

A differential operational amplifier circuit that outputs a pair of differential output signals corresponding to the pair of differential input signals to a pair of output nodes;
A common mode feedback circuit for supplying a voltage generated based on the pair of differential output signals to a common mode feedback input node of the differential operational amplifier circuit;
A fully differential amplifier circuit comprising: a reset circuit that short-circuits the pair of output nodes and the common mode feedback input node. In claim 1,
The common mode feedback circuit is
A resistance dividing circuit for resistance-dividing the voltage between the pair of output nodes;
A fully-differential amplifier circuit, wherein a voltage obtained by resistance-dividing the voltage between the pair of output nodes by the resistor divider circuit is output to the common mode feedback input node. A differential operational amplifier circuit that outputs a pair of differential output signals corresponding to the pair of differential input signals to a pair of output nodes;
A common mode feedback circuit that supplies a voltage generated based on the pair of differential output signals to a common mode feedback input node of the differential operational amplifier circuit;
The common mode feedback circuit is
A resistance divider circuit for dividing resistance between the pair of output nodes;
An amplifying circuit for outputting a voltage obtained by amplifying a voltage corresponding to a difference between a voltage obtained by the resistance dividing circuit and a given reference voltage to the common mode feedback input node;
A fully differential amplifier circuit comprising: a reset circuit that short-circuits the pair of output nodes and an input node of the amplifier circuit. In any one of Claims 1 thru | or 3,
The reset circuit is
A fully differential amplifier circuit characterized in that the pair of output nodes and the common mode feedback input node or the input node of the amplifier circuit are short-circuited during a given reset period. A fully-differential amplifier circuit according to any one of claims 1 to 4,
And a dynamic latch comparator circuit to which the pair of differential output signals of the fully differential amplifier circuit are input. A first fully differential amplifier circuit;
A second fully differential amplifier circuit connected to the output of the first fully differential amplifier circuit;
A dynamic latch comparator circuit connected to the output of the second fully differential amplifier circuit;
5. The comparator circuit according to claim 1, wherein at least one of the first fully differential amplifier circuit and the second fully differential amplifier circuit is the fully differential amplifier circuit according to claim 1. The comparator circuit according to claim 5 or 6,
A comparison approximation register in which a register value is updated according to a comparison result of the comparator circuit;
A D / A conversion circuit for outputting an analog signal corresponding to the register value;
A sample hold circuit that samples and holds the input signal,
The comparator circuit is
An A / D conversion circuit that compares the analog signal with the signal held by the sample and hold circuit.   An electronic apparatus comprising the fully differential amplifier circuit according to claim 1.   An electronic apparatus comprising the A / D conversion circuit according to claim 7.

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