JPS592420A - Comparator - Google Patents

Abstract

PURPOSE:To attain the performance of high speed and high accuracy at the same time, by constituting a titled comparator with the 1st amplifier having two inputs, the 2nd amplifier to the input of which the output signal of the 1st amplifier is applied, an FF and plural analog switches. CONSTITUTION:An input 1 of a differential amplifier 7-1 is a terminal to which a comparison voltage is applied and connected to a capacitor train 12 having an S/H function. The other input 2 is a terminal to which a reference voltage is applied and grounded. Each input of an amplifier 7-2 is connected respectively to a corresponding output of the amplifier 7-1 via the analog switches 5-1, 5-2. The FF8 has a clear function releasing the hysteresis characteristic so as to make the complementary internal state and external output state to the same state, when a clear signal is given to a clear control terminal 11. Each input of the FF8 is connected respectively to an output corresponding to the amplifier 7-2 via offset error charging capacitors 6-1, 6-2. The high-speed and high-accuracy performance are attained at the same time through the constitution above.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog comparator, and more particularly to a comparator suitable for use in a successive approximation type A/I) converter in which a capacitor string is used as a local IJ/A converter. .

Conventionally, in such a successive approximation type Δ/1) converter, a comparator having a configuration as shown in FIG. 1 or 2 has been used.

First, to explain the converter shown in FIG. 1, reference numeral 104 is an operational amplifier. One of the input terminals 1 (]I is used as a terminal to which a comparison voltage is applied, and a capacitor string (not shown) having a sample-and-hold (S/I+) function is connected to it. In the figure, it is grounded and becomes 1. The comparison result is obtained at the output 108 of the operational amplifier 104. 106 is a capacitor for charging and holding the offset error of the operational amplifier 104.
() 5 is an analog switch.

In operation, first, the analog switch 05 is closed to apply negative feedback, and the offset error of the operational amplifier 104 is charged to the capacitor 10 (3). In other words, OFF compensation is performed. Then, the analog switch 105 is opened. 8 of the capacitor string connected to the input 101.
When the 711 function is activated, successive approximation A/D conversion is performed.

In order to improve the accuracy of the A/1 converter using this conventional comparator, the gain of the operational amplifier 104 must be increased to 1-min. However, since the operational amplifier 104 applies negative feedback for offset compensation, it is necessary to suppress the phase rotation to 1-min, which makes it difficult to increase the speed, so there is a limit to the speedup of the comparator with this configuration. In addition, there was a problem in that changes in the state of the operational amplifier U4 leaked through the human input to the conversion column, causing errors in the conversion column and reducing the conversion accuracy (Al1).

First, the comparator shown in FIG. 2 will be explained. In the same figure (
-1, 2(]7 is a differential output rectangular amplifier, one input is connected to the capacitor M° column (not shown), and the other input is applied with a reference voltage (grounded in the figure). ).2
08 is a frig-frot, each input of which is grounded to the corresponding output of the amplifier 207 through a capacitor 2 (16, 206') for charging the offset error.
5, 205', 209, and 210 are analog switches.

For high accuracy, this comparator has 2 flip-flops.
08 is used to increase the discrimination sensitivity, an amplifier 207 compensates for an offset error generated by a flip-flop, and further an offset error generated by the amplifier 207 is compensated for by a capacitor 206 and an analog switch 205. That is, before performing the comparison operation, the analog switch 209 is opened and the analog switches 205 and 205' are opened.
and 210 are closed to charge the capacitor 206 with the offset error of the amplifier 7.

During comparison operation, analog switches 209 and 2[0
is opened to perform offset compensation for the amplifier 7.

The analog switch 209 is essential in order to avoid the comparison voltage held in the array from disappearing due to the operation of closing the analog switch 210 during offset compensation. There is a problem in that noise is accumulated in the expression array every time a comparison operation is performed, resulting in a large Al1) conversion error.

SUMMARY OF THE INVENTION An object of the present invention is to provide a comparator that overcomes the drawbacks of the conventional comparators as described above.

Therefore, the comparator according to the present invention includes a first amplifier of the differential type having two inputs, a second amplifier to which the output signal of the first amplifier is applied to the input, and an output signal of the second amplifier. a flip-flop in which a signal is applied to the power source via a capacitive element; M number of analog switch elements are provided in the signal path leading to the human power of the switch.

The configuration is such that a comparison voltage is applied to one power source of the first amplifier, and a reference voltage is applied to the other power source of the first amplifier, and a comparison result signal is extracted from the output of the solve flop.

As will be described later, in order to further speed up the comparison operation, it is preferable to add a clearing function to the flip-flop and to configure the output of the second amplifier to be preset to an intermediate level.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to embodiments with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of a comparator according to the present invention.

Reference numeral 7-1 is a differential type amplifier, and one input terminal 1 is a terminal to which a comparison voltage is applied, and here it is connected to the input line 12 having an S/11 function. The other input 2 is a terminal to which a reference voltage is applied and is here grounded. 7-2
is an amplifier, each of which is connected to an analog switch 5-1.
．． 5-2 to the corresponding outputs of the amplifier 7-1, respectively.

Reference numeral 8 denotes a flip-flop, which has a function (clear function) of canceling the hysteresis characteristic and making the complementary internal state and external output state the same state when a clear signal is applied to the clear production terminal 11. The purpose of providing this clearing function is to shorten the comparison time, and it is not essential. Each input of the ℃1° flip-flop 8 is They are respectively connected to corresponding outputs of amplifier 7-2.

5-3 to 5-7 are also analog switches, and their connections are as shown in the figure.

The operation of this comparator is as follows: First, the capacity is A/f,
) Sample and hold the conversion input analog signal, simultaneously close the analog switches 5-1, 5-1.5-6.5-7, and open the remaining analog switches 5-3.5-4.5-5. As a result, the offset error of the amplifiers 7-1 and 7-2 is charged to the capacitors 6-1 and 6-2.

After that, it moves to the comparison operation, but before that, S
7: In this embodiment, the following preset operation is performed.

That is, analog switch 5-1.5-2.5-6.5-
7 is opened, analog switch 5-3.5-4.5-5 is closed, and clear control terminal 11 of flip-flop 8 is opened.
Input the clear signal to . As a result, the outputs of amplifier 7-2 and flip-flop 8 are preset to approximately an intermediate level. '/, C At this time, the analog switches 5-6, 5-7 are opened, so the offset error charged in the capacitor 6 is not lost and is held.

This preset operation is performed for the purpose of further speeding up the comparison operation. Therefore, if there is enough comparison time, the preset operation of the amplifier 7-2 can be omitted (analog switches 5-1 to 5-5 are no longer required).
. The same applies to the preset operation, that is, the clear operation, of the flip-flop 8.

After that, the preset is canceled and the comparison operation is started. That is, open the analog switch 5-3.5-4.5-5,
By closing analog switch 5-1.52, the amplifier 720 pre-sent is cleared and the clear control terminal 1
1- Cut off the supply of clear signal of \ and flip-flop 8
Cancel the preset (clear operation). This results in
The difference between the comparison voltage and the reference voltage (ground potential in this example) supplied from the capacitor string 12 to the input 1 is amplified by the amplifier 7-1, further amplified by the amplifier 7-2, and then the difference is applied to the capacitor 6-. 1.6-2 and is input to the solve flop 8 after offset compensation. At the output 3 of the flip-flop 8, a signal with a level corresponding to the comparison result is obtained.

With the above configuration, all the drawbacks of the prior art as described above can be eliminated.

As for isolation from the mass capacitor array 12, large isolation can be achieved by suppressing the gain of the amplifier 7-1 to reduce bias fluctuations associated with the comparison operation. In addition, since there is no need to provide a switch between the input 1 of the amplifier 7-1 and the capacitor array 12, there is no charge noise or fs for opening or closing the switch. Further, since the overall gain can be made sufficiently large due to the presence of the amplifier 7-2, the offset errors of the amplifiers 7-2, 7-2 and the solver flop 8 can be sufficiently compensated for. Thus, A is better than before.
, /1) The accuracy and sensitivity of the conversion can be significantly improved.

Also, since the high gain amplifier 7-2 does not apply negative feedback,
Compared to the conventional amplifier (207) explained in FIG. 2, the speed can be increased easily, and the speed of comparison operation can also be increased. In particular, when the amplifier 7-2 and the flip-flop 8 are preset as in this embodiment, the comparison time is, for example, 50
It can be shortened to about nanoseconds.

The comparator according to the present invention can of course be realized as a discrete circuit, but it can also be easily realized as an IC (integrated circuit) using a MOSIC process.

An example of a circuit configuration when realized by a CMOS-IC process is shown in FIG. 4 and will be described. Since the overall configuration is the same as that in FIG. 3, each part in FIG. 4 will be explained below in comparison with FIG. 3.

In FIG. 4, M1 to M13 are MOS transistors forming an amplifier 7-1. In this example, M.O.
The gain and dynamic range of the amplifier 7-1 are suppressed by connecting the drains and sources of the S transistors M8 to M I (+).Also, in order to increase the isolation from the capacitor column 12, , M.O.
A source follower consisting of S transistors M1 to M4 is provided at the input stage.

MOS) for transistors M35 to V38! These constitute analog switches 5-1 and 5-2, and are opened and closed by signals φ1 and T4 applied to their respective gates.

Analog switch 5-3.5-4 is made up of
The opening and closing of these are also controlled by the signal hole provided in the game 1.

MOS1. The registers MM to MI8 constitute an amplifier 7-22. In this example, a high gain is achieved by using the MOS l-transistor M14, [~41/I as an active load. The analog switch 5-5 connected to the pair of output terminals of this amplifier 7-2 is M O
8l-transistor M39, MzlO. The opening/closing of this analog switch 5-5 is performed using a MOS
) It is controlled by the signals φi, L applied to the run stars M39, +vl, io.

MOS) transistors M45 to M/18 constitute analog switches 5-6, and MOS transistors M45 to M/18 constitute analog switches 5-6, and MOS transistors M45 to M/18 constitute analog switches 5-6, and
19 to M52 constitute an analog switch 5-7. The opening and closing of these analog switches is controlled by the signal φ applied to the gate of the MOS transistor.

The MOS transistors MI9 to M34 connect the flip-flop 8 to +#"&. Among them, the MOS l-transistors M28 to M34 are only used to realize the clear function, and the clear operation is performed by the signals φ2 and φ3. In other words, these signals φ2 and φ3 correspond to the clear signal applied to the clear control terminal 11 in FIG.
．． 3 has been taken out.

13 is an IF power supply terminal, and 14 is a negative power supply terminal.

A typical timing diagram of the signals φ1, φ1 to φ1, φ4 is shown in FIG. Note that the signal φ: is not used in FIG.

As detailed above, according to the present invention, it is possible to realize a comparator that eliminates the drawbacks of the prior art. In particular, when the present invention is applied to a successive approximation type A/1) converter using a capacitive array as a local converter, the effect is remarkable, and high speed and high precision can be achieved at the same time. If the present invention is implemented using a CMOS-IC process that can easily realize a capacitor array and a high-precision analog switch, an extremely high-precision and high-speed A/D converter can be realized. Even with the currently popular CMOS-IC process, a comparison time of about 50 nanoseconds can be expected with an accuracy of 14 bits.

[Brief explanation of the drawing]

Fig. 1 and Fig. 2 are block diagrams showing different conventional examples of comparators, Fig. 3 is a block diagram showing an example of a comparator based on the invention, and Fig. 4 is realized by a CMOS-IC process. FIG. 5 is a circuit diagram showing an example of a comparator according to the present invention in the case of the present invention, and FIG. 5 is a timing diagram of the signals φ1 to φ4 in FIG. 1...Comparison voltage input, 2...Reference voltage input, 5-1~
5-7... Analog switch, 6], , 6-2...
Offset error charging capacitor,? -1゜7-2...
・Amplifier, 8...Flip-flop.

Claims (1)

[Claims] (1) A differential type first amplifier with two human power sources, a second amplifier to which the output signal of the first amplifier is applied to the human power, and an output signal of the second amplifier that is connected to an electrostatic waste. a flip-frog applied to the input via a capacitive element; and a flip-frog from the output of the first amplifier 11 to charge the capacitive element with the offset error of the first and second amplifiers. A reference voltage is applied to one input of the first amplifier, a comparison voltage is applied to the other input, and the output of the flip-flop is A comparator characterized in that it obtains a comparison result signal.