JP2007028090A - Automatic offset canceling circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an automatic offset canceling circuit of high precision which is capable of almost entirely erasing an inter-differential-output DC offset which is generated at a D/A convertor. <P>SOLUTION: The differential output voltage of an LPF14 is inputted in OOS, and a differential voltage is amplified by the amount of gain which the OOS has. The value is determined by a first comparator 18, and is sent to a digital control circuit 16. In the OOS, a series of switching processes for erasing a DC offset generated by a second comparator 19 using two capacitors C1 and C2 equipped to an output, is executed by the control signal generated by the digital control circuit 16. An amplifying stage by OOS which amplifies the inter-differential-output DC offset up to the value for ignoring DC offset of the comparator 18 is provided before the comparator 18, to prevent misjudgment due to DC offset of the comparator 18 itself. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an automatic offset cancellation circuit, and more particularly to an automatic offset cancellation circuit that automatically and accurately erases a DC offset between differential outputs generated in an analog baseband transmission unit in a W-CDMA communication system. .

  In an analog baseband transmission unit of a mobile communication system, a digitally modulated positive signal I signal and a quadrature signal Q signal thereof are D / A converted as differential outputs I and IB and Q and QB. It is output to the RF circuit. At this time, it is ideally desired that no DC offset is generated between the differential outputs I-IB and Q-QB, but in reality, the DC offset is generated due to various factors. As a result, in a mobile communication transmitter, a carrier leak occurs in the transmission spectrum, and eventually the EVM (Error Vector Magnitude) deteriorates.

  FIG. 1 is a block diagram showing a conventional offset cancel circuit that performs offset adjustment by manual operation. Conventionally, when this type of offset cancellation is performed, as shown in FIG. 1, a D / A converter 2 for offset adjustment is added to the main D / A converter 1 and a register (for offset adjustment) 5 is manually set. The correction value is written, and the correction value is added to the output of the main D / A converter 1 by the adder 3 to cancel the DC offset between the differential outputs. Reference numeral 4 denotes a low-pass filter (LPF).

  FIG. 2 is a block diagram showing a conventional automatic offset cancel circuit. In the case of automatically executing an operation for canceling the DC offset between the differential outputs, one having a comparator 8 as shown in FIG. 2 is known. When automatic offset cancellation is executed in the automatic offset cancel circuit shown in FIG. 2, the selector 7 switches the input to the offset adjustment D / A converter 2 from the output of the register 5 to the output of the digital control circuit 6. Then, the comparator 8 detects the DC offset between the differential outputs existing in the differential output of the transmission unit, and the digital control circuit 6 receives the comparison result. The digital control circuit 6 includes an up / down counter and the like, and generates a correction value for reducing the DC offset between the differential outputs according to the comparison result of the comparator 8. The correction value is sent to the offset adjustment D / A converter 2 and output as an analog signal, and then added to the output of the main D / A converter 1 by the adder 3. By repeating this operation several times, the DC offset between the differential outputs is gradually erased, the final correction value is written in the register 5, and the D / A converter for offset adjustment by the selector 7 2 is switched from the output of the digital control circuit 6 to the output of the register 5.

  In the automatic offset cancellation circuit shown in FIG. 2, when performing automatic offset cancellation of the transmission unit, it is necessary to pay attention to the DC offset existing in the comparator 8 itself. When the DC offset between the differential outputs is sufficiently larger than the DC offset of the comparator 8, the determination by the comparator 8 is performed normally, but the DC offset between the differential outputs is a value that cannot be ignored with respect to the DC offset of the comparator 8. In this case, an erroneous determination occurs in the comparator 8, and the DC offset cannot be removed accurately.

  For example, it is assumed that the DC offset V1 between differential outputs is +20 mV and the offset V2 present in the comparator 8 is +5 mV. The comparator 8 ideally outputs H when the input is positive with 0 mV as a boundary, and outputs L when the input is negative, and the resolution of the offset adjustment D / A converter 2 is ± 1 mV / LSB. At this time, the comparator 8 detects the input of V1 + V2 = + 25 mV and outputs H. From this result, a correction value is created so that V1 becomes +20 mV or less, and V1 corrected to 19 mV is input to the comparator 8 again. Even if this is repeated several times and V1 becomes 0 mV, the comparator 8 outputs H to detect V1 + V2 = + 5 mV, and V1 becomes −1 mV. In the next comparison, V1 + V2 = + 4 mV is detected and H is output. That is, the comparator 8 outputs H until V1 + V2 <0, and L is output when V1 <−5 mV.

  In order to cancel the offset accurately, the determination of the comparator 8 must be switched with the DC offset between the differential outputs as a boundary at 0 mV. In this case, the input is switched with -5 mV as the boundary because of the DC offset of the comparator 8 itself. Any determination from 0 mV to -5 mV is erroneous. This is shown in FIGS. 3 (a) and 3 (b). FIGS. 3A and 3B are diagrams showing a comparison operation model of an ideal comparator and a comparator having a DC offset.

  For this reason, the DC offset between the differential outputs is not completely erased but has an error of about −5 mV. If this value is an acceptable circuit specification for the DC offset between the differential outputs, in other words, for the circuit specification where the allowable value for the DC offset between the differential outputs is sufficiently larger than the DC offset of the comparator. Although there is no problem with this configuration, for example, in an analog baseband transmitter in a W-CDMA communication system, the DC offset between differential outputs greatly affects the deterioration of transmission characteristics, so the allowable value is very small and almost It is desirable that it be completely erased.

  Conventionally, as a method of executing this type of offset cancellation with high accuracy without depending on the influence of the DC offset generated in the comparator itself, after the offset cancellation is executed as usual in the first mode and the correction value 1 is obtained. In the second mode, the differential signal input to the comparator is exchanged to execute offset cancellation to obtain the correction value 2 and the average of the correction value 1 and the correction value 2 is calculated as the correction value 3, There is a technique for performing offset cancellation using a result as a final value (see, for example, Patent Document 1).

JP 2005-5873 A

  However, as described above, in a circuit that corrects a DC offset generated by a D / A converter using a comparator, the DC offset generated by the comparator itself can be ignored as the allowable value of the DC offset decreases. The DC offset cannot be canceled accurately. In addition, when a strict speed is required for the time required for offset cancellation, the offset cancellation is executed twice, and the average value is taken to cancel the DC offset of the comparator itself. I need it.

  The present invention has been made in view of such a problem, and an object of the present invention is to provide a high accuracy capable of almost completely erasing a DC offset between differential outputs even when a DC offset exists in the comparator. An automatic offset cancel circuit is provided.

  The present invention has been made to achieve such an object, and the invention according to claim 1 is directed to an automatic offset cancel circuit for canceling a DC offset generated by a D / A converter. A comparator for detecting a DC offset generated in the converter and a DC offset generated in the D / A converter are amplified until the influence of the DC offset can be ignored in order to prevent erroneous determination due to the DC offset generated in the comparator. An amplification stage having a single-stage connection or a multi-stage connection of the circuits, and the amplification stage is connected to the offset comparison circuit provided in the preceding stage of the comparator and the D / A converter, and the D / A converter The offset adjustment D / A converter for adjusting the generated DC offset and the off-state according to the comparison result in the offset comparison circuit Characterized in that a digital control circuit for generating an offset correction value of Tsu preparative adjustment D / A converter.

  According to a second aspect of the present invention, in the first aspect of the present invention, the amplification stage includes a low gain comparator and a means for eliminating a DC offset generated by the comparator. A switch for switching the reference voltage and the output signal of the D / A converter on the input side of the comparator, and a switch for disconnecting from the reference voltage on the output side of the capacitor, Has a differential output configuration or a single output configuration, and is connected in a single stage or in multiple stages.

  According to a third aspect of the present invention, in the first aspect of the present invention, the amplification stage includes a high gain comparator and a means for eliminating a DC offset generated by the comparator. A switch for operating the comparator with negative feedback, and a switch for switching the input of the comparator between a reference voltage and the output of the D / A converter, and the circuit has a differential output. It is a structure and is characterized by being connected in one stage or in multiple stages.

  According to a fourth aspect of the present invention, there is provided the invention according to the second or third aspect, wherein a plurality of stages are connected by combining any of the amplification stages.

  According to a fifth aspect of the present invention, in the first aspect of the present invention, the increase / decrease amount of the offset correction value generated by the digital control circuit is reduced for each comparison, and the accuracy is gradually increased. The offset cancellation time is shortened by reducing the number of comparisons.

  According to a sixth aspect of the present invention, in the first aspect of the present invention, the circuit connected to the output of the amplification stage is not a comparator but a latch circuit.

  A seventh aspect of the present invention is a D / A converter using the automatic offset cancel circuit according to any one of the first to sixth aspects.

  That is, the automatic offset cancel circuit according to the present invention detects a DC offset between differential outputs using a comparator, and an amplification stage for reducing the DC offset of the comparator itself relative to the input voltage is provided at the front stage of the comparator. It is prepared for.

  Further, the amplification stage is provided with an offset auto-zero comparator.

  In addition, by connecting multiple stages of offset auto-zero comparators, it is possible to realize an automatic offset cancellation circuit with higher accuracy and higher speed, and can be realized regardless of differential output configuration or single output configuration. And

  According to the present invention, in addition to a general comparator, an offset autozero comparator is used to amplify the DC offset between differential outputs until the DC offset generated in the comparator itself becomes relatively small. There is an effect that the DC offset can be canceled automatically and with high accuracy. Further, in order to execute high-precision and high-speed offset cancellation using a comparator having a larger DC offset, it can be easily achieved by simply connecting offset / auto-zero comparators in multiple stages.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 4 is a circuit diagram showing a configuration example of the analog baseband transmission unit in the differential output to which the automatic offset cancellation circuit of the present invention is applied. This automatic offset cancel circuit shows an output offset auto-zero comparator (hereinafter referred to as OOS) having a single-stage (one-stage connection) differential output configuration. The automatic offset cancel circuit shown in FIG. 4 is a circuit diagram in which the OOS shown in FIG. 7 is added to the preceding stage of the comparator shown in FIG.

  This automatic offset cancel circuit is for erasing the DC offset generated in the D / A converter 11. The offset comparison circuit 10 includes a first comparator 18 and an amplification stage 10 a provided in the previous stage of the first comparator 18. The first comparator 18 detects a DC offset generated by the D / A converter 11, and the amplification stage 10a is affected by the DC offset in order to prevent erroneous determination due to the DC offset generated by the comparator 18. A circuit for amplifying a DC offset generated in the D / A converter 11 is connected in one stage until it can be ignored. The amplification stage 10a includes a second comparator 19, capacitors C1 and C2, and switches S1 to S6.

  The D / A converter 12 for offset adjustment is connected to the main D / A converter 11 and adjusts an offset generated by the main D / A converter 11. The digital control circuit 16 is used for offset comparison. The offset correction value of the offset adjustment D / A converter 12 is generated according to the comparison result in the circuit 10.

  With such a configuration, an offset autozero comparator is used in addition to a general comparator, and the DC offset between the differential outputs is amplified until the DC offset generated in the comparator itself becomes relatively small. The DC offset can be canceled automatically and with high accuracy.

  More specifically, when automatic offset cancellation is executed, the differential output voltage of the LPF 14 is input to the OOS, and the differential voltage is amplified by the gain of the OOS. The first comparator 18 determines the value and sends it to the digital control circuit 16. In the OOS, a series of switching processes for erasing the DC offset generated by the second comparator 19 by the two capacitors C1 and C2 provided at the output are executed by the control signal generated by the digital control circuit 16.

Next, the switching control method of the OOS will be described. In the initial state, the switches S1 and S2 are turned off to disconnect the input, and the switches S3, S4, S5, and S6 are turned on to connect to the reference voltage. In this state, the reset of the second comparator 19 is released, and charges corresponding to the DC offset of the second comparator 19 are accumulated in the capacitors C1 and C2. Thereafter, the switches S3, S4, S5, and S6 are turned off to disconnect from the reference voltage, and the switches S1 and S2 are turned on to amplify the DC offset between the differential outputs from the LPF. At this time, since the electric charges accumulated in the capacitors C1 and C2 are stored, the DC offset of the second comparator 19 is cancelled. Assuming that the voltage detected by the first comparator 18 is V1, the value can be expressed by the following equation.
V1 = A × Vdif + ΔQ / C + Vosc

Here, Vdif is a DC offset between the differential outputs, ΔQ is an error due to charge injection of the switches S5 and S6, C is a capacitance due to the capacitors C1 and C2, and Vosc is a DC offset of the first comparator 18. The influence of the charge injection ΔQ can be considerably reduced by using a switch having a combination of a PMOS transistor and an NMOS transistor for each switch and reducing the size of each MOS transistor. In other words, in the present invention, the first comparator 18 is amplified by amplifying the DC offset between the differential outputs input to the first comparator 18 to a value sufficiently larger than the DC offset generated by the first comparator 18 itself. The comparison processing is performed in an area where the determination by 18 is normally performed. At this time, the residual offset of the first comparator 18 viewed from the input of the OOS is expressed as Vos as follows.
Vos = ΔQ / (A × C) + Vosc / A

  Here, ΔQ is an error due to charge injection of the switches S 5 and S 6, A is the gain of OOS, C is the capacitance due to the capacitors C 1 and C 2, and Vosc is the DC offset of the first comparator 18. If the error due to the charge injection of the switches S5 and S6 is ignored, it can be seen that the DC offset Vosc of the first comparator 18 is multiplied by 1 / A. That is, by amplifying the DC offset between the differential outputs, the influence of the DC offset of the first comparator 18 can be reduced to 1 / A times, and as a result, automatic offset cancellation accuracy up to about Vosc / A is possible. Become. This is shown in FIGS. 8 (a) and 8 (b). FIGS. 8A and 8B are diagrams showing a comparison operation model to which the present invention is applied and a comparison operation model of a comparator having a DC offset.

  The digital control circuit 16 generates a correction value by an up / down counter in addition to the switching control necessary for the offset / auto-zero operation of the OOS. The up / down counter increases or decreases the counter value from the comparison result of the first comparator 18. The automatic offset cancellation often ends when the comparison result of the first comparator 18 is inverted. However, when it is desired to specify the offset cancellation time strictly so as not to depend on the sample, it is necessary to determine the number of comparisons. The number of comparisons necessary for offset cancellation when the increase / decrease value of the up / down counter is ± 1 can be determined by dividing the DC offset voltage to be erased by the resolution of the D / A converter 2. In order to shorten the execution time of the automatic offset cancellation, it is possible to reduce the number of comparisons by switching the increase / decrease value of the up / down counter. For example, when the DC offset voltage is 20 mV and the resolution of the D / A converter 2 is ± 1 mV / LSB, if the counter is increased or decreased by ± 1, a comparison of at least 20 times is required, but the first five times By increasing / decreasing the comparison by ± 2 and increasing / decreasing the remaining 10 times by ± 1, automatic offset cancellation with a DC offset of 20 mV is compensated by a total of 15 comparisons. In addition to the control method using the up-down method, the successive approximation method can also be used. In this case, the number of bits of the offset adjustment D / A converter 12 is the number of processing times, and the number of comparisons required for automatic offset cancellation in the case of an N-bit D / A converter is N times, which is higher than that of the up-down method. Quite efficient operation is possible. Furthermore, when higher speed processing is desired, the flash method in which the above-described comparator configurations are arranged in parallel can be used. In this case, the processing can be completed by one comparison.

  FIG. 5 is a circuit diagram showing a configuration example of an analog baseband transmission unit in a single output to which the automatic offset cancel circuit (single stage single output OOS type) of the present invention is applied, and is replaced with the differential output configuration in FIG. FIG. Therefore, the amplification stage 10a of the offset comparison circuit 10 includes the second comparator 19, the capacitor C1, and the switches S1 to S3. The relationship between the main D / A converter 11, the offset adjustment D / A converter 12, and the LPF 14 is also a single output configuration.

  6 and 7 are circuit diagrams of an offset auto-zero comparator having a single-stage (one-stage connection) differential output configuration, and FIG. 6 is an input offset auto-zero comparator (hereinafter referred to as IOS) having a differential output configuration. FIG. 7 shows an output offset autozero comparator (OOS) having a differential output configuration.

  In FIG. 6, the amplification stage 10a includes a high-gain comparator 19a and capacitors C1 and C2 on the input side of the comparator 19a as means for erasing the DC offset generated by the comparator 19a. And switches S1, S2, S3, and S4 for switching the input of the comparator 19a between the reference voltage and the output of the main D / A converter 11.

  In FIG. 7, similarly to FIG. 6, the amplification stage 10a includes a low gain comparator 19b and capacitors C1 and C2 as outputs for eliminating the DC offset generated in the comparator 19b. The switches S1, S2, S3, S4 for switching the reference voltage and the output signal of the main D / A converter 11 to the input side of the comparator 19b, and the reference voltage to the output side of the capacitors C1, C2 It has switches S5 and S6 for disconnecting.

[Second Embodiment]
FIG. 9 is a circuit diagram showing a configuration example of the analog baseband transmission unit in the differential output to which the automatic offset cancel circuit (multi-stage differential output OOS type) of the present invention is applied. The OOS in FIG. It is the figure changed into the multistage of 2 steps | paragraphs from the stage. The third comparator 20 is provided after the comparator 19b shown in FIG. Therefore, the amplification stage 21a of the offset comparison circuit 21 in this case includes the second comparator 19b, the third comparator 20, capacitors C1 to C4, and switches S1 to S8.

In OOS, the comparator is used in an open loop, so that it cannot have a very high gain. Therefore, the residual offset Vosc / A can be reduced to a certain extent, but it may be insufficient depending on the circuit specifications. Even in such a case, in the present invention, offset cancellation with higher accuracy and higher speed can be easily realized by using a multi-stage in which offset auto-zero comparators are connected in multiple stages. The switching control method in the two-stage configuration shown in FIGS. 8A and 8B is almost the same as that of the OOS, and the added third comparator 20 has an offset holding operation and the holding of the second comparator 19b. Can be executed at the same time. At this time, the residual offset Vos viewed from the input of the OOS is expressed by the following equation.
Vos = ΔQ1 / (Ca × A1) + ΔQ2 / (Cb × A1 × A2) + Vosc / (A1 × A2)

  Here, ΔQ1 is an error due to charge injection of the switches S5 and S6, ΔQ2 is an error due to charge injection of the switches S7 and S8, A1 is a gain due to the first stage OOS, Ca is a capacitance due to the capacitors C1 and C2, and Cb is a capacitor C3. And C4, A2 is the gain due to the second stage OOS, and Vosc is the DC offset of the first comparator 18. The DC offset Vosc of the first comparator 18 becomes a value Vosc / (A1 × A2) divided by the gain product A1 × A2 of the second comparator 19b and the third comparator 20, and the residual offset corresponding to this is considerably large. Can be reduced. However, the effects of charge injection by the switches S5 and S6 provided after the capacitors C1 and C2 and the switches S7 and S8 provided after the capacitors C3 and C4 still exist, and the residual offset corresponding to ΔQ1 / ( Ca × A1) + ΔQ2 / (Cb × A1 × A2). As a countermeasure, by performing the offset holding operation of the second comparator 19b before the third comparator 20, only the influence of charge injection by the switches S7 and S8 in the previous stage of the first comparator 18 remains, and the switch S5 , S6 can eliminate the residual offset due to the charge injection. This is because the residual offset due to the charge injection by the switches S5 and S6 is regarded as the DC offset of the third comparator 20 and is held in the output capacitor.

Next, the switching control method will be described. In the initial state, the switches S1 and S2 are turned off to disconnect the input, and the switches S3, S4, S5, S6, S7, and S8 are turned on to connect to the reference voltage. In this state, the reset of the second comparator 19b is released, and charges corresponding to the DC offset of the second comparator 19b are accumulated in the capacitors C1 and C2. Thereafter, the switches S5 and S6 are turned off to disconnect from the reference voltage, and the reset of the third comparator 20 is released, and the charge due to the error of charge injection by the switches S5 and S6 to the capacitors C1 and C2 and the second comparator 19b. The charge corresponding to the DC offset is accumulated. Thereafter, the switches S3, S4, S7, and S8 are turned off to disconnect from the reference voltage, and the switches S1 and S2 are turned on to amplify the DC offset between the differential outputs from the LPF. At this time, since the charges accumulated in the capacitors C1, C2, C3, and C4 are stored, the DC offsets of the second comparator 19b and the third comparator 20 are cancelled. As a result, the residual offset is expressed as follows, which is useful when more accuracy is required.
Vos = ΔQ2 / (Cb × A1 × A2) + Vosc / (A1 × A2)

  The digital control circuit 16 is the same as that in the first embodiment.

  10 is a circuit diagram of a multi-stage offset auto-zero comparator. The input offset auto-zero comparator (IOS) having the differential output configuration shown in FIG. 6 and the output having the differential output configuration shown in FIG. An offset auto-zero comparator (OOS) is connected in multiple stages. In this case, since the DC offset of the two comparators 19a and 19b is stored in the capacitors C1 and C2, there is an advantage that the number of capacitors can be reduced and the area can be reduced compared to the above-described configuration.

  FIG. 11 is a circuit diagram when the output section of the offset comparison circuit in the automatic offset cancellation circuit (multi-stage differential output OOS type) of the present invention is changed from a comparator to a latch circuit. The latch circuit 22 determines and holds the output signal of the offset auto-zero comparator at the timing of the enable signal. For example, after the switches S1 and S2 are closed and the comparison determination is started, an enable signal is generated at a certain interval. When this enable is H, when the enable rises, if the differential input> 0, H is set. If differential input <0, hold as L. When the enable is L, it is cleared. By doing in this way, there exists an effect that the output response at the time of a comparatively small input voltage becomes quick compared with a comparator.

  The present invention can be applied as an automatic offset cancel circuit that automatically and accurately erases a DC offset between differential outputs generated in an analog baseband transmitter in a W-CDMA communication system. In addition to a general comparator, an offset auto-zero comparator is used to amplify the DC offset between differential outputs until the DC offset generated by the comparator itself becomes relatively small. And it becomes possible to cancel with high precision.

It is a block diagram which shows the conventional offset cancellation circuit which performs offset adjustment by manual operation. It is a block diagram which shows the conventional automatic offset cancellation circuit. It is a figure which shows the comparison operation model of the comparator with an ideal comparator and DC offset. It is a circuit diagram which shows the structural example of the analog baseband transmission part in the differential output to which the automatic offset cancellation circuit (single stage differential output OOS type) of this invention is applied. It is a circuit diagram which shows the structural example of the analog baseband transmission part in the single output to which the automatic offset cancellation circuit (single stage single output OOS type) of this invention is applied. It is a circuit diagram of a single stage differential output IOS type offset autozero comparator. It is a circuit diagram of a single stage differential output OOS type offset autozero comparator. It is a figure which shows the comparative operation | movement model to which this invention is applied, and the comparison operation | movement model of the comparator with DC offset. It is a circuit diagram which shows the structural example of the analog baseband transmission part in the differential output to which the automatic offset cancellation circuit (multi stage differential output OOS type) of this invention is applied. It is a circuit diagram of a multi-stage offset auto-zero comparator. FIG. 6 is a circuit diagram when the output section of the offset comparison circuit in the automatic offset cancellation circuit (multi-stage differential output OOS type) of the present invention is changed from a comparator to a latch circuit.

Explanation of symbols

1 Main D / A Converter 2 D / A Converter for Offset Adjustment 3 Adder 4 Low Pass Filter (LPF)
5 registers (for offset adjustment)
6 Digital Control Circuit 7 Selector 8 Comparator 10 Offset Comparison Circuit 10a Amplification Stage 11 Main D / A Converter 12 Offset Adjustment D / A Converter 13 Adder 14 Low Pass Filter (LPF)
15 registers (for offset adjustment)
16 Digital Control Circuit 17 Selector 18 First Comparator 19 Second Comparator 19a High Gain Comparator 19b Low Gain Comparator 20 Third Comparator 21 Offset Comparison Circuit 21a Amplification Stage 22 Latch Circuit

Claims (7)

In an automatic offset cancel circuit for erasing the DC offset generated in the D / A converter,
A comparator for detecting a DC offset generated in the D / A converter, and a DC generated in the D / A converter until the influence of the DC offset can be ignored in order to prevent erroneous determination due to the DC offset generated in the comparator. An offset comparison circuit comprising an amplification stage in which a circuit for amplifying an offset is connected in one stage or connected in multiple stages, and the amplification stage is provided in a stage preceding the comparator;
An offset adjusting D / A converter connected to the D / A converter for adjusting a DC offset generated by the D / A converter;
An automatic offset cancel circuit comprising: a digital control circuit that generates an offset correction value of the offset adjustment D / A converter according to a comparison result in the offset comparison circuit.   The amplifying stage is provided with a low gain comparator and a capacitor for eliminating a DC offset generated by the comparator on the output side of the comparator, and a reference voltage and D / A conversion are provided on the input side of the comparator. A switch for switching the output signal of the capacitor and a switch for disconnecting from the reference voltage on the output side of the capacitor, the circuit of which is a differential output configuration or a single output configuration, and is connected in a single stage or in multiple stages The automatic offset cancel circuit according to claim 1, wherein:   The amplification stage includes a high-gain comparator, and a switch for operating the comparator with negative feedback, with a capacitor provided on the input side of the comparator as means for erasing the DC offset generated by the comparator; A switch for switching the input of the comparator between a reference voltage and an output of the D / A converter, and the circuit has a differential output configuration and is connected in one stage or in multiple stages. The automatic offset cancel circuit according to 1.   4. The automatic offset cancel circuit according to claim 2, wherein a multistage connection is made by combining any of the amplification stages.   The amount of increase / decrease in the offset correction value generated by the digital control circuit is reduced for each comparison, and the accuracy is gradually increased to reduce the overall number of comparisons, thereby reducing the offset cancellation time. The automatic offset cancel circuit according to 1.   2. The automatic offset cancel circuit according to claim 1, wherein the circuit connected to the output of the amplification stage is constituted by a latch circuit instead of a comparator. A D / A converter using the automatic offset cancel circuit according to any one of claims 1 to 6.

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