JPH01258188A - Adder - Google Patents

Abstract

PURPOSE:To reduce the area occupied by an operational amplifier on a chip and the power consumption by using switched capacitor circuits. CONSTITUTION:An adder is constituted to include first and second input terminals IN1 and IN2 to which signals to be added are applied, an operational amplifier A1, switched capacitor circuits C2, S1, S2, and C4, S3, S4 which are connected between the input part of the operational amplifier A1 and input terminals IN1 and IN2, and switches capacitor circuits C6, S5, S6 which are connected between the output part and the input part of the operational amplifier A1 to form a feedback circuit. Since no resistance elements are used at all and switched capacitor circuits are used in this manner, the adder is realized with a small chip area and a low power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an adder, and particularly to an adder that can be implemented with a smaller hardware configuration so as to be mounted on an LSI.

[Conventional technology]

Conventionally, the configuration of an adder as shown in FIG. 3 is well known. Resistor R1 from each input terminal INI, IN2
, R2 to the inverting input terminal (-) of the operational amplifier A, while feedback is provided between the output terminal OUT of the operational amplifier A and the inverting input terminal (-) through a resistor R5.

When signal voltages V r and V 2 are input to both input terminals INI and IN2 of this adder, respectively, an output voltage v0 expressed by the following equation is obtained.

As is clear from equation (1), for example, R1=Rs, R
2=R3, the input voltages V and v2 are simply added to obtain the output voltage v0.

[Problem to be solved by the invention]

The conventional adder described above includes resistors R1 and R8 and resistor R2.
Since the weighting of the two-input terminal addition changes depending on the ratio of R8 and R8, the accuracy of the ratio of each resistance value affects the characteristics. However, the relative accuracy of resistance values is generally poor in LSIs, for example 1
% variation occurs. Furthermore, if the resistance value is made smaller, the operational amplifier's resistance drive ability and sink characteristics will become stricter, and therefore the area occupied by the operational amplifier on the chip will increase, and power consumption will also increase, which is economically disadvantageous. be. Conversely, if the resistance value is increased, the area occupied by the resistance element on the chip increases, which is also economically disadvantageous.

[Means to solve the problem]

The adder of the present invention includes first and second input terminals for adding signals to be added, an operational amplifier, a first switch connected between the input of the operational amplifier and the first input terminal, a feedback circuit is formed between the switching capacitor circuit, a second switched capacitor circuit connected between the input section of the operational amplifier and the second input terminal, and the output section and the input section of the operational amplifier. and a third switched capacitor circuit connected to each other.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

AI is an operational amplifier, 01 to C6 are capacitive elements, 81 to S,
indicates a switch, and the switches S, ~S, are all simultaneously switched to ground potential at a constant sampling period.

Here, the capacitance ratios of the capacitive elements C1 and C2a, the capacitive elements C3 and 041, and the capacitive elements C2 and 06 are all designed to be equal. At this time, signal voltages V, , V! are applied to both input terminals INI and IN2, respectively. When is input, an output voltage v0 expressed by the following formula is obtained.

As is clear from equation (2), for example, Cs = Cs,
When Cs = C8, the input voltages v1 and v2 are simply added to obtain the output voltage v0.

Furthermore, a low-pass filter is generally required before the switched capacitor circuit in order to avoid aliasing (aliasing of signals in the high frequency range), but in the case of the circuit of the present invention, since aliasing does not occur, a low-pass filter is required. is not necessary. However, capacitive elements C1 and C2p capacitive elements C1 and C
4. If there is a variation in the capacitance ratio between the capacitive elements Cs and 06, aliasing will occur, but it is easy to suppress the variation to 1% or less, and the aliasing noise at this time will be at least 40%.
Can be suppressed by more than dB.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

A2 is an operational amplifier, 01 to Cs are capacitive elements, 81 to S8
indicates a switch, and all switches 81 to S8 are simultaneously switched to the ground potential at a constant sampling period.

Here, capacitive element C1 and Ctr capacitive element C1 and 041
The capacitance ratios to capacitive elements C5 and C6 are all designed to be equal. At this time, the rain input terminals INI, IN2. lN5):
When each of the signal voltages V r , V 2 , and V 3 is input, an output voltage v0 expressed by the following formula is obtained.

As is clear from equation (3), for example, Or = Ct,
Cs = Ct.

Cs ” When Ct, the input voltage V 1. V and V,
is simply added to the output voltage ■. obtained as.

Similarly, in the case of other embodiments, a low-pass filter is not necessary for pruning.

〔Effect of the invention〕

As explained above, the present invention does not use any resistive elements at all and is configured with switched capacitor circuits, thereby achieving the effect of realizing an adder with a small mop area and low power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the adder of the present invention, and FIG.
This figure is a circuit diagram showing another embodiment of the adder of the present invention, and FIG. 3 is a circuit diagram showing a conventional adder. INI, IN2. IN3...Input terminal, OUT
...Output terminal, C1-C1...Capacitive element, S1-8...Switch, A, AI, A2.
...Operation amplifier, R1゜R2, R3...
Resistance element. Agent Patent Attorney Susumu Uchihara 2: ≧ 1+Il+I Mi Mi

Claims (1)

[Claims] 1. An operational amplifier having a first input terminal, a second input terminal, an output terminal, a reference voltage terminal, and at least an inverting input section, and the inverting input terminal of the operational amplifier. and a first capacitor, both terminals of which are connected to the output terminal, a first switch, a second capacitor, and a second capacitor, which are connected in series between the inverting input terminal and the output terminal of the operational amplifier. a second switch; a third capacitor having both terminals connected to the inverting input terminal and the first input terminal of the operational amplifier; and a third capacitor having both terminals connected to the inverting input terminal and the first input terminal of the operational amplifier; a third switch, a fourth capacitor, and a fourth switch connected in series in order between them; and a fourth switch, both terminals of which are connected to the inverting input terminal and the second input terminal of the operational amplifier. 5 and the inverting input terminal of the operational amplifier and the second
a fifth switch, a sixth capacitor, and a sixth switch connected in series in order between the input terminal of the first
- An adder characterized in that all of the sixth switches are connected to the reference voltage terminal at the same time, being connected when on and open when off. 2. A patent characterized in that the capacitance ratio of the first and second capacitors, the capacitance ratio of the third and fourth capacitors, and the fifth and sixth capacitance ratios are set equal to each other. An adder according to claim 1.