JP2011061319A - Comparator circuit and motor drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce capacitors requiring high breakdown voltage characteristics from a comparator circuit. <P>SOLUTION: The comparator circuit has: capacitors C1-C3 of which the one end is connected in common; a first switch circuit for impressing either an voltage Vref or Vin onto C1 one by one; and an inverter the input edge of which is connected to a connection point of C1-C3. The comparator circuit also has: a second switch circuit; a first latch circuit; and a control circuit. The second switch circuit connects the input end and the output end of the inverter during a first period when Vref is impressed onto C1. The first latch circuit outputs the output level of the inverter during a second period when Vin is impressed onto C1 after the first period, and holds and outputs the output level of the inverter at the end of the second period during the first period. The control circuit impresses a voltage of L level onto C3 and impresses a voltage of H level onto C2 during the first period, while it impresses a voltage of a H level onto C3 and impresses a voltage of a L or H level onto C2 during the second period. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a comparator circuit and a motor drive circuit.

  A sensorless system that does not require a position detection element such as a Hall element is known as a driving system for a motor including a plurality of phase driving coils such as a three-phase motor. The sensorless method uses a counter electromotive voltage generated in the drive coil, and can detect the position of the rotor (rotor) by comparing the voltage of the drive coil of each phase with the voltage of the neutral point. it can. For example, Patent Document 1 discloses a comparator circuit that has a hysteresis characteristic corresponding to the output of a filter that removes noise from an output signal and is suitable for use in a sensorless motor drive circuit.

  A chopper type comparator can also be used for the sensorless motor drive circuit. Since the chopper type comparator can be composed of a logic circuit and a capacitor, a small area and highly accurate comparator circuit can be realized. For example, in Patent Document 2, in addition to a capacitor C1 to which an input voltage or a reference voltage (reference voltage) is applied in accordance with a control signal, a hysteresis characteristic is added using a capacitor C2 to which only an input voltage is applied. A semiconductor integrated circuit having a built-in type comparator is disclosed.

  In this manner, a chopper type comparator circuit having hysteresis characteristics can be used for a sensorless motor driving circuit.

JP 2003-111437 A JP 2004-336504 A

  However, in the chopper comparator of Patent Document 2, the input voltage is applied not only to the conventional capacitor C1 but also to the additional capacitor C2. Accordingly, it is necessary to use a capacitor having a withstand voltage characteristic corresponding to the input voltage. Therefore, when an input voltage higher than a logic level voltage used in the logic circuit is applied, such as a comparator circuit used in a motor drive circuit, the circuit area is increased by the capacitors C1 and C2 having high withstand voltage characteristics corresponding thereto. growing.

  In the chopper comparator of Patent Document 2, the hysteresis width (difference between two threshold voltages) is proportional to C2 / (C1 + C2). However, in order to make the hysteresis width variable, when the capacitor C1 or C2 is connected in parallel and switched, the denominator (C1 + C2) changes. For this reason, it is difficult to change the hysteresis width in a constant step.

  The main present invention that solves the above-described problems includes a first capacitor having one end connected in common, a second capacitor, and one or more third capacitors, and a first capacitor at the other end of the first capacitor. Alternatively, a first switch circuit that sequentially applies one of the second voltages, an inverter having an input terminal connected to a connection point of the first to third capacitors, and the other end of the first capacitor A second switch circuit connecting an input terminal and an output terminal of the inverter in a first period in which the first voltage is applied; and, in addition to the first capacitor, in addition to the first capacitor. The output level of the inverter is output during a second period in which the second voltage is applied to the end, and the output level of the inverter at the end of the second period is maintained during the first period. Output the first latch In the first period, a first logic level voltage is applied to the other end of the third capacitor, and a second logic level voltage is applied to the other end of the second capacitor. In the second period, a voltage of the second logic level is applied to at least one other end of the third capacitor, and the first or second voltage is applied to the other end of the second capacitor. And a control circuit for applying a logic level voltage.

  Other features of the present invention will become apparent from the accompanying drawings and the description of this specification.

  According to the present invention, capacitors that require high withstand voltage characteristics can be reduced from a chopper type comparator circuit having hysteresis characteristics. Further, the hysteresis width can be made variable in a certain step.

1 is a circuit block diagram showing a configuration of a comparator circuit in a first embodiment of the present invention. It is a circuit block diagram which shows the outline of a structure of the whole motor drive circuit provided with the comparator circuit. In 1st Embodiment of this invention, it is a schematic diagram which shows an example of the relationship between the input voltage Vin and the change of a threshold voltage. It is a circuit block diagram which shows the structure of the comparator circuit in 2nd Embodiment of this invention. It is a circuit block diagram which shows the structure of the comparator circuit in 3rd Embodiment of this invention. It is a figure which shows the example of a setting of the hysteresis control signal Vc2 thru | or Vc5 in the 1st and 2nd comparison period of the control circuit 11c.

  At least the following matters will become apparent from the description of this specification and the accompanying drawings.

=== Overall Configuration of Motor Drive Circuit ===
Hereinafter, with reference to FIG. 2, an outline of the configuration of the entire motor drive circuit including the comparator circuit in the first to third embodiments of the present invention to be described later will be described. In FIG. 3, for convenience of explanation, only components related mainly to the operation of the comparator circuit are shown.

  The motor drive circuit 1 shown in FIG. 2 is a circuit for driving the motor 9 including three-phase drive coils 91 to 93, and is configured as an integrated circuit including terminals 61 to 68. The motor drive circuit 1 includes a comparator circuit 10, a switching control circuit 31, a selection circuit 32, and output transistors 41 to 43, 51 to 53, for example. In addition to the motor 9, a resistor 7 and a capacitor 8 are connected to the motor drive circuit 1.

  In the following, a case where each output transistor is an N-channel power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) will be described as an example. In addition, the phases of the drive coils 91 to 93 are a U phase, a V phase, and a W phase, respectively.

  The drains of the high-side output transistors 41 to 43 are all connected to the power supply potential VCC via the terminal 65. The sources of the low-side output transistors 51 to 53 are all connected to the ground potential via a resistor 7 externally connected to the terminal 66. Further, the output transistors 41 to 43 are connected in series with the output transistors 51 to 53, respectively, and each connection point is connected to the terminals 61 to 63. The drive coils 91 to 93 are connected to the terminals 61 to 63, respectively, and the neutral point of the drive coils 91 to 93 is connected to the terminal 64.

  Each voltage U, V, W, and COM of the terminals 61 to 64 is input to the selection circuit 32. Further, the input voltage Vin and the reference voltage Vref are input from the selection circuit 32 to the comparator circuit 10. Further, the capacitor 8 is externally connected via terminals 67 and 68 between the signal lines of the input voltage Vin and the reference voltage Vref.

  The comparison result signal Vout output from the comparator circuit 10 is input to the switching control circuit 31. The switching signals S41 to S43 and S51 to S53 output from the switching control circuit 31 are input to the gates of the output transistors 41 to 43 and 51 to 53, respectively.

=== Outline of operation of entire motor driving circuit ===
Next, an outline of the operation of the entire motor drive circuit will be described.
The output transistors 41 to 43, 51 to 53 are subjected to switching control according to switching signals S41 to S43 and S51 to S53 which are binary signals, and supply driving current to the driving coils 91 to 93 of the motor 9. For example, when the output transistors 41 and 52 are on, a drive current flows from the power supply potential VCC to the ground potential via the output transistor 41, the drive coils 91 and 92, the output transistor 52, and the resistor 7. Therefore, in this case, a drive current flows from the U phase to the V phase. For example, when the output transistors 43 and 52 are on, the drive current flows from the W phase to the V phase.

  The selection circuit 32 sequentially selects any one of the voltages U, V, and W of the terminals 61 to 63 (U phase, V phase, and W phase) and supplies the input voltage Vin to the comparator circuit 10. input. Further, the selection circuit 32 inputs the voltage COM at the terminal 64 (the neutral point of the drive coils 91 to 93) to the comparator circuit 10 as the reference voltage Vref. Furthermore, the capacitor 8 functions as a filter that removes noise of the input signal of the comparator circuit 10 by being connected between the signal lines of the input voltage Vin and the reference voltage Vref.

  The comparator circuit 10 compares the input voltage Vin and the reference voltage Vref, and outputs the comparison result as a comparison result signal Vout that is a binary signal. Further, the switching control circuit 31 detects the position of the rotor based on the comparison result signal Vout, and generates switching signals S41 to S43 and S51 to S53 according to the detected position of the rotor.

<First Embodiment>
=== Configuration of Comparator Circuit ===
The configuration of the comparator circuit according to the first embodiment of the present invention will be described below with reference to FIG.

  1 includes, for example, a control circuit 11a, an inverter (inverting circuit) 12, a clock generation circuit 21a, capacitors C1 to C3, D latches (transparent latches) L1 and L2, and a switch circuit S1a. S1b and S2 are included. In the present embodiment, the switch circuits S1a and S1b correspond to the first switch circuit.

  The clock signal φA output from the clock generation circuit 21a is a control signal for on / off control of the switch circuits S1a and S2. The clock signal φB is a control signal for on / off control of the switch circuit S1b.

  The reference voltage Vref (first voltage) is input to the input terminal (the other end) of the (first) capacitor C1 via the switch circuit S1a, and the input voltage Vin (second voltage) via the switch circuit S1b. Is input). The hysteresis control signals Vc2 and Vc3 output from the control circuit 11a are input to the input ends (the other ends) of the (second) capacitor C2 and the (third) capacitor C3, respectively. Furthermore, the output ends (one end) of the capacitors C1 to C3 are connected in common to the input end of the inverter 12. The output terminal and the input terminal of the inverter 12 are connected via a (second) switch circuit S2.

  The clock signal φB is input to the CK input (clock input) of the D latch L1 (first latch circuit), and the output signal of the inverter 12 is input to the D input (data input). The comparison result signal Vout output from the D latch L1 is output from the comparator circuit 10.

  The clock signal φA is input to the CK input of the D latch L2 (second latch circuit), and the output signal of the D latch L1 is input to the D input. The delay result signal VoD output from the D latch L2 is input to the control circuit 11a.

=== Operation of the comparator circuit ===
Next, the operation of the comparator circuit in this embodiment will be described. In the following description, the low level corresponds to the first logic level, and the high level corresponds to the second logic level.

  Clock generation circuit 21a outputs clock signals φA and φB that are in opposite phases and alternately at a high level. The switch circuits S1a and S2 are turned on while the clock signal φA is at a high level, and the switch circuit S1b is turned on while the clock signal φB is at a high level. In the present embodiment, periods when the clock signals φA and φB are at a high level are referred to as a sampling period (first period) and a comparison period (second period), respectively.

First, the operation in the sampling period will be described.
When the switch circuit S1a is turned on by the high level clock signal φA, the voltage V1 at the input terminal of the capacitor C1 becomes equal to the reference voltage Vref. When the switch circuit S2 is turned on, the voltage V2 at the output terminal of the capacitor C1 becomes equal to the threshold voltage VthI of the inverter 12. Therefore, the charge Q1a accumulated in the capacitor C1 during the sampling period is
Q1a = C1 × (VthI−Vref)
It becomes.

  Since the low level clock signal φB is input to the CK input of the D latch L1, the level of the comparison result signal Vout is held and does not change. Further, since the high level clock signal φA is input to the CK input of the D latch L2, the level of the delay result signal VoD becomes equal to the level of the comparison result signal Vout.

The control circuit 11a sets the hysteresis control signal Vc2 to the high level and the hysteresis control signal Vc3 to the low level regardless of the level of the delay result signal VoD. Therefore, assuming that the high level voltage is VDD and the low level voltage is 0, the charges Q2a and Q3a respectively stored in the capacitors C2 and C3 in the sampling period are
Q2a = C2 × (VthI−VDD),
Q3a = C3 × (VthI-0)
It becomes.

Next, the operation in the comparison period will be described.
When the switch circuit S1b is turned on by the high level clock signal φB, the voltage V1 at the input terminal of the capacitor C1 becomes equal to the input voltage Vin. Further, the switch circuit S2 is turned off. Therefore, in the comparison period, the charge Q1b accumulated in the capacitor C1 is
Q1b = C1 × (V2−Vin)
It becomes.

  Since the high level clock signal φB is input to the CK input of the D latch L1, the level of the comparison result signal Vout becomes equal to the level of the output signal of the inverter 12. In addition, since the low level clock signal φA is input to the CK input of the D latch L2, the level of the delay result signal VoD is held and does not change. Accordingly, the delay result signal VoD having the same level as the comparison result signal Vout in the previous comparison period is input to the control circuit 11a.

When the delay result signal VoD is at high level, the control circuit 11a sets the hysteresis control signal Vc2 to low level and the hysteresis control signal Vc3 to high level. Therefore, in this case, charges Q2b and Q3b stored in capacitors C2 and C3, respectively, in the comparison period are
Q2b = C2 × (V2-0),
Q3b = C3 × (V2−VDD)
It becomes.

Here, according to the law of charge conservation,
Q1a + Q2a + Q3a = Q1b + Q2b + Q3b
Therefore, if V2 ≧ VthI, that is,
Vin ≧ Vref + [(C2−C3) / C1] × VDD (= VthH)
In this case, the comparison result signal Vout becomes a low level.

On the other hand, when the delay result signal VoD is at the low level, the control circuit 11a sets the hysteresis control signals Vc2 and Vc3 to the high level. Therefore, in this case, the charges Q2b and Q3b are Q2b = C2 × (V2−VDD),
Q3b = C3 × (V2−VDD)
It becomes. And when V2 ≦ VthI, that is,
Vin ≦ Vref− (C3 / C1) × VDD (= VthL <VthH)
In this case, the comparison result signal Vout becomes high level.

  In this manner, (Vc2, Vc3) = (VDD, 0) is set in the sampling period, and (Vc2, Vc3) = (0, VDD) or (VDD) is set in the comparison period according to the delay result signal VoD. , VDD), hysteresis characteristics can be added to the comparator circuit 10. When the input voltage Vin reaches the upper (higher) threshold voltage VthH, the comparison result signal Vout becomes a low level, and the threshold voltage is set to the lower (lower) threshold by the low-level delay result signal VoD. The voltage is switched to VthL. On the other hand, when the input voltage Vin reaches the lower threshold voltage VthL, the comparison result signal Vout becomes high level, and the threshold voltage is switched to the upper threshold voltage VthH by the high level delay result signal VoD.

Here, as an example, FIG. 3 shows the relationship between the input voltage Vin and the change in threshold voltage when C1 = A, C2 = B, and C3 = B / 2. In this case, the upper threshold voltage VthH, the lower threshold voltage VthL, and the hysteresis width HYS (= VthH−VthL) are VthH = Vref + (1/2) × (B / A) × VDD,
VthL = Vref− (1/2) × (B / A) × VDD,
HYS = (B / A) × VDD
Thus, the comparator circuit 10 has a vertically symmetrical hysteresis characteristic with respect to the reference voltage Vref.

  In the comparator circuit 10 of the present embodiment, the input voltage Vin is applied only to the capacitor C1, and the logic level voltage VDD is applied to the capacitors C2 and C3. Therefore, even when the input voltage Vin higher than the voltage VDD is applied to the comparator circuit 10, only the capacitor C1 may be a capacitor having a high withstand voltage characteristic, and the circuit area can be suppressed. Also in the second and third embodiments, only the capacitor C1 may be a capacitor having a high withstand voltage characteristic.

Second Embodiment
=== Configuration of Comparator Circuit ===
The configuration of the comparator circuit in the second embodiment of the present invention will be described below with reference to FIG.

  4 includes, for example, a control circuit 11b, an inverter 12, an AND circuit (logical product circuit) 13, a NOR circuit (negative logical sum circuit) 14, an RS latch (RS type flip-flop) 15, a clock. The circuit includes a generation circuit 21b, an OR circuit (OR circuit) 22, capacitors C1 to C3, D latches L1 and L3, and switch circuits S1a, S1d, and S2. In the present embodiment, the switch circuits S1a and S1d correspond to the first switch circuit, and the AND circuit 13, the NOR circuit 14, and the RS latch 15 correspond to the fourth latch circuit.

  The clock signal φA output from the clock generation circuit 21b is a control signal for on / off control of the switch circuits S1a and S2. Further, the clock signals φB and φC are input to the OR circuit 22, and the clock signal φD output from the OR circuit 22 is a control signal for on / off control of the switch circuit S1d.

  The reference voltage Vref is input to the input terminal of the capacitor C1 through the switch circuit S1a, and the input voltage Vin is input through the switch circuit S1d. The hysteresis control signals Vc2 and Vc3 output from the control circuit 11b are input to the input terminals of the capacitors C2 and C3, respectively. Further, as in the first embodiment, the output terminals of the capacitors C1 to C3 are connected in common to the input terminal of the inverter 12. The output terminal and the input terminal of the inverter 12 are connected via the switch circuit S2.

  Clock signals φB and φC are input to the CK inputs of the D latch L1 and D latch L3 (third latch circuit), respectively, and the output signal of the inverter 12 is input to the D input. The upper comparison result signal Vo1 and the lower comparison result signal Vo2 output from the D latches L1 and L3, respectively, are output from the comparator circuit 10.

  The AND circuit 13 and the NOR circuit 14 both receive the upper comparison result signal Vo1 and the lower comparison result signal Vo2. The output signal of the AND circuit 13 is input to the S input (set input) of the RS latch 15, and the output signal of the NOR circuit 14 is input to the R input (reset input). The comparison result signal Vout output from the RS latch 15 is output from the comparator circuit 10.

=== Operation of the comparator circuit ===
Next, the operation of the comparator circuit in this embodiment will be described. In the present embodiment, as in the first embodiment, a case where C1 = A, C2 = B, and C3 = B / 2 will be described as an example.

  The clock generation circuit 21b outputs clock signals φA, φB, and φC whose phases are different from each other and any one of them sequentially becomes a high level. The switch circuits S1a and S2 are turned on while the clock signal φA is at a high level, and the switch circuit S1d is turned on while the clock signal φB or φC is at a high level. In the present embodiment, the periods when the clock signals φA, φB, and φC are at the high level are the sampling period (first period), the first comparison period (second period), and the second comparison period, respectively. (Third period).

First, the operation in the sampling period will be described.
As in the first embodiment, the charge Q1a accumulated in the capacitor C1 during the sampling period is
Q1a = A × (VthI−Vref)
It becomes. Since the low level clock signals φB and φC are input to the CK inputs of the D latches L1 and L3, respectively, the levels of the upper comparison result signal Vo1 and the lower comparison result signal Vo2 are both held. It does not change.

The control circuit 11b sets the hysteresis control signal Vc2 to high level and the hysteresis control signal Vc3 to low level. Therefore, assuming that the high level voltage is VDD and the low level voltage is 0, the charges Q2a and Q3a respectively stored in the capacitors C2 and C3 in the sampling period are the same as in the first embodiment.
Q2a = B × (VthI−VDD),
Q3a = (B / 2) × (VthI-0)
It becomes.

Next, the operation in the first comparison period will be described.
When the switch circuit S1d is turned on by the high level clock signal φD, the voltage V1 at the input terminal of the capacitor C1 becomes equal to the input voltage Vin, as in the comparison period of the first embodiment. Further, the switch circuit S2 is turned off. Therefore, in the first comparison period, the charge Q1b accumulated in the capacitor C1 is
Q1b = A × (V2-Vin)
It becomes.

  Since the high level clock signal φB is inputted to the CK input of the D latch L1, the level of the upper comparison result signal Vo1 becomes equal to the level of the output signal of the inverter 12. Further, since the low level clock signal φC is input to the CK input of the D latch L3, the level of the lower comparison result signal Vo2 is held and does not change.

The control circuit 11b sets the hysteresis control signal Vc2 to a low level and sets the hysteresis control signal Vc3 to a high level. Therefore, similarly to the comparison period when the delay result signal VoD in the first embodiment is at the high level, the charges Q2b and Q3b respectively stored in the capacitors C2 and C3 in the first comparison period are
Q2b = B × (V2-0),
Q3b = (B / 2) × (V2−VDD)
It becomes. And when V2 ≧ VthI, that is,
Vin ≧ Vref + (1/2) × (B / A) × VDD (= VthH)
In this case, the upper comparison result signal Vo1 becomes low level.

Next, the operation in the second comparison period will be described.
Similar to the first comparison period, the voltage V1 at the input terminal of the capacitor C1 is equal to the input voltage Vin. Further, the switch circuit S2 is turned off. Therefore, in the second comparison period, the charge Q1c accumulated in the capacitor C1 is
Q1c = A × (V2-Vin)
It becomes.

  Since the low level clock signal φB is input to the CK input of the D latch L1, the level of the upper comparison result signal Vo1 is held and does not change. Further, since the high level clock signal φC is inputted to the CK input of the D latch L3, the level of the lower comparison result signal Vo2 becomes equal to the level of the output signal of the inverter 12.

The control circuit 11b sets the hysteresis control signals Vc2 and Vc3 to the high level. Therefore, as in the comparison period when the delay result signal VoD in the first embodiment is at the low level, the charges Q2c and Q3c stored in the capacitors C2 and C3 in the second comparison period are respectively
Q2c = B × (V2−VDD),
Q3c = (B / 2) × (V2−VDD)
It becomes. And when V2 ≦ VthI, that is,
Vin ≦ Vref− (1/2) × (B / A) × VDD (= VthL)
In this case, the lower comparison result signal Vo2 becomes high level.

  When Vin ≧ VthH (> VthL), that is, when both the upper comparison result signal Vo1 and the lower comparison result signal Vo2 are low level, the R input of the RS latch 15 becomes high level. The result signal Vout becomes low level. Further, when Vin ≦ VthL (<VthH), that is, when both the upper comparison result signal Vo1 and the lower comparison result signal Vo2 are at the high level, the S input of the RS latch 15 is at the high level. The comparison result signal Vout becomes a high level. On the other hand, when the levels of the upper comparison result signal Vo1 and the lower comparison result signal Vo2 are different, the level of the comparison result signal Vout is held and does not change.

  In this way, (Vc2, Vc3) = (VDD, 0) is set in the sampling period, (Vc2, Vc3) = (0, VDD) is set in the first comparison period, and in the second comparison period. By setting (Vc2, Vc3) = (VDD, VDD), a hysteresis characteristic can be added to the comparator circuit 10 as in the first embodiment. In this embodiment, the upper comparison result signal Vo1 and the lower comparison result signal Vo2 are also output, so that the input voltage Vin does not reach either the upper threshold voltage VthH or the lower threshold voltage VthL, that is, VthL. It is also possible to distinguish when <Vin <VthH.

<Third Embodiment>
=== Configuration of Comparator Circuit ===
The configuration of the comparator circuit according to the third embodiment of the present invention will be described below with reference to FIG.
The comparator circuit 10 shown in FIG. 5 includes a control circuit 11c instead of the control circuit 11b, and further includes capacitors C4 and C5 with respect to the comparator circuit 10 of the second embodiment. The hysteresis control signals Vc2 to Vc5 output from the control circuit 11c are input to the input ends (the other ends) of the capacitors C2 to C5, respectively, and the output ends (one end) of the capacitors C1 to C5 are the input ends of the inverter 12, respectively. Connected in common. In the present embodiment, the capacitors C3 to C5 correspond to a third capacitor.

=== Operation of the comparator circuit ===
Next, the operation of the comparator circuit in this embodiment will be described. In the present embodiment, the capacities of the capacitors C3 to C5 are set so as to be sequentially reduced by half with respect to the capacity of the capacitor C2. In the following, a case where C1 = A, C2 = B, C3 = B / 2, C4 = B / 4, and C5 = B / 8 will be described as an example.

First, the operation in the sampling period will be described.
As in the second embodiment, the charge Q1a accumulated in the capacitor C1 during the sampling period is
Q1a = A × (VthI−Vref)
It becomes. Further, the levels of the upper comparison result signal Vo1 and the lower comparison result signal Vo2 are both held and do not change.

The control circuit 11c sets the hysteresis control signal Vc2 to the high level and sets the hysteresis control signals Vc3 to Vc5 to the low level. Accordingly, when the high level voltage is VDD and the low level voltage is 0, the charges Q2a to Q5a accumulated in the capacitors C2 to C5 in the sampling period are respectively
Q2a = B × (VthI−VDD),
Q3a = (B / 2) × (VthI-0),
Q4a = (B / 4) × (VthI-0),
Q5a = (B / 8) × (VthI-0)
It becomes.

Next, the operation in the first and second comparison periods will be described.
Similarly to the second embodiment, in the first and second comparison periods, the charges Q1b and Q1c stored in the capacitor C1 are both Q1b = Q1c = A × (V2−Vin)
It becomes. Further, the level of the upper comparison result signal Vo1 becomes equal to the level of the output signal of the inverter 12 in the first comparison period, and is held and does not change in the second comparison period. Further, the level of the lower comparison result signal Vo2 is held in the first comparison period, does not change, and becomes equal to the level of the output signal of the inverter 12 in the second comparison period.

  In the present embodiment, the control circuit 11c can change the combination of levels of the hysteresis control signals Vc2 to Vc5 in the first and second comparison periods. Hereinafter, as an example, a case where the levels of the hysteresis control signals Vc2 to Vc5 are set as in setting 1 in FIG. 6 will be described.

In the first comparison period, the charges Q2b to Q5b stored in the capacitors C2 to C5, respectively,
Q2b = B × (V2-0),
Q3b = (B / 2) × (V2−VDD),
Q4b = (B / 4) × (V2−VDD),
Q5b = (B / 8) × (V2−VDD)
It becomes.

In the second comparison period, the charges Q2c to Q5c stored in the capacitors C2 to C5, respectively,
Q2c = B × (V2−VDD),
Q3c = (B / 2) × (V2-0),
Q4c = (B / 4) × (V2-0),
Q5c = (B / 8) × (V2−VDD)
It becomes.

Therefore, the upper threshold voltage VthH, the lower threshold voltage VthL, and the hysteresis width HYS are VthH = Vref + (1/8) × (B / A) × VDD,
VthL = Vref− (1/8) × (B / A) × VDD,
HYS = (B / 4A) × VDD (= HYS0)
Thus, the comparator circuit 10 has a vertically symmetrical hysteresis characteristic with respect to the reference voltage Vref.

  Further, as shown in FIG. 6, by changing the combination of the levels of the hysteresis control signals Vc2 to Vc5 in the first and second comparison periods as set 2 to set 7, the hysteresis width is fixed. It can be made variable at step HYS0. It should be noted that the hysteresis width can be set to a constant step similarly to the present embodiment by adding a capacitor whose capacitance is sequentially reduced by half to the comparator circuit 10 of the first embodiment. Can be made variable.

  As described above, in the chopper comparator circuit 10 having hysteresis characteristics, the hysteresis control signal Vc3 (or Vc5) is set to the low level, the hysteresis control signal Vc2 is set to the high level during the sampling period, and the comparison period includes By setting the hysteresis control signal Vc3 (or at least one of Vc5) to high level and the hysteresis control signal Vc2 to low level or high level, the input voltage Vin higher than the logic level voltage VDD is applied only to the capacitor C1. Thus, capacitors that require high withstand voltage characteristics can be reduced.

  In the comparator circuit 10 of the first embodiment, in the comparison period, the hysteresis control signals Vc2 and Vc3 are output in response to the delay result signal VoD having the same level as the comparison result signal Vout in the previous comparison period. The threshold voltage can be switched based on the comparison result between the voltage Vin and the upper threshold voltage VthH or the lower threshold voltage VthL.

  Further, in the comparator circuit 10 of the second embodiment, in the second comparison period, hysteresis control signals Vc2 and Vc3 having a different combination from the sampling period and the first comparison period are output, and the upper comparison is performed from the D latches L1 and L3, respectively. By outputting the result signal Vo1 and the lower comparison result signal Vo2, the hysteresis characteristic is added and the input voltage Vin reaches both the upper threshold voltage VthH and the lower threshold voltage VthL as in the first embodiment. It is also possible to distinguish when not.

  Further, in the comparator circuit 10 of the third embodiment, the hysteresis width can be varied in a constant step by setting the capacitances of the capacitors C3 to C5 to be successively reduced by half with respect to the capacitance of the capacitor C2. It can be.

  Further, in the motor drive circuit 1 shown in FIG. 2, the neutral point voltage COM is defined by using any one of the voltages U, V, and W of each phase of the drive coils 91 to 93 as the input voltage Vin. By inputting the voltage Vref to the comparator circuit 10 respectively, the position of the rotor is detected based on the comparison result signal Vout, and the output transistors 41 to 43 and 51 to 53 are subjected to switching control according to the detected rotor position. can do.

  In addition, the said embodiment is for making an understanding of this invention easy, and is not for limiting and interpreting this invention. The present invention can be changed and improved without departing from the gist thereof, and equivalents thereof are also included in the present invention.

  In the above embodiment, the low level corresponds to the first logic level and the high level corresponds to the second logic level. However, the present invention is not limited to this. In the description of the operation of the comparator circuit of the first to third embodiments, hysteresis characteristics can be similarly added even when the first logic level and the second logic level are interchanged.

DESCRIPTION OF SYMBOLS 1 Motor drive circuit 7 Resistance 8 Capacitor 9 Motor 10 Comparator circuit 11a, 11b, 11c Control circuit 12 Inverter (inversion circuit)
13 AND circuit (logical product circuit)
14 NOR circuit (Negative OR circuit)
15 RS latch (RS flip-flop)
21a, 21b Clock generation circuit 22 OR circuit (OR circuit)
31 switching control circuit 32 selection circuit 41, 42, 43, 51, 52, 53 output transistor 61, 62, 63, 64, 65, 66, 67, 68 terminal 91, 92, 93 drive coil C1, C2, C3, C4 , C5 capacitors L1, L2, L3 D latch (transparent latch)
S1a, S1b, S1d, S2 switch circuit

Claims (5)

A first capacitor having one end connected in common, a second capacitor, and one or more third capacitors;
A first switch circuit that sequentially applies one of a first voltage and a second voltage to the other end of the first capacitor;
An inverter having an input terminal connected to a connection point of the first to third capacitors;
A second switch circuit for connecting an input terminal and an output terminal of the inverter in a first period in which the first voltage is applied to the other end of the first capacitor;
After the first period, in the second period in which the second voltage is applied to the other end of the first capacitor, the output level of the inverter is output, and in the first period, A first latch circuit that holds and outputs the output level of the inverter at the end of the second period;
In the first period, a first logic level voltage is applied to the other end of the third capacitor, and a second logic level voltage is applied to the other end of the second capacitor, In the second period, a voltage of the second logic level is applied to at least one other end of the third capacitor, and the first or second logic level is applied to the other end of the second capacitor. A control circuit for applying a voltage of
A comparator circuit comprising: In the first period, the output level of the first latch circuit is output, and in the second period, the output level of the first latch circuit at the end of the first period is held. A second latch circuit for outputting;
In the second period, the control circuit applies a voltage having a combination of logic levels according to the output level of the second latch circuit to the other ends of the second and third capacitors. The comparator circuit according to claim 1. After the second period, in the third period in which the second voltage is applied to the other end of the first capacitor, the output level of the inverter is output, and the first and second In the period, a third latch circuit that holds and outputs the output level of the inverter at the end of the third period; and
When the output levels of the first and third latch circuits are the same logic level, the same logic level is output, and when the output levels of the first and third latch circuits are not the same logic level A fourth latch circuit for holding the output level;
Further comprising
The first latch circuit outputs the output level of the inverter during the second period, and the output level of the inverter at the end of the second period during the third and first periods. Hold and output,
In the third period, the control circuit applies a voltage having a logic level of a combination different from that in the first and second periods to the other ends of the second and third capacitors. The comparator circuit according to claim 1. A plurality of the third capacitors;
The capacity of the third capacitor is set so as to be successively reduced by one-half with respect to the capacity of the second capacitor. Comparator circuit. A plurality of output transistors for supplying a driving current to a plurality of driving coils of the motor;
A comparator circuit for comparing the voltage of each phase of the multi-phase drive coil with the voltage at the neutral point of the multi-phase drive coil;
A switching control circuit that controls the switching of the plurality of output transistors according to a comparison result of the comparator circuit;
With
The comparator circuit is
A first capacitor having one end connected in common, a second capacitor, and one or more third capacitors;
A first switch circuit for sequentially applying either the neutral point voltage or the voltage of each phase to the other end of the first capacitor;
An inverter having an input terminal connected to a connection point of the first to third capacitors;
A second switch circuit for connecting an input terminal and an output terminal of the inverter in a first period in which a voltage at the neutral point is applied to the other end of the first capacitor;
After the first period, the output level of the inverter is output in the second period when the voltage of each phase is applied to the other end of the first capacitor, and in the first period, A latch circuit that holds and outputs the output level of the inverter at the end of the second period;
In the first period, a first logic level voltage is applied to the other end of the third capacitor, and a second logic level voltage is applied to the other end of the second capacitor, In the second period, a voltage of the second logic level is applied to at least one other end of the third capacitor, and the first or second logic level is applied to the other end of the second capacitor. A control circuit for applying a voltage of
A motor drive circuit comprising:

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