CN117526740A - Voltage comparator for correcting offset voltage - Google Patents

Voltage comparator for correcting offset voltage Download PDF

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Publication number
CN117526740A
CN117526740A CN202410001989.1A CN202410001989A CN117526740A CN 117526740 A CN117526740 A CN 117526740A CN 202410001989 A CN202410001989 A CN 202410001989A CN 117526740 A CN117526740 A CN 117526740A
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CN
China
Prior art keywords
pmos tube
electrically connected
amplifying unit
tube
electrode
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Granted
Application number
CN202410001989.1A
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Chinese (zh)
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CN117526740B (en
Inventor
谭在超
罗寅
丁国华
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Suzhou Covette Semiconductor Co ltd
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Suzhou Covette Semiconductor Co ltd
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Priority to CN202410001989.1A priority Critical patent/CN117526740B/en
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer

Abstract

The invention relates to the technical field of voltage comparison and discloses a voltage comparator for correcting offset voltage, which comprises a first amplifying unit, a second amplifying unit, a third amplifying unit and a fourth amplifying unit; when the synchronous rectification circuit is used, the four-stage amplifying unit is arranged, the two output ends of the first amplifying unit are respectively and electrically connected with the two output ends of the second amplifying unit and the two input ends of the third amplifying unit, the two output ends of the third amplifying unit are respectively and electrically connected with the two input ends of the second amplifying unit through the second switch branch, and the node on each second switch branch is electrically connected with the energy storage unit, so that the reference voltage input by the first amplifying unit and the input offset voltage can be output together for zero offset through the virtual short characteristic of the second amplifying unit, the elimination of the input offset voltage is realized, the consistency of voltage comparison points is realized, and the efficiency and reliability of synchronous rectification are improved.

Description

Voltage comparator for correcting offset voltage
Technical Field
The invention relates to the technical field of voltage comparison, in particular to a voltage comparator for correcting offset voltage.
Background
In the field of switching power supply control, in order to improve the system conversion efficiency, a synchronous rectification control technology is generally adopted to replace a schottky diode for rectification, wherein the synchronous rectification control technology is used for rectifying by controlling the on-off state of a synchronous rectification power tube.
During the follow current period of the synchronous rectification power tube in the synchronous rectification process, the voltage drop at the two ends of the drain and source of the synchronous rectification power tube needs to be detected from time to reflect the current change, as the current finally drops to 0A, the primary side switch is also turned on, in order to avoid the voltage spike caused by the simultaneous opening of the primary side switch and the secondary side switch to damage devices, the synchronous rectification power tube needs to be turned off before the current drops to 0A, so that the voltage drop between the drain and source of the synchronous rectification power tube is particularly important, once the synchronous rectification power tube is turned off, if the current does not drop to 0A at the moment, the follow current is necessarily carried out through the body diode of the synchronous rectification power tube, and the voltage drop of the body diode is generally 0.6V, so that great conduction loss is caused, the turn-off threshold of the synchronous rectification power tube needs to be close to 0mV as much as possible, and the turn-off point is generally set to be between-10 mV and 0 mV.
At present, a comparator is used for comparing the voltage drop between the drain electrode and the source electrode of the synchronous rectification power tube with a reference voltage to judge whether the voltage drop between the drain electrode and the source electrode reaches a threshold value or not. However, since the comparator generates offset voltage in the design production process due to the matching property of the input pair of tubes, and the offset voltage is in the range of 0-10 mV, the designed turn-off threshold value has large discreteness, and meanwhile, since the range of the turn-off threshold value is too small, the chip wants to improve the consistency through the programming technology, which brings great difficulty. There is a need for a voltage comparator that can functionally reduce the input offset voltage.
Disclosure of Invention
In view of the shortcomings of the background technology, the invention provides a voltage comparator for correcting offset voltage, which can reduce the input offset voltage of the voltage comparator.
In order to solve the technical problems, in a first aspect, the present invention provides the following technical solutions: a voltage comparator for correcting offset voltage comprises a first amplification unit with double inputs and double outputs, a second amplification unit with double inputs and double outputs, a third amplification unit with double inputs and double outputs and a fourth amplification unit with double inputs and single output;
the first input end of the first amplifying unit is electrically connected with the output end of the first control switch, and the second input end of the first amplifying unit is electrically connected with the output end of the second control switch;
at least one input end of the first amplifying unit is electrically connected with a switch branch circuit, and the switch branch circuit is used for inputting a comparison voltage and controlling whether the comparison voltage is input to the first amplifying unit or not based on an input control signal;
the two output ends of the first amplifying unit are respectively and electrically connected with the two output ends of the second amplifying unit and the two input ends of the third amplifying unit;
two output ends of the third amplifying unit are respectively and electrically connected with two input ends of the second amplifying unit through second switch branches, and at least one node except the nodes electrically connected with the third amplifying unit on each second switch branch is electrically connected with an energy storage unit; the two output ends of the third amplifying unit are electrically connected with the two input ends of the fourth amplifying unit, and the output end of the fourth amplifying unit is used for outputting a voltage comparison result.
In a certain implementation manner of the first aspect, an output terminal of the fourth amplifying unit is electrically connected to a schmitt trigger.
In a certain implementation manner of the first aspect, the control end of the first control switch, the control end of the second control switch and the two second switch branches simultaneously input a SET signal SET, and are turned on when the SET signal SET is at a high level and turned off when the SET signal SET is at a low level;
the switch branch is turned on when the control signal is in a high level, and turned off when the control signal is in a low level;
the SET signal SET and the control signal are periodic signals with the same frequency, the rising edge of the SET signal SET is the same as the falling edge of the control signal, and the high-level duty ratio of the SET signal SET is smaller than the low-level duty ratio of the control signal.
In a certain implementation manner of the first aspect, the first control switch and the second control switch are an NMOS transistor NM1 and an NMOS transistor NM8, respectively, a drain electrode of the NMOS transistor NM1 is electrically connected to the first input terminal of the first amplifying unit, a drain electrode of the NMOS transistor NM8 is electrically connected to the second input terminal of the first amplifying unit, and a gate electrode of the NMOS transistor NM1 and a gate electrode of the NMOS transistor NM8 are used for inputting the SET signal SET.
In a certain implementation manner of the first aspect, the second switching branch includes two NMOS tubes connected in series, a drain electrode of the NMOS tube at the front end is electrically connected with an output end of the third amplifying unit, a source electrode of the NMOS tube at the rear end is electrically connected with an input end of the second amplifying unit, a source electrode of each NMOS tube is respectively electrically connected with an energy storage unit, and gates of the two NMOS tubes are used for inputting the SET signal SET.
In a certain implementation manner of the first aspect, the switch branch includes an NMOS transistor NM2, an NMOS transistor NM3, and a resistor R1, where a drain electrode of the NMOS transistor NM2 is electrically connected to an input end of the first amplifying unit, a gate electrode of the NMOS transistor NM2 is electrically connected to a gate electrode of the NMOS transistor NM3, and is used for inputting the control signal, a source electrode of the NMOS transistor NM2 is electrically connected to a drain electrode of the NMOS transistor NM3, and a source electrode of the NMOS transistor NM3 is electrically connected to one end of the resistor R1.
In a certain implementation manner of the first aspect, a drain of the NMOS transistor NM3 is electrically connected to a drain of the NMOS transistor NM4, a source of the NMOS transistor NM4 is grounded, and a gate of the NMOS transistor NM4 is used for inputting a reset signal RST, where the reset signal RST is opposite to the control signal.
In a certain implementation manner of the first aspect, the first amplifying unit includes a PMOS tube PM1, a PMOS tube PM2, a resistor R2, and a resistor R3; the source electrode of the PMOS tube PM1 is electrically connected with the source electrode of the PMOS tube PM2 and is used for inputting a first bias current, the grid electrode of the PMOS tube PM1 and the grid electrode of the PMOS tube PM2 are two input ends of the first amplifying unit, and the drain electrode of the PMOS tube PM1 and the drain electrode of the PMOS tube PM2 are two output ends of the first amplifying unit and are grounded through a resistor R2 and a resistor R3 respectively;
the second amplifying unit comprises a PMOS tube PM3 and a PMOS tube PM4; the source electrode of the PMOS tube PM3 is electrically connected with the source electrode of the PMOS tube PM4 and is used for inputting a second bias current, the grid electrode of the PMOS tube PM3 and the grid electrode of the PMOS tube PM4 are two input ends of the second amplifying unit, the drain electrode of the PMOS tube PM3 and the drain electrode of the PMOS tube PM4 are two output ends of the second amplifying unit, the drain electrode of the PMOS tube PM3 is electrically connected with the drain electrode of the PMOS tube PM1, and the drain electrode of the PMOS tube PM4 is electrically connected with the drain electrode of the PMOS tube PM 2;
the third amplifying unit comprises a PMOS tube PM5, a PMOS tube PM6, a resistor R5 and a resistor R6; the source electrode of the PMOS tube PM5 is electrically connected with the source electrode of the PMOS tube PM6 and is used for inputting a third bias current, the grid electrode of the PMOS tube PM5 and the grid electrode of the PMOS tube PM6 are two input ends of a third amplifying unit, the grid electrode of the PMOS tube PM5 is electrically connected with the drain electrode of the PMOS tube PM4, the grid electrode of the PMOS tube PM6 is electrically connected with the drain electrode of the PMOS tube PM3, the drain electrode of the PMOS tube PM5 and the drain electrode of the PMOS tube PM6 are two output ends of the third amplifying unit, and the drain electrode of the PMOS tube PM5 and the drain electrode of the PMOS tube PM6 are respectively grounded through a resistor R5 and a resistor R6 and are electrically connected with two second switch branches;
the fourth amplifying unit comprises a PMOS tube PM7, a PMOS tube PM8, an NMOS tube NM13, an NMOS tube NM14, an NMOS tube NM15 and an NMOS tube NM16; the source electrode of the PMOS tube PM7 is electrically connected to the source electrode of the PMOS tube PM8, for inputting a fourth bias current, the gate electrode of the PMOS tube PM7 and the gate electrode of the PMOS tube PM8 are two input ends of the fourth amplifying unit, the gate electrode of the PMOS tube PM7 is electrically connected to the drain electrode of the PMOS tube PM5, the gate electrode of the PMOS tube PM8 is electrically connected to the drain electrode of the PMOS tube PM6, the drain electrode of the PMOS tube PM7 is electrically connected to the drain electrode of the NMOS tube NM13, the gate electrode of the NMOS tube NM13 and the gate electrode of the NMOS tube NM14, the source electrode of the NMOS tube NM13 and the gate electrode of the NMOS tube NM15 are electrically connected to the drain electrode of the NMOS tube NM14, the source electrode of the NMOS tube NM15 and the source electrode of the NMOS tube NM16 are electrically connected to each other, the drain electrode of the NMOS tube NM15 is an output end of the fourth amplifying unit, for inputting a fifth bias current, and the gate electrode of the NMOS tube NM16 is used for inputting a reset signal RST.
In a certain implementation manner of the first aspect, the present invention further includes a current mirror, where the current mirror includes a PMOS pipe PM9, a PMOS pipe PM10, a PMOS pipe PM11, a PMOS pipe PM12, a PMOS pipe PM13, and a PMOS pipe PM14; the source electrode of the PMOS tube PM9 is respectively and electrically connected with the source electrode of the PMOS tube PM10, the source electrode of the PMOS tube PM11, the source electrode of the PMOS tube PM12, the source electrode of the PMOS tube PM13 and the source electrode of the PMOS tube PM14 for accessing a power supply; the grid electrode of the PMOS tube PM9 is electrically connected with the drain electrode of the PMOS tube PM9, the grid electrode of the PMOS tube PM10, the grid electrode of the PMOS tube PM11, the grid electrode of the PMOS tube PM12, the grid electrode of the PMOS tube PM13 and the grid electrode of the PMOS tube PM14 respectively and is used for inputting bias current IBP; the drain electrode of the PMOS transistor PM10 is electrically connected to the source electrode of the PMOS transistor PM1, the first bias current is input to the first amplifying unit, the drain electrode of the PMOS transistor PM11 is electrically connected to the source electrode of the PMOS transistor PM3, the second bias current is input to the second amplifying unit, the drain electrode of the PMOS transistor PM12 is electrically connected to the source electrode of the PMOS transistor PM5, the third bias current is input to the third amplifying unit, the drain electrode of the PMOS transistor PM13 is electrically connected to the source electrode of the PMOS transistor PM7, the fourth bias current is input to the fourth amplifying unit, the drain electrode of the PMOS transistor PM14 is electrically connected to the drain electrode of the NMOS transistor NM15, and the fifth bias current is input to the drain electrode of the NMOS transistor NM 15.
In a certain implementation manner of the first aspect, two input ends of the first switch unit are respectively and electrically connected with a switch branch, and one switch branch is used for inputting a comparison voltage and controlling whether the comparison voltage is input to an input end of the first amplifying unit electrically connected with one switch branch or not based on an input control signal; the other switching branch controls whether to pull down a signal of an input terminal electrically connected with the first amplifying unit and the other switching branch based on the input control signal.
Compared with the prior art, the invention has the following beneficial effects: according to the invention, the four-stage amplifying unit is arranged, the two output ends of the first amplifying unit are respectively and electrically connected with the two output ends of the second amplifying unit and the two input ends of the third amplifying unit, the two output ends of the third amplifying unit are respectively and electrically connected with the two input ends of the second amplifying unit through the second switch branches, and at least one node of the nodes which are electrically connected with the third amplifying unit except the second switch branches is electrically connected with the energy storage unit, so that the reference voltage and the input offset voltage which are input by the first amplifying unit can be output together with zero offset through the virtual short characteristic of the second amplifying unit, thereby eliminating the input offset voltage, realizing the consistency of voltage comparison points and improving the efficiency reliability of synchronous rectification.
Drawings
FIG. 1 is a schematic view of the structure of the present invention in an embodiment;
fig. 2 is a circuit diagram of a first amplifying unit, a first control switch, a second control switch and a switch branch in the embodiment;
FIG. 3 is another circuit diagram of a first amplifying unit, a first control switch, a second control switch and a switch branch in an embodiment;
fig. 4 is a circuit diagram of a second amplifying unit and a second switching leg and an energy storage unit in an embodiment;
fig. 5 is a circuit diagram of a third amplifying unit, a fourth amplifying unit, and a schmitt trigger in the embodiment;
fig. 6 is a waveform diagram of a control signal, a SET signal SET, and a reset signal RST in the embodiment;
fig. 7 is a circuit diagram of a current mirror in an embodiment.
Detailed Description
The invention will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic representations which merely illustrate the basic structure of the invention and therefore show only the structures which are relevant to the invention.
As shown in fig. 1, a voltage comparator for correcting offset voltage includes a first amplification unit 1 with dual input and dual output, a second amplification unit 2 with dual input and dual output, a third amplification unit 3 with dual input and dual output, and a fourth amplification unit 4 with dual input and single output;
a first input end of the first amplifying unit 1 is electrically connected with an output end of the first control switch 5, and a second input end of the first amplifying unit 1 is electrically connected with an output end of the second control switch 6;
the first input end and the second input end of the first amplifying unit 1 are connected with a switch branch 7, one switch branch 7 is used for inputting a comparison voltage, and whether the comparison voltage is input into the first amplifying unit or not is controlled based on an input control signal EN; the other switching branch 7 controls whether or not to pull down the signal of the input terminal to which the first amplifying unit 1 is electrically connected with the other switching branch 7, based on the inputted control signal EN;
the two output ends of the first amplifying unit 1 are respectively and electrically connected with the two output ends of the second amplifying unit 2 and the two input ends of the third amplifying unit 3;
two output ends of the third amplifying unit 3 are respectively and electrically connected with two input ends of the second amplifying unit 2 through second switch branches 8, and at least one node except the nodes electrically connected with the third amplifying unit 3 on each second switch branch 8 is electrically connected with an energy storage unit 9; the two output ends of the third amplifying unit 3 are electrically connected with the two input ends of the fourth amplifying unit 4, and the output end AOUT of the fourth amplifying unit 4 is used for outputting a voltage comparison result.
With the configuration shown in fig. 1, by providing the switching branches 7 at the first input terminal and the second input terminal of the first amplifying unit 1, respectively, in order to achieve bilateral symmetry of the circuit, impedance matching can be achieved, so that the input impedance of the first input terminal and the second input terminal of the first amplifying unit 1 is the same in any state, and input errors are reduced. In a certain embodiment, in order to reduce the circuit area and the number of circuit components, the switching leg 7 may be connected only at the first input or at the second input of the first amplifying unit 1.
In actual use, the structure shown in fig. 1 is configured such that two output ends of the first amplifying unit 1 are electrically connected with two output ends of the second amplifying unit 2 and two input ends of the third amplifying unit 3, two output ends of the third amplifying unit 3 are electrically connected with two input ends of the second amplifying unit 2 through the second switch branches 8, and at least one node of the nodes of each second switch branch 8 except the node electrically connected with the third amplifying unit is electrically connected with the energy storage unit 9, so that the reference voltage and the input offset voltage input by the first amplifying unit 1 can be output together with zero offset through the virtual short characteristic of the second amplifying unit 2, thereby eliminating the input offset voltage, realizing consistency of voltage comparison points and improving efficiency and reliability of synchronous rectification.
Specifically, in this embodiment, the control end of the first control switch 5, the control end of the second control switch 6, and the two second switch branches 8 simultaneously input the SET signal SET, and are turned on when the SET signal SET is at a high level, and turned off when the SET signal SET is at a low level;
the switch branch 7 is turned on when the control signal EN is at a high level and turned off when the control signal EN is at a low level;
the SET signal SET and the control signal EN are periodic signals with the same frequency, the rising edge of the SET signal SET is the same as the falling edge of the control signal EN, and the high-level duty ratio of the SET signal SET is smaller than the low-level duty ratio of the control signal EN.
In this embodiment, a circuit diagram of the first amplifying unit 1, the first control switch 5, the second control switch 6 and the switch branch 7 is shown in fig. 2, in which:
the first control switch 5 is an NMOS tube NM1, the second control switch 6 is an NMOS tube NM8, the drain electrode of the NMOS tube NM1 is electrically connected with the first input end of the first amplifying unit 1, the drain electrode of the NMOS tube NM8 is electrically connected with the second input end of the first amplifying unit 1, and the grid electrode of the NMOS tube NM1 and the grid electrode of the NMOS tube NM8 are used for inputting a SET signal SET;
the two switch branches 7 have the same structure, except that the names of components in the two switch branches 7 are different, taking the switch branch 7 on the left side as an example, the switch branch 7 comprises an NMOS tube NM2, an NMOS tube NM3 and a resistor R1, the drain electrode of the NMOS tube NM2 is electrically connected with the first input end of the first amplifying unit 1, the grid electrode of the NMOS tube NM2 is electrically connected with the grid electrode of the NMOS tube NM3 and is used for inputting a control signal EN, the source electrode of the NMOS tube NM2 is electrically connected with the drain electrode of the NMOS tube NM3, the source electrode of the NMOS tube NM3 is electrically connected with one end of the resistor R1, and the other end of the resistor R1 is grounded;
in addition, the drain electrode of the NMOS tube NM3 is electrically connected with the drain electrode of the NMOS tube NM4, the source electrode of the NMOS tube NM4 is grounded, the grid electrode of the NMOS tube NM4 is used for inputting a reset signal RST, and the reset signal RST and a control signal EN are opposite signals; specifically, waveforms of the SET signal SET, the reset signal RST, and the control signal EN in the present embodiment are shown in fig. 6; when in actual use, the SET signal SET, the reset signal RST and the control signal EN can be generated by an external control signal generating circuit, so that the control is convenient, and the area of the voltage comparator can be reduced;
the first amplifying unit 1 comprises a PMOS tube PM1, a PMOS tube PM2, a resistor R2 and a resistor R3; the source electrode of the PMOS tube PM1 is electrically connected with the source electrode of the PMOS tube PM2 and used for inputting a first bias current, the grid electrode of the PMOS tube PM1 and the grid electrode of the PMOS tube PM2 are two input ends of the first amplifying unit 1, and the drain electrode of the PMOS tube PM1 and the drain electrode of the PMOS tube PM2 are two output ends of the first amplifying unit 1 and are grounded through a resistor R2 and a resistor R3 respectively.
For the circuit shown in fig. 2, when the SET signal SET is at a high level, the NMOS transistor NM1 and the NMOS transistor NM8 are turned on, the gate of the PMOS transistor PM1 is connected to the reference voltage VREF, the gate of the PMOS transistor PM2 is grounded through the NMOS transistor NM8, referring to the waveform shown in fig. 6, at this time, the control signal EN is at a low level, the NMOS transistor NM2, the NMOS transistor NM3, the NMOS transistor NM6 and the NMOS transistor NM7 are turned off, the comparison voltage VIN cannot be input to the gate of the PMOS transistor PM2, and since the comparison voltage VIN is periodically input to the first amplifying unit 1, the NMOS transistor NM4 and the NMOS transistor NM5 are turned on to clear an intermediate signal for inputting the comparison voltage VIN to the first amplifying unit 1.
For the circuit shown in fig. 2 for comparing negative comparison voltages, the circuit diagram of the first amplifying unit 1, the first control switch 5, the second control switch 6 and the switch branch 7 can be referred to in fig. 3 when a comparison of proportional comparison voltages is required.
Specifically, in the present embodiment, the circuits of the second amplifying unit 2, the second switching leg 8 and the energy storage unit 9 are as shown in fig. 4, in which:
the second switch branch 8 includes two NMOS tubes connected in series, taking the second switch branch 8 on the left side as an example, the two NMOS tubes are respectively an NMOS tube NM9 and an NMOS tube NM10, the front NMOS tube, that is, the drain electrode of the NMOS tube NM9, is electrically connected with the output end of the third amplifying unit 3, the rear NMOS tube, that is, the source electrode of the NMOS tube NM10, is electrically connected with the input end of the second amplifying unit 2, the source electrode of each NMOS tube is respectively electrically connected with an energy storage unit 9, and the gates of the two NMOS tubes are used for inputting a SET signal SET. In this embodiment, the energy storage unit 9 is a capacitor;
the second amplifying unit 2 comprises a PMOS tube PM3 and a PMOS tube PM4; the source electrode of the PMOS tube PM3 is electrically connected with the source electrode of the PMOS tube PM4 and is used for inputting a second bias current, the grid electrode of the PMOS tube PM3 and the grid electrode of the PMOS tube PM4 are two input ends of the second amplifying unit, the drain electrode of the PMOS tube PM3 and the drain electrode of the PMOS tube PM4 are two output ends of the second amplifying unit, the drain electrode of the PMOS tube PM3 is electrically connected with the drain electrode of the PMOS tube PM1, and the drain electrode of the PMOS tube PM4 is electrically connected with the drain electrode of the PMOS tube PM 2;
for the circuit shown in fig. 4, the PMOS transistor PM3 and the PMOS transistor PM4 are differential input pairs; in actual use, when the NMOS transistor NM8, the NMOS transistor NM9, the NMOS transistor NM10, the NMOS transistor NM11, and the NMOS transistor NM12 are turned on, the output voltage of the third amplifying unit 3 is input to the capacitor C1, the capacitor C2, the capacitor, and the capacitor C4 for latching, and at this time, the input of the second amplifying unit 2 is the output of the third amplifying unit 3.
In the present embodiment, the circuits of the third amplifying unit 3 and the fourth amplifying unit 4 are as shown in fig. 5, in which:
the third amplifying unit 3 comprises a PMOS tube PM5, a PMOS tube PM6, a resistor R5 and a resistor R6; the source electrode of the PMOS tube PM5 is electrically connected with the source electrode of the PMOS tube PM6 and is used for inputting a third bias current, the grid electrode of the PMOS tube PM5 and the grid electrode of the PMOS tube PM6 are two input ends of the third amplifying unit 3, the grid electrode of the PMOS tube PM5 is electrically connected with the drain electrode of the PMOS tube PM4, the grid electrode of the PMOS tube PM6 is electrically connected with the drain electrode of the PMOS tube PM3, the drain electrode of the PMOS tube PM5 and the drain electrode of the PMOS tube PM6 are two output ends of the third amplifying unit 3, and are grounded through a resistor R5 and a resistor R6 respectively, and the drain electrode of the PMOS tube PM5 and the drain electrode of the PMOS tube PM6 are electrically connected with the two second switch branches 8;
the fourth amplifying unit 4 comprises a PMOS tube PM7, a PMOS tube PM8, an NMOS tube NM13, an NMOS tube NM14, an NMOS tube NM15 and an NMOS tube NM16; the source electrode of the PMOS tube PM7 is electrically connected with the source electrode of the PMOS tube PM8 and is used for inputting a fourth bias current, the grid electrode of the PMOS tube PM7 and the grid electrode of the PMOS tube PM8 are two input ends of a fourth amplifying unit, the grid electrode of the PMOS tube PM7 is electrically connected with the drain electrode of the PMOS tube PM5, the grid electrode of the PMOS tube PM8 is electrically connected with the drain electrode of the PMOS tube PM6, the drain electrode of the PMOS tube PM7 is respectively electrically connected with the drain electrode of the NMOS tube NM13, the grid electrode of the NMOS tube NM13 and the grid electrode of the NMOS tube NM14, the source electrode of the NMOS tube NM13 and the grid electrode of the NMOS tube NM15 are respectively electrically connected with the drain electrode of the NMOS tube NM14, the source electrode of the NMOS tube NM16 and the grid electrode of the NMOS tube NM15 are respectively grounded, the drain electrode of the NMOS tube NM15 is an output end of the fourth amplifying unit 4 and is used for inputting a fifth bias current, and the grid electrode of the NMOS tube NM16 is used for inputting a reset signal;
in addition, the output end of the fourth amplifying unit 4 in fig. 4 is also electrically connected with a schmitt trigger SMIT; in actual use, the output of the fourth amplifying unit 4 can be prevented from vibrating during the turnover through the schmitt trigger SMIT, and the turnover of the output of the invention can be quickened.
For the circuit shown in fig. 5, the PMOS transistors PM5 and PM6 are differential input pairs, and the resistors R5 and R6 are resistive loads of the differential pairs, providing voltage gain;
in addition, the fourth amplifying unit 4 is a two-stage amplifying unit, the PMOS tube PM7 and the PMOS tube PM8 are differential input pairs of the first-stage amplifying unit, the NMOS tube NM15 is a common source amplifying circuit of the second stage, the NMOS tube NM16 is a reset pull-down tube, when the reset signal RST is at a high level, the NMOS tube NM16 is turned on, the gate of the NMOS tube NM15 is pulled down to the ground, and the output of the fourth amplifying unit 4 is set high.
In addition, in this embodiment, the present invention further includes a current mirror as shown in fig. 7, where the current mirror includes a PMOS tube PM9, a PMOS tube PM10, a PMOS tube PM11, a PMOS tube PM12, a PMOS tube PM13, and a PMOS tube PM14; the source electrode of the PMOS tube PM9 is respectively and electrically connected with the source electrode of the PMOS tube PM10, the source electrode of the PMOS tube PM11, the source electrode of the PMOS tube PM12, the source electrode of the PMOS tube PM13 and the source electrode of the PMOS tube PM14 for accessing the power supply VDD; the grid electrode of the PMOS tube PM9 is electrically connected with the drain electrode of the PMOS tube PM9, the grid electrode of the PMOS tube PM10, the grid electrode of the PMOS tube PM11, the grid electrode of the PMOS tube PM12, the grid electrode of the PMOS tube PM13 and the grid electrode of the PMOS tube PM14 respectively and is used for inputting bias current IBP; the drain electrode of the PMOS transistor PM10 is electrically connected to the source electrode of the PMOS transistor PM1, the first bias current is input to the first amplifying unit, the drain electrode of the PMOS transistor PM11 is electrically connected to the source electrode of the PMOS transistor PM3, the second bias current is input to the second amplifying unit, the drain electrode of the PMOS transistor PM12 is electrically connected to the source electrode of the PMOS transistor PM5, the third bias current is input to the third amplifying unit, the drain electrode of the PMOS transistor PM13 is electrically connected to the source electrode of the PMOS transistor PM7, the fourth bias current is input to the fourth amplifying unit, the drain electrode of the PMOS transistor PM14 is electrically connected to the drain electrode of the NMOS transistor NM15, and the fifth bias current is input to the drain electrode of the NMOS transistor NM 15.
With reference to fig. 2, 4, 5, 6 and 7, the circuit of the present invention operates as follows:
at time t0, the grid electrode of the PMOS tube PM2 of the first amplifying unit 1 is connected with 0V, the grid electrode of the PMOS tube PM2 is connected with a reference voltage VREF, at this time, the input voltage of an input differential pair formed by the PMOS tube PM1 and the PMOS tube PM2 comprises the reference voltage VREF and an input offset voltage Vos, and at this time, the input differential mode voltage of the first amplifying unit 1 is Vos-VREF;
the output of the third amplification unit 3 is furthermore connected to the input of the second amplification unit 2 and returned to the input of the third amplification unit 3, and is also the output of the first amplification unit 1. According to the virtual short characteristic of the operational amplifier, the output of the second amplifying unit 2 is equal to the input of the third amplifying unit 3, that is, the output voltage of the first amplifying unit 1 is equal, and the first amplifying unit 1 is configured to output an equal state when the input voltage is Vos-VREF; at this time, it can be considered that the differential output of the first amplifying unit 1 is not output-dereferenced when the differential input thereof is Vos-VREF;
at time t2, the gate of the PMOS tube PM2 of the first amplifying unit 1 is connected to the comparison voltage VIN, the gate of the PMOS tube PM1 is connected to 0V, meanwhile, the two second switch branches are disconnected, when the voltages stored in the capacitor C2 and the capacitor C3 are in the previous t0 state, the output of the third amplifying unit 3 is output, so that the second amplifying unit 2 can configure the output of the first amplifying unit 1 to be the input differential voltage Vos-VREF in the normal comparison stage, when the actual comparison point of the first amplifying unit 1 is changed to vin+vos=vos-VREF, offset voltage Vos on the left side and the right side can be counteracted, the value of the comparison voltage VIN is-VREF, if the value of VREF is 5mV, the output turnover input voltage of the whole comparator is-5 mV, at this time, one comparison is completed, and meanwhile, the influence of input offset of the first amplifying unit 1 is eliminated, and the consistency of the comparator is greatly improved.
The present invention has been made in view of the above-described circumstances, and it is an object of the present invention to provide a portable electronic device capable of performing various changes and modifications without departing from the scope of the technical spirit of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.

Claims (10)

1. The voltage comparator for correcting offset voltage is characterized by comprising a first amplification unit with double input and double output, a second amplification unit with double input and double output, a third amplification unit with double input and double output and a fourth amplification unit with double input and single output;
the first input end of the first amplifying unit is electrically connected with the output end of the first control switch, and the second input end of the first amplifying unit is electrically connected with the output end of the second control switch;
at least one input end of the first amplifying unit is electrically connected with a switch branch circuit, and the switch branch circuit is used for inputting a comparison voltage and controlling whether the comparison voltage is input to the first amplifying unit or not based on an input control signal;
the two output ends of the first amplifying unit are respectively and electrically connected with the two output ends of the second amplifying unit and the two input ends of the third amplifying unit;
two output ends of the third amplifying unit are respectively and electrically connected with two input ends of the second amplifying unit through second switch branches, and at least one node except the nodes electrically connected with the third amplifying unit on each second switch branch is electrically connected with an energy storage unit; the two output ends of the third amplifying unit are electrically connected with the two input ends of the fourth amplifying unit, and the output end of the fourth amplifying unit is used for outputting a voltage comparison result.
2. The voltage comparator for correcting offset voltage according to claim 1, wherein the output terminal of the fourth amplifying unit is electrically connected to a schmitt trigger.
3. The voltage comparator for correcting offset voltage according to claim 1, wherein the control terminal of the first control switch, the control terminal of the second control switch and the two second switch branches simultaneously input a SET signal SET, and are turned on when the SET signal SET is at a high level and turned off when the SET signal SET is at a low level;
the switch branch is turned on when the control signal is in a high level, and turned off when the control signal is in a low level;
the SET signal SET and the control signal are periodic signals with the same frequency, the rising edge of the SET signal SET is the same as the falling edge of the control signal, and the high-level duty ratio of the SET signal SET is smaller than the low-level duty ratio of the control signal.
4. The voltage comparator for correcting offset voltage according to claim 3, wherein the first control switch and the second control switch are an NMOS transistor NM1 and an NMOS transistor NM8, respectively, a drain of the NMOS transistor NM1 is electrically connected to the first input terminal of the first amplifying unit, a drain of the NMOS transistor NM8 is electrically connected to the second input terminal of the first amplifying unit, and a gate of the NMOS transistor NM1 and a gate of the NMOS transistor NM8 are used for inputting the SET signal SET.
5. A voltage comparator for correcting offset voltage according to claim 3, wherein the second switching branch comprises two NMOS tubes connected in series, the drain electrode of the NMOS tube at the front end is electrically connected with the output end of the third amplifying unit, the source electrode of the NMOS tube at the rear end is electrically connected with the input end of the second amplifying unit, the source electrode of each NMOS tube is electrically connected with an energy storage unit, and the gates of the two NMOS tubes are used for inputting the SET signal SET.
6. The voltage comparator for correcting offset voltage according to claim 3, wherein the switching branch comprises an NMOS tube NM2, an NMOS tube NM3 and a resistor R1, the drain electrode of the NMOS tube NM2 is electrically connected to the input end of the first amplifying unit, the gate electrode of the NMOS tube NM2 is electrically connected to the gate electrode of the NMOS tube NM3, the source electrode of the NMOS tube NM2 is electrically connected to the drain electrode of the NMOS tube NM3, and the source electrode of the NMOS tube NM3 is electrically connected to one end of the resistor R1.
7. The voltage comparator for correcting offset voltage according to claim 6, wherein the drain of the NMOS transistor NM3 is electrically connected to the drain of the NMOS transistor NM4, the source of the NMOS transistor NM4 is grounded, the gate of the NMOS transistor NM4 is used for inputting a reset signal RST, and the reset signal RST is opposite to the control signal.
8. The voltage comparator for correcting offset voltage according to any one of claims 1 to 7, wherein the first amplifying unit comprises a PMOS tube PM1, a PMOS tube PM2, a resistor R2 and a resistor R3; the source electrode of the PMOS tube PM1 is electrically connected with the source electrode of the PMOS tube PM2 and is used for inputting a first bias current, the grid electrode of the PMOS tube PM1 and the grid electrode of the PMOS tube PM2 are two input ends of the first amplifying unit, and the drain electrode of the PMOS tube PM1 and the drain electrode of the PMOS tube PM2 are two output ends of the first amplifying unit and are grounded through a resistor R2 and a resistor R3 respectively;
the second amplifying unit comprises a PMOS tube PM3 and a PMOS tube PM4; the source electrode of the PMOS tube PM3 is electrically connected with the source electrode of the PMOS tube PM4 and is used for inputting a second bias current, the grid electrode of the PMOS tube PM3 and the grid electrode of the PMOS tube PM4 are two input ends of the second amplifying unit, the drain electrode of the PMOS tube PM3 and the drain electrode of the PMOS tube PM4 are two output ends of the second amplifying unit, the drain electrode of the PMOS tube PM3 is electrically connected with the drain electrode of the PMOS tube PM1, and the drain electrode of the PMOS tube PM4 is electrically connected with the drain electrode of the PMOS tube PM 2;
the third amplifying unit comprises a PMOS tube PM5, a PMOS tube PM6, a resistor R5 and a resistor R6; the source electrode of the PMOS tube PM5 is electrically connected with the source electrode of the PMOS tube PM6 and is used for inputting a third bias current, the grid electrode of the PMOS tube PM5 and the grid electrode of the PMOS tube PM6 are two input ends of a third amplifying unit, the grid electrode of the PMOS tube PM5 is electrically connected with the drain electrode of the PMOS tube PM4, the grid electrode of the PMOS tube PM6 is electrically connected with the drain electrode of the PMOS tube PM3, the drain electrode of the PMOS tube PM5 and the drain electrode of the PMOS tube PM6 are two output ends of the third amplifying unit, and the drain electrode of the PMOS tube PM5 and the drain electrode of the PMOS tube PM6 are respectively grounded through a resistor R5 and a resistor R6 and are electrically connected with two second switch branches;
the fourth amplifying unit comprises a PMOS tube PM7, a PMOS tube PM8, an NMOS tube NM13, an NMOS tube NM14, an NMOS tube NM15 and an NMOS tube NM16; the source electrode of the PMOS tube PM7 is electrically connected to the source electrode of the PMOS tube PM8, for inputting a fourth bias current, the gate electrode of the PMOS tube PM7 and the gate electrode of the PMOS tube PM8 are two input ends of the fourth amplifying unit, the gate electrode of the PMOS tube PM7 is electrically connected to the drain electrode of the PMOS tube PM5, the gate electrode of the PMOS tube PM8 is electrically connected to the drain electrode of the PMOS tube PM6, the drain electrode of the PMOS tube PM7 is electrically connected to the drain electrode of the NMOS tube NM13, the gate electrode of the NMOS tube NM13 and the gate electrode of the NMOS tube NM14, the source electrode of the NMOS tube NM13 and the gate electrode of the NMOS tube NM15 are electrically connected to the drain electrode of the NMOS tube NM14, the source electrode of the NMOS tube NM15 and the source electrode of the NMOS tube NM16 are electrically connected to each other, the drain electrode of the NMOS tube NM15 is an output end of the fourth amplifying unit, for inputting a fifth bias current, and the gate electrode of the NMOS tube NM16 is used for inputting a reset signal RST.
9. The voltage comparator for correcting offset voltage according to claim 8, further comprising a current mirror, wherein the current mirror comprises a PMOS tube PM9, a PMOS tube PM10, a PMOS tube PM11, a PMOS tube PM12, a PMOS tube PM13, and a PMOS tube PM14; the source electrode of the PMOS tube PM9 is respectively and electrically connected with the source electrode of the PMOS tube PM10, the source electrode of the PMOS tube PM11, the source electrode of the PMOS tube PM12, the source electrode of the PMOS tube PM13 and the source electrode of the PMOS tube PM14 for accessing a power supply; the grid electrode of the PMOS tube PM9 is electrically connected with the drain electrode of the PMOS tube PM9, the grid electrode of the PMOS tube PM10, the grid electrode of the PMOS tube PM11, the grid electrode of the PMOS tube PM12, the grid electrode of the PMOS tube PM13 and the grid electrode of the PMOS tube PM14 respectively and is used for inputting bias current IBP; the drain electrode of the PMOS transistor PM10 is electrically connected to the source electrode of the PMOS transistor PM1, the first bias current is input to the first amplifying unit, the drain electrode of the PMOS transistor PM11 is electrically connected to the source electrode of the PMOS transistor PM3, the second bias current is input to the second amplifying unit, the drain electrode of the PMOS transistor PM12 is electrically connected to the source electrode of the PMOS transistor PM5, the third bias current is input to the third amplifying unit, the drain electrode of the PMOS transistor PM13 is electrically connected to the source electrode of the PMOS transistor PM7, the fourth bias current is input to the fourth amplifying unit, the drain electrode of the PMOS transistor PM14 is electrically connected to the drain electrode of the NMOS transistor NM15, and the fifth bias current is input to the drain electrode of the NMOS transistor NM 15.
10. The voltage comparator for correcting offset voltage according to claim 1, wherein two input terminals of the first switching unit are electrically connected to switching branches, respectively, one switching branch is used for inputting a comparison voltage, and whether the comparison voltage is inputted to an input terminal of the first amplifying unit electrically connected to the one switching branch is controlled based on an inputted control signal; the other switching branch controls whether to pull down a signal of an input terminal electrically connected with the first amplifying unit and the other switching branch based on the input control signal.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000031824A (en) * 1998-07-13 2000-01-28 Nec Corp Offset cancel comparator for a/d converter
US6507241B1 (en) * 2000-10-03 2003-01-14 International Business Machines Corporation Method and circuit for automatically correcting offset voltage
US20110074505A1 (en) * 2009-09-29 2011-03-31 Yu-Chen Chiang Offset Voltage Calibration Method and Apparatus and Amplifier Thereof
CN103036512A (en) * 2012-12-17 2013-04-10 清华大学深圳研究生院 Dynamic comparator with large offset voltage correction range
US20160164467A1 (en) * 2014-12-05 2016-06-09 Fuji Electric Co., Ltd. Amplifying device and offset voltage correction method
CN206585537U (en) * 2016-12-29 2017-10-24 北京时代民芯科技有限公司 A kind of integrated disappearance is adjusted, jamproof comparator circuit
CN112187214A (en) * 2020-10-09 2021-01-05 上海安路信息科技有限公司 IO impedance calibration circuit and method of FPGA
CN116846391A (en) * 2023-07-18 2023-10-03 福州大学 Low-offset low-power consumption dynamic comparator based on double calibration

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000031824A (en) * 1998-07-13 2000-01-28 Nec Corp Offset cancel comparator for a/d converter
US6507241B1 (en) * 2000-10-03 2003-01-14 International Business Machines Corporation Method and circuit for automatically correcting offset voltage
US20110074505A1 (en) * 2009-09-29 2011-03-31 Yu-Chen Chiang Offset Voltage Calibration Method and Apparatus and Amplifier Thereof
CN103036512A (en) * 2012-12-17 2013-04-10 清华大学深圳研究生院 Dynamic comparator with large offset voltage correction range
US20160164467A1 (en) * 2014-12-05 2016-06-09 Fuji Electric Co., Ltd. Amplifying device and offset voltage correction method
CN206585537U (en) * 2016-12-29 2017-10-24 北京时代民芯科技有限公司 A kind of integrated disappearance is adjusted, jamproof comparator circuit
CN112187214A (en) * 2020-10-09 2021-01-05 上海安路信息科技有限公司 IO impedance calibration circuit and method of FPGA
CN116846391A (en) * 2023-07-18 2023-10-03 福州大学 Low-offset low-power consumption dynamic comparator based on double calibration

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