CN111049518A - Digital delay phase-locked loop and locking method thereof - Google Patents
Digital delay phase-locked loop and locking method thereof Download PDFInfo
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/1803—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the counter or frequency divider being connected to a cycle or pulse swallowing circuit
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
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Abstract
The invention discloses a digital delay phase-locked loop and a locking method thereof, wherein the digital delay phase-locked loop comprises: the device comprises a ring oscillation module, a frequency division module, a clock synchronization module, a delay chain code generation module and a delay chain unit, wherein the ring oscillation module is used for generating a counting clock; the frequency division module is used for respectively carrying out frequency division processing on the input reference clock and the input counting clock and outputting a frequency division counting clock and a frequency division reference clock; the clock synchronization module is used for performing clock synchronization processing on the frequency division counting clock and the frequency division reference clock and outputting a synchronous counting clock and a synchronous reference clock; the delay chain code generating module is used for generating a delay chain control signal; the delay chain unit is used for generating an output clock signal with a predetermined phase difference with the reference clock according to the delay chain control signal. The digital delay-locked loop can rapidly improve the resolution of the phase difference by increasing the bit width of the control delay chain code so as to meet the requirement of higher level.
Description
Technical Field
The invention belongs to the technical field of delay-locked loops, and particularly relates to a digital delay-locked loop and a locking method thereof.
Background
As the amount of data transmission increases, the requirement for a synchronous clock frequency increases. In order to transmit more data at a lower clock frequency, the data acquisition is designed to be carried out by using double edges (rising edge and falling edge) of a clock, and the data can be transmitted twice more at the same clock frequency than by using a single edge (rising edge or falling edge) mode. At the receiving data end, in order to accurately recover the data, the clock needs to be accurately delayed by a certain amount of time (for example, 1/4 cycles), and the duty ratio of the clock is basically unchanged.
The DDR (double data rate synchronous dynamic random access memory) chip is supported in an FPGA chip, a DDR protocol needs a clock which is 90 degrees different from a reference clock, and a Delay Locked Loop (DLL) circuit is usually used for generating the clock which is 90 degrees different from the reference clock in phase for DDR application. Fig. 1 shows a structure of a typical delay-locked loop, which includes a phase detector, a charge pump, a loop filter, a Bias Generator (Bias Generator), and a Voltage Controlled Delay Line (VCDL). The phase discriminator judges the phases of the source clock signal SCLK and the delayed clock signal FCLK, outputs corresponding control signals UP and DN to the charge pump, and converts the control signals UP and DN into current through the charge pump. The charge pump charges or discharges the loop filter under the control of the control signals UP and DN to obtain a control voltage Vctr of the voltage-controlled delay line, and bias voltages VBP and VBN generated by the bias generator are input to the voltage-controlled delay line. The bias voltage VBP and VBN generated by the bias generator controls the voltage-controlled delay line to generate time delay, so that the duty ratio of the clock is basically unchanged.
Due to the adoption of a closed loop structure, the delay-locked loop has the problem of loop stability and is relatively complex in design. Although the clock can be accurately positioned, the number of the voltage-controlled delay line delay units is frequently adjusted because the shift register is always dynamically adjusted, so that a large and complex state machine is required, and a large amount of noise is brought.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a digital delay locked loop and a locking method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
one aspect of the present invention provides a digital delay locked loop including a ring oscillation module, a frequency division module, a clock synchronization module, a delay chain code generation module, and a delay chain unit, wherein,
the ring oscillation module is used for generating a counting clock;
the frequency division module is connected with the annular oscillation module, inputs a reference clock, is used for respectively carrying out frequency division processing on the reference clock and the counting clock and outputting a frequency division counting clock and a frequency division reference clock;
the clock synchronization module is connected with the frequency division module and is used for performing clock synchronization processing on the frequency division counting clock and the frequency division reference clock and outputting a synchronous counting clock and a synchronous reference clock;
the delay chain code generation module is connected with the clock synchronization module and used for counting the synchronous reference clock through the synchronous counting clock and generating a delay chain control signal according to a counting value;
the delay chain unit is connected with the delay chain code generation module and used for generating an output clock signal with a preset phase difference with the reference clock according to the delay chain control signal.
In one embodiment of the invention, the frequency dividing module comprises a first frequency divider and a second frequency divider, wherein the first frequency divider is used for performing 2 on the reference clockn1Performing secondary frequency division processing, and outputting the frequency division counting clock; the input end of the second frequency divider is connected with the output end of the ring oscillation module and is used for carrying out 2 on the counting clockn2A sub-division process of outputting the divisionCount clocks, and n1>>n2。
In one embodiment of the present invention, the delay chain code generation block includes a counting unit, an approximate filtering code generation unit, a code generation unit, and a control signal generation unit, wherein,
the counting unit is connected with the clock synchronization module and is used for counting the synchronous reference clock by using the synchronous counting clock when the synchronous reference clock is at a high level so as to obtain the binary period number of the synchronous reference clock relative to the synchronous counting clock;
the approximate filtering code generating unit is connected with the counting unit and is used for receiving part of bit width of the binary cycle number for processing and generating a binary carry signal;
the code generation unit is connected with the counting unit and the approximate filtering code generation unit and used for generating a binary delay chain code according to the binary period number and the binary carry signal;
the control signal generating unit is connected with the code generating unit and the delay chain unit and used for generating a delay chain control signal according to the binary delay chain code.
In an embodiment of the present invention, the digital delay locked loop further includes a state machine module, respectively connected to the counting unit, the approximate filter code generating unit and the code generating unit, the state machine module is configured to control the approximate filter code generating unit to generate a carry signal after the counting unit counts, and is configured to generate an update signal according to the binary cycle number and the binary carry signal, so as to control the code generating unit to generate and update the binary delay chain code.
In an embodiment of the present invention, the digital delay-locked loop further includes a fine tuning module, connected to the code generation unit, for generating a phase fine tuning signal according to a user setting to adjust the precision of the generated binary delay chain code.
Another aspect of the present invention provides a method for locking a digital delay locked loop, including:
generating a count clock using a ring oscillator;
respectively carrying out frequency division processing on an input reference clock and the counting clock, and outputting a frequency division counting clock and a frequency division reference clock, wherein the period of the frequency division counting clock is far smaller than that of the frequency division reference clock;
performing clock synchronization processing on the frequency division counting clock and the frequency division reference clock, and outputting a synchronous counting clock and a synchronous reference clock;
counting the synchronous reference clock through the synchronous counting clock, and generating a delay chain control signal according to a counting value;
an output clock signal having a predetermined phase difference from the reference clock is generated according to the delay chain control signal.
In one embodiment of the present invention, frequency-dividing an input reference clock and the count clock, respectively, outputting a frequency-divided count clock and a frequency-divided reference clock, and a cycle of the frequency-divided count clock being much smaller than a cycle of the frequency-divided reference clock, includes:
go on 2 to the reference clockn1Secondary frequency division processing, outputting a frequency division counting clock;
carry out 2 to the counting clocks respectivelyn2A sub-division process of outputting a division count clock of n1>>n2 such that the period of the divided count clock is much smaller than the period of the divided reference clock.
In one embodiment of the present invention, counting the synchronous reference clock by the synchronous count clock and generating a delay chain control signal according to the count value, includes:
counting the synchronous reference clock by using the synchronous counting clock when the synchronous reference clock is at a high level to obtain a binary period number of the synchronous reference clock relative to the synchronous counting clock;
intercepting part of bit width of the binary cycle number for processing to generate a binary carry signal;
the delay circuit is used for generating a binary delay chain code according to the binary cycle number and the binary carry signal;
and generating a delay chain control signal according to the binary delay chain code.
In an embodiment of the present invention, intercepting a part of bit widths of the binary cycle number for processing, and generating a binary carry signal includes:
intercepting part of bit width data of the synchronous counting clock period number;
judging the size of the part of bit width data and a preset threshold;
according to the judgment result, when the part of bit width data is greater than the preset threshold, the generated carry signal is 1, and when the part of bit width data is not greater than the preset threshold, the generated carry signal is 0.
In one embodiment of the present invention, the apparatus for generating a binary delay chain code according to the binary cycle number and the binary carry signal comprises:
and adding the binary cycle number and the binary carry signal to form a binary delay chain code.
Compared with the prior art, the invention has the beneficial effects that:
1. the digital delay phase-locked loop and the locking method thereof adopt an open-loop structure, have no problem of loop stability, can quickly improve the resolution of the phase difference by increasing the bit width of the control delay chain code so as to meet the requirement of higher level, and have simple structure.
2. Compared with the traditional 90 DEG delay-locked loop circuit, the digital delay-locked loop of the invention can provide a variable phase function, and the variable phase is set by a fine phase adjustment register fine _ tune.
3. The digital delay phase-locked loop of the invention needs the ratio of the number of the clock cycles, so the delay value of the inverter does not need to be made very accurate, and the influence of the deviation of the manufacturing process on the precision of the product in large-scale mass production is effectively eliminated.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a typical delay locked loop of the prior art;
FIG. 2 is a block diagram of a digital delay locked loop according to an embodiment of the present invention;
fig. 3 is a specific structural diagram of a digital delay-locked loop according to an embodiment of the present invention;
fig. 4 is a flowchart of a locking method of a digital delay-locked loop according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a generation principle of a binary delay chain code according to an embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, a digital delay locked loop and a locking method thereof according to the present invention are described in detail below with reference to the accompanying drawings and the detailed description.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element.
Example one
Referring to fig. 2, fig. 2 is a block diagram of a digital delay-locked loop according to an embodiment of the present invention. The digital delay-locked loop of the embodiment includes a ring oscillation module 101, a frequency division module 102, a clock synchronization module 103, a delay chain code generation module 104, and a delay chain unit 105, where the ring oscillation module 101 is configured to generate a count clock; the frequency dividing module 102 is connected to the ring oscillation module 101, inputs a reference clock, and is configured to perform frequency dividing processing on the reference clock and the count clock, and output a frequency-divided count clock and a frequency-divided reference clock; the clock synchronization module 103 is connected to the frequency division module 102, and is configured to perform clock synchronization processing on the frequency division counting clock and the frequency division reference clock, and output a synchronous counting clock and a synchronous reference clock; the delay chain code generation module 104 is connected to the clock synchronization module 103, and is configured to count the synchronous reference clock by using the synchronous count clock, and generate a delay chain control signal according to the count value; the delay chain unit 105 is connected to the delay chain code generation block 104 for generating an output clock signal having a predetermined phase difference from the reference clock according to the delay chain control signal.
The digital delay latch of the embodiment uses an open loop structure, does not need an analog phase discriminator circuit, can realize that the phase difference between an output clock and an input clock is 90 degrees, can be accurate to 14 degrees of step length, and can improve the resolution of the delay latch by increasing the bit width of a control code, thereby meeting the requirement of higher precision phase difference.
The ring oscillation module 101 of the present embodiment includes a plurality of inverters connected end to end, and the delay chain unit 105 includes a plurality of inverters connected in sequence. In the present embodiment, the number of inverters in the ring oscillation module 101 is larger than the number of inverters in the delay chain unit 105. It should be noted that the specific principle of generating the clock signal by the ring oscillation module and the operation principle of generating the clock signal with the specified phase difference by the delay chain unit are well known in the art and will not be described in detail herein.
Further, referring to fig. 3, fig. 3 is a specific structural diagram of a digital delay-locked loop according to an embodiment of the present invention. The frequency division module 102 comprises a first frequency divider 1021 and a second frequency divider 1022, wherein the first frequency divider 1021 is used for performing 2 on the reference clockn1Secondary frequency division processing is carried out, and a frequency division counting clock is output; the input terminal of the second frequency divider 1022 is connected to the output terminal of the ring oscillator module 101, and is used for performing 2 operations on the counting clockn2A sub-division process of outputting a division count clock, and n1>>n2。
Further, the delay chain code generating module 104 includes a counting unit 1041, an approximate filtering code generating unit 1042, a code generating unit 1043, and a control signal generating unit 1044, where the counting unit 1041 is connected to the clock synchronization module 103, and is configured to count the synchronous reference clock by using the synchronous counting clock when the synchronous reference clock is at a high level to obtain a binary cycle number of the synchronous reference clock relative to the synchronous counting clock; the approximate filtering code generating unit 1042 is connected to the counting unit 1041, and is configured to receive a part of bit widths of the binary cycle number for processing, and generate a binary carry signal; the code generating unit 1043 is connected to the counting unit 1041 and the approximate filtering code generating unit 1042, and is configured to generate a binary delay chain code according to the binary cycle number and the binary carry signal; the control signal generating unit 1044 is connected to the code generating unit 1043 and the delay chain unit 105, and is configured to generate the delay chain control signal according to the binary delay chain code.
Further, the digital delay locked loop further includes a state machine module 106, which is respectively connected to the counting unit 1041, the approximate filtering code generating unit 1042 and the code generating unit 1043, where the state machine module 106 is configured to control the approximate filtering code generating unit 1042 to generate a carry signal after the counting unit 1041 finishes counting, and is configured to generate an update signal according to the binary cycle number and the binary carry signal, so as to control the code generating unit 1043 to generate and update the binary delay chain code.
Specifically, with continued reference to FIG. 3, during actual operation, the reference clock clk _ ref and the ring oscillationThe count clocks clk _ osc outputted from the module 101 are respectively subjected to frequency division processing by the frequency dividing circuit, and specifically, the reference clock clk _ ref is subjected to 2 in the first frequency divider 1021n1A second frequency division process to form a frequency-divided reference clock, and the count clock clk _ osc is performed by 2 in the second frequency divider 1022n2Sub-divided to form a divided count clock, where n1>>n2, such that the period of the divided count clock is much smaller than the period of the divided reference clock; subsequently, the two clock signals after the frequency division processing are subjected to clock synchronization processing, and a synchronous count clock ck _ osc and a synchronous reference clock ck _ ref are generated, wherein the synchronous count clock ck _ osc and the synchronous reference clock ck _ ref are clocks having the same edge, i.e., rising edges having the same time at the beginning. Frequency division number 2 due to reference clock clk _ refn1Frequency division number 2 much larger than count clock clk _ oscn2Therefore, the period of the obtained synchronous reference clock ck _ ref is far larger than that of the synchronous counting clock ck _ osc, and when the synchronous counting clock ck _ osc is used for counting every time the synchronous reference clock ck _ ref has a high level, the binary period number of the half period of ck _ ref relative to ck _ osc is obtained and is marked as counter [ n3: 0]](ii) a Next, the generated binary cycle number counter [ n3: 0%]Truncate bit width counter [ n4: 0]](n3>n4) to the approximate filter code generating unit 1042, the approximate filter code generating unit 1042 counts the truncated partial-bit-width data [ n4: 0]]Processing, namely judging the size of the part of bit width data and a preset threshold, and according to a judgment result, when the part of bit width data is greater than the preset threshold, generating a carry signal carry which is 1, and when the part of bit width data is not greater than the preset threshold, generating a carry signal carry which is 0; the value of the carry signal carry is then compared with the binary cycle count [ n3: 0] generated in the counting unit]The result is processed in a code generation unit to generate a binary delay chain code counter [ n5: 0]]Then, as a final delay chain code, a delay chain control signal is generated based on the delay chain code to control the number of inverters connected in series in the delay circuit to generate an output clock signal having a predetermined phase difference from the reference clock.
Further, in order to ensure that the count value during the counting process does not affect the number of inverters included in the delay chain unit 105, the state machine module 106 controls the approximate filtering code generation unit 1042 to generate a carry signal after the counting unit 1041 finishes counting, and is configured to generate an update signal according to the binary cycle number and the carry signal, so as to control the code generation unit 1043 to generate and update the binary delay chain code, so as to change the number of inverters added into the delay chain, and finally generate a desired phase difference.
In addition, the digital delay-locked loop further includes a fine tuning module (not shown in the drawings) connected to the code generation unit 1043 for generating a phase fine tuning signal according to a user setting to adjust the precision of the generated binary delay chain code. Preferably, the fine tuning module is a phase fine tuning register fine _ tune. In actual operation, the digital delay-locked loop of the present embodiment can provide a variable phase through the phase fine _ tune register, and the operation will be described in detail below.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a generation principle of a binary delay chain code according to an embodiment of the present invention. Assuming that the bit width of the binary cycle number generated in the calculation unit is 10, which is denoted as counter [10:0], and it is desired to obtain an output clock that differs from the reference clock by 90 °, the delay chain control signal can be finally generated by the calculation as shown in fig. 5. A higher precision can be achieved with a larger number of inverters making up the ring oscillator, since ultimately a ratio of the number of cycles is required, rather than a specific time, so there is no requirement for a specific value of the delay time of the individual inverters. The working condition of the circuit of the invention needs to cover a wider frequency range, and in order to adjust the two clocks after frequency division within the whole frequency range by 90 degrees, the selection of the frequency division number needs to be reasonable, and the counting result can not exceed the bit width of the counter. A reasonable set of design examples is presented below.
Specifically, the period of the count clock is: t isclk_osc＝28×t dly2, wherein, tdlyIs the delay time of one inverter in the ring oscillator module.The period of the synchronous reference clock is: t isck_ref＝215×Tclk_refThe period of the synchronous count clock is: t isck_osc＝24×Tclk_osc，
The binary cycle count [10:0] of ck _ ref half cycle relative to ck _ osc is:
counter[10:0]＝((Tclk_ref×215)/2)/(24×Tclk_osc)
＝((Tclk_ref*215)/2)/(24×29*tdly)
＝2×Tclk_ref/tdly(1)
then, the two sides of formula (1) are simultaneously divided by 8 to obtain:
counter[10:0]/8＝(1/4)×Tclk_ref/tdly(2)
in this embodiment, the period T of the reference clock is setclk_refCorresponding to 360 deg., then (1/4) × Tclk_refCorresponding to 90 deg., then (1/4) × Tclk_ref/tdlyThe corresponding count value (cycle number) is the count value corresponding to 90 °. Further, when a step size is required in which the phase difference is accurate to 11 °, the fine adjustment module generates a fine phase adjustment signal fine _ tune [2:0] according to the setting]. Since counter [10:0]]/8＝(1/4)×Tclk_ref/tdlyIs a code value corresponding to 90 deg., that if 90 deg./8 is 11 deg., then dividing equation (2) by 8 yields an expression of 11 deg.:
(counter[10:0]/8)/8 (3)
multiplying equation (3) by the phase fine adjustment signal fine _ tune [2:0] yields an increase or decrease of an integer multiple of 11 °, where the increase or decrease depends on the positive or negative of fine _ tune [2:0 ]:
((counter[10:0]/8)/8)*fine_tune[2:0](4)
next, formula (5) obtained by adding formulas (2) and (4) to the carry signal carry is an expression of a binary delay chain code including a step phase difference of 11 ° around 90 °:
(counter[10:0]+fine_tune[2:0]*counter[10:0]/8)/8+carry(5)
generating a delay chain control signal according to the delay chain code to control the number of inverters connected in series in the delay circuit to generate an output clock signal having a predetermined phase difference from the reference clock
It should be noted that when the fine _ tune [2:0] is 0, the phase difference between the output clock of the digital delay-locked loop and the reference clock is 90 °, and when the fine _ tune [2:0] is not zero, the phase difference between the output clock of the digital delay-locked loop and the reference clock is 90 ° +/-11 × fine _ tune [2:0 ].
The digital delay phase-locked loop of this embodiment adopts the open loop structure, does not have the problem of loop stability, can promote the resolution ratio of phase difference fast through increasing the bit width of control delay chain code to satisfy the demand of higher level, simple structure. Compared with the traditional 90 DEG delay-locked loop circuit, the digital delay-locked loop of the invention can provide a variable phase function, and the variable phase is set by a fine phase adjustment register fine _ tune. In addition, the scheme of the digital delay-locked loop needs the ratio of the number of the clock cycles, so that the delay value of the inverter does not need to be very accurate, and the influence of the deviation of the manufacturing process on the accuracy of the product in large-scale mass production is effectively eliminated.
Example two
On the basis of the above embodiments, the present embodiment provides a locking method for a digital delay locked loop. Referring to fig. 4, fig. 4 is a flowchart illustrating a locking method of a digital delay-locked loop according to an embodiment of the present invention. The locking method comprises the following steps:
s1: generating a count clock using a ring oscillator;
the ring oscillation module 101 of the present embodiment includes a plurality of inverters connected end to end.
S2: respectively carrying out frequency division processing on the input reference clock and the counting clock, and outputting a frequency division counting clock and a frequency division reference clock;
specifically, the S2 includes:
go on 2 to the reference clockn1Secondary frequency division processing, outputting a frequency division counting clock; carry out 2 to the counting clocks respectivelyn2A sub-division process of outputting a division count clock of n1>>n2。
With reference to fig. 2, the reference clock clk _ ref and the count clock clk _ osc outputted from the ring oscillator are divided by the frequency dividing circuit, specifically, the reference clock clk _ ref is divided by 2n1 times in the first frequency divider 1021 to form a divided reference clock, and the count clock clk _ osc is divided by 2n2 times in the second frequency divider 1022 to form a divided count clock, where n1> > n2 makes the period of the divided count clock much shorter than the period of the divided reference clock.
S3: performing clock synchronization processing on the frequency division counting clock and the frequency division reference clock, and outputting a synchronous counting clock and a synchronous reference clock;
specifically, the two clock signals after the frequency division processing are subjected to clock synchronization processing, and a synchronous count clock ck _ osc and a synchronous reference clock ck _ ref are generated, wherein the synchronous count clock ck _ osc and the synchronous reference clock ck _ ref are clocks with the same edge, that is, rising edges having the same time at the beginning.
S4: counting the synchronous reference clock through the synchronous counting clock, and generating a delay chain control signal according to a counting value;
further, the S4 includes:
s41: counting the synchronous reference clock by using the synchronous counting clock when the synchronous reference clock is at a high level to obtain a binary period number of the synchronous reference clock relative to the synchronous counting clock;
s42: intercepting part of bit width of the binary cycle number for processing to generate a binary carry signal;
intercepting part of bit width data of the synchronous counting clock period number; judging the size of the part of bit width data and a preset threshold; according to the judgment result, when the part of bit width data is greater than the preset threshold, the generated carry signal is 1, and when the part of bit width data is not greater than the preset threshold, the generated carry signal is 0.
S43: the delay circuit is used for generating a binary delay chain code according to the binary cycle number and the binary carry signal;
s44: and generating a delay chain control signal according to the binary delay chain code.
Specifically, the frequency division number 2 due to the reference clock clk _ refn1Frequency division number 2 much larger than count clock clk _ oscn2Therefore, the period of the obtained synchronous reference clock ck _ ref is far larger than that of the synchronous counting clock ck _ osc, and when the synchronous counting clock ck _ osc is used for counting every time the synchronous reference clock ck _ ref has a high level, the binary period number of the half period of ck _ ref relative to ck _ osc is obtained and is marked as counter [ n3: 0]](ii) a Next, the generated binary cycle number counter [ n3: 0%]Truncate bit width counter [ n4: 0]](n3>n4), namely, judging the size of the part of bit width data and a preset threshold, according to the judgment result, when the part of bit width data is greater than the preset threshold, generating a carry signal carry which is 1, and when the part of bit width data is not greater than the preset threshold, generating a carry signal carry which is 0; the value of the carry signal carry is then compared with the binary cycle count [ n3: 0] generated in the counting unit]The result is processed in a code generation unit to generate a binary delay chain code counter [ n5: 0]]As the final delay chain code.
S5: an output clock signal having a predetermined phase difference from the reference clock is generated according to the delay chain control signal.
And generating a delay chain control signal according to the delay chain code to control the number of inverters connected in series in the delay circuit so as to generate an output clock signal having a predetermined phase difference with the reference clock.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A digital delay-locked loop comprises a ring oscillation module (101), a frequency division module (102), a clock synchronization module (103), a delay chain code generation module (104), and a delay chain unit (105),
the ring oscillation module (101) is used for generating a counting clock;
the frequency dividing module (102) is connected with the annular oscillation module (101), inputs a reference clock, and is used for respectively performing frequency dividing processing on the reference clock and the counting clock and outputting a frequency dividing counting clock and a frequency dividing reference clock;
the clock synchronization module (103) is connected with the frequency division module (102) and is used for performing clock synchronization processing on the frequency division counting clock and the frequency division reference clock and outputting a synchronous counting clock and a synchronous reference clock;
the delay chain code generation module (104) is connected with the clock synchronization module (103) and is used for counting the synchronous reference clock through the synchronous counting clock and generating a delay chain control signal according to the counting value;
the delay chain unit (105) is connected to the delay chain code generation module (104) for generating an output clock signal having a predetermined phase difference from the reference clock according to the delay chain control signal.
2. The digital delay locked loop of claim 1, wherein the frequency-dividing module (102) comprises a first frequency divider (1021) and a second frequency divider (1022), wherein the first frequency divider (1021) is configured to perform a 2-divide on the reference clockn1Performing secondary frequency division processing, and outputting the frequency division counting clock; the input end of the second frequency divider (1022) is connected with the output end of the ring oscillation module (101) and is used for carrying out 2 on the counting clockn2A sub-division process of outputting the divided count clock, and n1>>n2。
3. The digital delay locked loop of claim 1, wherein the delay chain code generation block (104) comprises a counting unit (1041), an approximate filtering code generation unit (1042), a code generation unit (1043), and a control signal generation unit (1044), wherein,
the counting unit (1041) is connected to the clock synchronization module (103) and configured to count the synchronous reference clock by using the synchronous counting clock when the synchronous reference clock is at a high level to obtain a binary number of cycles of the synchronous reference clock relative to the synchronous counting clock;
the approximate filtering code generating unit (1042) is connected with the counting unit (1041) and is used for receiving and processing part of bit width of the binary cycle number to generate a binary carry signal;
the code generation unit (1043) is connected with the counting unit (1041) and the approximate filtering code generation unit (1042) and is used for generating a binary delay chain code according to the binary cycle number and the binary carry signal;
the control signal generating unit (1044) is connected to the code generating unit (1043) and the delay chain unit (105), and is configured to generate a delay chain control signal according to the binary delay chain code.
4. The digital delay locked loop according to claim 3, further comprising a state machine module (106) respectively connected to the counting unit (1041), the approximate filtering code generating unit (1042) and the code generating unit (1043), wherein the state machine module (106) is configured to control the approximate filtering code generating unit (1042) to generate a carry signal after the counting unit (1041) finishes counting, and configured to generate an update signal according to the binary cycle number and the binary carry signal to control the code generating unit (1043) to generate and update the binary delay chain code.
5. The digital delay locked loop according to any of claims 3 or 4, further comprising a fine tuning module connected to the code generation unit (1043) for generating a phase fine tuning signal according to a user setting for adjusting the accuracy of the produced binary delay chain code.
6. A method for locking a digital delay locked loop, comprising:
generating a count clock using a ring oscillator;
respectively carrying out frequency division processing on an input reference clock and the counting clock, and outputting a frequency division counting clock and a frequency division reference clock, wherein the period of the frequency division counting clock is far smaller than that of the frequency division reference clock;
performing clock synchronization processing on the frequency division counting clock and the frequency division reference clock, and outputting a synchronous counting clock and a synchronous reference clock;
counting the synchronous reference clock through the synchronous counting clock, and generating a delay chain control signal according to a counting value;
an output clock signal having a predetermined phase difference from the reference clock is generated according to the delay chain control signal.
7. The method of locking a digital delay locked loop according to claim 6, wherein the dividing process is performed on the input reference clock and the count clock, the divided count clock and the divided reference clock are output, and the period of the divided count clock is much smaller than the period of the divided reference clock, and the method comprises:
go on 2 to the reference clockn1Secondary frequency division processing, outputting a frequency division counting clock;
carry out 2 to the counting clocks respectivelyn2A sub-division process of outputting a division count clock of n1>>n2 such that the period of the divided count clock is much smaller than the period of the divided reference clock.
8. The method of locking a digital delay locked loop according to claim 6 or 7, wherein counting the synchronous reference clock by the synchronous count clock and generating the delay chain control signal according to the count value comprises:
counting the synchronous reference clock by using the synchronous counting clock when the synchronous reference clock is at a high level to obtain a binary period number of the synchronous reference clock relative to the synchronous counting clock;
intercepting part of bit width of the binary cycle number for processing to generate a binary carry signal;
the delay circuit is used for generating a binary delay chain code according to the binary cycle number and the binary carry signal;
and generating a delay chain control signal according to the binary delay chain code.
9. The method of claim 8, wherein intercepting a portion of the bit width of the binary cycle number for processing to generate a binary carry signal comprises:
intercepting part of bit width data of the synchronous counting clock period number;
judging the size of the part of bit width data and a preset threshold;
according to the judgment result, when the part of bit width data is greater than the preset threshold, the generated carry signal is 1, and when the part of bit width data is not greater than the preset threshold, the generated carry signal is 0.
10. The method of claim 8, wherein generating a binary delay chain code based on the number of binary cycles and the binary carry signal comprises:
and adding the binary cycle number and the binary carry signal to form a binary delay chain code.
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| CN113098499A (en) * | 2021-04-06 | 2021-07-09 | 中国科学院微电子研究所 | Delay phase-locked loop |
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| CN113098499A (en) * | 2021-04-06 | 2021-07-09 | 中国科学院微电子研究所 | Delay phase-locked loop |
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