CN109743058A - Phase frequency detection circuit, charge pump phase-frequency detector and phase-locked loop circuit - Google Patents
Phase frequency detection circuit, charge pump phase-frequency detector and phase-locked loop circuit Download PDFInfo
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Abstract
This application discloses a kind of phase frequency detection circuit, charge pump phase-frequency detector and phase-locked loop circuits, the phase frequency detection circuit includes: the first trigger, its input end of clock is for inputting the first clock signal, and signal output end is for exporting the first signal；Second trigger, input end of clock is for inputting second clock signal, and signal output end is for exporting second signal；Reset circuit, input terminal are respectively coupled to the signal output end of the first trigger and the signal output end of the second trigger；The insensitive delay circuit of PVT, input terminal couple the output end of reset circuit, and output end is respectively coupled to the RESET input of the first trigger and the RESET input of the second trigger.By the above-mentioned means, the influence of technique, voltage, temperature can be reduced, delay time variation caused by PVT changes can be reduced.
Description
Technical field
This application involves field of circuit technology, more particularly to a kind of phase frequency detection circuit, charge pump phase frequency
Detector and phase-locked loop circuit.
Background technique
Circuit of the PFD (phase-frequency detector) as the phase difference between the original CLC (phase) of detection and recovery CLC,
Central role is played in phase locking circuit (PLL/DLL).PFD is because that can detect display interface (display interface)
Data (data) phase and recovery phase difference of receiving part input, restore BUR to detection data and play a key effect.
But the strong influence that the performance of existing PFD is changed by technique, supply voltage and temperature (PVT), so that inspection
Survey the performance decline of device.
Summary of the invention
The application mainly provides a kind of phase frequency detection circuit, charge pump phase-frequency detector and phase-locked loop circuit,
The influence of technique, supply voltage and temperature (PVT) to PFD can be reduced.
A kind of technical solution that the application uses is to provide a kind of phase and frequency detection circuit, which includes:
First trigger, input end of clock is for inputting the first clock signal, and signal output end is for exporting the first signal；Second
Trigger, input end of clock is for inputting second clock signal, and signal output end is for exporting second signal；Reset electricity
Road, input terminal are respectively coupled to the signal output end of the first trigger and the signal output end of the second trigger；PVT is insensitive to be prolonged
Slow circuit, input terminal couple reset circuit output end, output end be respectively coupled to the first trigger the RESET input and
The RESET input of second trigger.
Wherein, the insensitive delay circuit of PVT includes: the negater circuit group comprising at least one negater circuit, input terminal
The output end of reset circuit is coupled, output end couples the reset input of the RESET input and the second trigger of the first trigger
End.
Wherein, negater circuit group includes multiple negater circuits sequentially coupled；The input of first negater circuit therein
The output end of end coupling reset circuit, output end couple the input terminal of next negater circuit；The last one reversed electricity therein
The input terminal on road couples the output end of a upper negater circuit, and output end couples the RESET input and the second touching of the first trigger
Send out the RESET input of device.
Wherein, negater circuit includes: not circuit, input terminal of the input terminal as negater circuit；Resistance, one end coupling
Connect the output end of not circuit, output end of the other end as negater circuit；Capacitor, the other end of one end coupling resistance,
Its other end ground connection.
Wherein, phase and frequency detection circuit further includes multiplexer；Multiple input terminals of multiplexer are respectively coupled to multiple anti-
To the output end of circuit, output end couples the RESET input of the first trigger and the RESET input of the second trigger.
Wherein, the insensitive delay circuit of PVT includes: the first negater circuit, and input terminal couples the output end of reset circuit；
Negater circuit group comprising at least one RC retardation ratio circuit, input terminal couple the first negater circuit；Second negater circuit, it is defeated
Enter the output end of end coupling negater circuit group, output end couples the RESET input of the first trigger and answering for the second trigger
Position input terminal.
Wherein, the insensitive delay circuit of PVT includes multiple RC retardation ratio circuits sequentially coupled；First RC retardation ratio therein
The output end of the input terminal coupling reset circuit of circuit, output end couple the input terminal of next negater circuit；It is therein last
The input terminal of one RC retardation ratio circuit couples the output end of upper RC retardation ratio circuit, and output end couples the reset of the first trigger
The RESET input of input terminal and the second trigger.
Wherein, reset circuit includes: NAND gate circuit, and first input end couples the signal output end of the first trigger,
Its second input terminal couples the signal output end of the second trigger.
The another technical solution that the application uses is to provide a kind of charge pump phase and frequency detector, the detector packet
Include: the first trigger, input end of clock is for inputting the first clock signal, and signal output end is for exporting the first signal；
Second trigger, input end of clock is for inputting second clock signal, and signal output end is for exporting second signal；Charge
Pump, first input end couple the signal output end of the first trigger, and the signal that the second input terminal couples the second trigger is defeated
Outlet, output end are used for output signal；Reset circuit, input terminal are respectively coupled to the signal output end and of the first trigger
The signal output end of two triggers；The insensitive delay circuit of PVT, input terminal couple the output end of reset circuit, output end
It is respectively coupled to the RESET input of the first trigger and the RESET input of the second trigger.
The another technical solution that the application uses is to provide a kind of phase-locked loop circuit, which includes: charge
Pump phase and frequency detector；Wherein, charge pump phase and frequency detector is that above-mentioned charge pump phase and frequency such as detects
Device；Loop filter, input terminal couple the output end of charge pump in charge pump phase and frequency detector；Voltage controlled oscillator,
Its input terminal couples the output end of loop filter, and output end is used for output signal；Frequency divider, input terminal couple voltage-controlled vibration
The output end of device is swung, output end couples the input end of clock of the second trigger in charge pump phase and frequency detector.
Phase and frequency detection circuit provided by the present application includes: the first trigger, and input end of clock is for inputting the
One clock signal, signal output end is for exporting the first signal；Second trigger, when input end of clock is for inputting second
Clock signal, signal output end is for exporting second signal；Reset circuit, input terminal are respectively coupled to the signal of the first trigger
The signal output end of output end and the second trigger；The insensitive delay circuit of PVT, input terminal couple the output of reset circuit
End, output end are respectively coupled to the RESET input of the first trigger and the RESET input of the second trigger.Pass through above-mentioned side
Formula can reduce the influence of technique, voltage, temperature using the insensitive delay circuit of PVT, can reduce delay caused by PVT variation
Time change.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the drawings in the following description are only some examples of the present application, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.Wherein:
Fig. 1 is the circuit diagram of phase and frequency detection circuit first embodiment provided by the present application；
Fig. 2 is the time diagram of Fig. 1；
Fig. 3 is the circuit diagram of phase and frequency detection circuit second embodiment provided by the present application；
Fig. 4 is the first circuit diagram of the insensitive delay circuit of PVT in Fig. 3；
Fig. 5 is the second circuit schematic diagram of the insensitive delay circuit of PVT in Fig. 3；
Fig. 6 is the tertiary circuit schematic diagram of the insensitive delay circuit of PVT in Fig. 3；
Fig. 7 is the structural schematic diagram of one embodiment of charge pump phase and frequency detector provided by the present application；
Fig. 8 is the structural schematic diagram of one embodiment of phase-locked loop circuit provided by the present application.
Specific embodiment
Referenced herein " embodiment " is it is meant that a particular feature, structure, or characteristic described can wrap in conjunction with the embodiments
It is contained at least one embodiment of the application.Each position in the description occur the phrase might not each mean it is identical
Embodiment, nor the independent or alternative embodiment with other embodiments mutual exclusion.Those skilled in the art explicitly and
Implicitly understand, embodiment described herein can be combined with other embodiments.
Refering to fig. 1, Fig. 1 is the circuit diagram of phase and frequency detection circuit first embodiment provided by the present application, should
Phase and frequency detection circuit 10 includes the first trigger 11, the second trigger 12, reset circuit 13 and delay circuit 14.
Wherein, the input end of clock of the first trigger 11 is for inputting the first clock signal CK_REF, signal output end
For exporting the first signal UP；The input end of clock of second trigger 12 is for inputting second clock signal CK_DLY, signal
Output end is for exporting second signal DN；The input terminal of reset circuit 13 be respectively coupled to the first trigger 11 signal output end and
The signal output end of second trigger 12；The output end of the input terminal coupling reset circuit 13 of delay circuit 14, output end point
The RESET input of the first trigger 11 and the RESET input of the second trigger 12 are not coupled.
Optionally, the first trigger 11 therein and the second trigger 12 are d type flip flop, and the truth table of d type flip flop is as follows:
| D | CLK | Q | QN |
| 0 | Rising edge clock | 0 | 1 |
| 1 | Rising edge clock | 1 | 0 |
| × | 0 | last Q | last QN |
| × | 1 | last Q | last QN |
Simultaneously referring to Fig.2, Fig. 2 is the time diagram of Fig. 1.
In the case where delay lags (late delay clock case), with CK_REF rising edge synch, UP signal becomes
It is 1, with CK_DLY rising edge synch, DN signal becomes 1.After UP signal and DN signal all become 1, by 13 He of reset circuit
The path of delay circuit 14 carries out logic delay, delay time tD, rst, UP signal and DN signal return to 0 after delay.?
After the pulse of the UP signal and DN signal that occur on PFD is accumulated because of subsequent charge pump (not shown), phase locking circuit is opened
It is dynamic, and keep UP signal identical with the impulse amplitude of DN signal under the action of feed circuit.
In the case where delay shifts to an earlier date (early delay clock case), with CK_DLY rising edge synch, DN signal
Become 1, with CK_REF rising edge synch, UP signal becomes 1.After UP signal and DN signal all become 1, by reset circuit 13
Logic delay, delay time t are carried out with the path of delay circuit 14D, rst, UP signal and DN signal return to 0 after delay.?
After the pulse of the UP signal and DN signal that occur on PFD is accumulated because of subsequent charge pump (not shown), phase locking circuit is opened
It is dynamic, and keep UP signal identical with the impulse amplitude of DN signal under the action of feed circuit.
PFD in above-described embodiment can correctly detect phase difference and to detect speed fast.But above-mentioned PFD
The shortcomings that having it.For example, the impulse amplitude of UP signal and DN signal is prolonged according to the path of reset circuit 13 and delay circuit 14
Depending on the slow time, when PVT variation is to when being affected of impulse amplitude of UP signal and DN signal, the influence to circuit compared with
Greatly.
It is the circuit diagram of phase and frequency detection circuit second embodiment provided by the present application refering to Fig. 3, Fig. 3, it should
Phase and frequency detection circuit 20 includes the first trigger 21, the second trigger 22, reset circuit 23 and the insensitive deferred telegram of PVT
Road 24.
Wherein, the input end of clock of the first trigger 21 is for inputting the first clock signal CK_REF, signal output end
For exporting the first signal UP；The input end of clock of second trigger 22 is for inputting second clock signal CK_DLY, signal
Output end is for exporting second signal DN；The input terminal of reset circuit 23 be respectively coupled to the first trigger 21 signal output end and
The signal output end of second trigger 22；The output end of the input terminal coupling reset circuit 23 of the insensitive delay circuit 24 of PVT,
Output end is respectively coupled to the RESET input of the first trigger 21 and the RESET input of the second trigger 22.
Compared to above-mentioned first embodiment, using the insensitive delay circuit 24 of PVT instead of above-mentioned implementation in the present embodiment
Delay circuit 14 in example, so that its influence to technique, supply voltage and temperature (PVT) reduces.
Specifically, as shown in figure 4, Fig. 4 is the first circuit diagram of the insensitive delay circuit of PVT in Fig. 3.
The insensitive delay circuit 24 of the PVT includes the negater circuit group of at least one negater circuit 241 in the present embodiment,
Its input terminal couples the output end of reset circuit, and output end couples the RESET input and second trigger of the first trigger
The RESET input.
Wherein, negater circuit group includes multiple negater circuits 241 sequentially coupled；First negater circuit therein it is defeated
Enter the output end of end coupling reset circuit 23, output end couples the input terminal of next negater circuit 241；It is therein the last one
The input terminal of negater circuit 241 couples the output end of a upper negater circuit 241, and output end couples the reset of the first trigger 21
The RESET input of input terminal and the second trigger 22.
Wherein, negater circuit 241 includes: not circuit, input terminal of the input terminal as negater circuit；Resistance, one
The output end of end coupling not circuit, output end of the other end as negater circuit；Capacitor, one end coupling resistance it is another
End, other end ground connection.
Specifically, as shown in figure 5, Fig. 5 is the second circuit schematic diagram of the insensitive delay circuit of PVT in Fig. 3.
Wherein, the insensitive delay circuit 24 of PVT includes: the first negater circuit 243, and input terminal couples reset circuit 23
Output end；Negater circuit group 245 comprising at least one RC retardation ratio circuit, input terminal couple the first negater circuit 243；Second
Negater circuit 247, input terminal couple the output end of negater circuit group 245, and output end couples the reset of the first trigger 21
The RESET input of input terminal and the second trigger 22.
Specifically, as shown in fig. 6, Fig. 6 is the tertiary circuit schematic diagram of the insensitive delay circuit of PVT in Fig. 3.
Wherein, the insensitive delay circuit 24 of PVT includes multiple RC retardation ratio circuits 249 sequentially coupled；First therein
The output end of the input terminal coupling reset circuit 23 of RC retardation ratio circuit, output end couple the input terminal of next negater circuit；Its
In the input terminal of the last one RC retardation ratio circuit couple the output end of upper RC retardation ratio circuit, output end coupling first triggers
The RESET input of the RESET input of device 21 and the second trigger 22.
It should be understood that in the embodiment in figure 1, the delay time using chain of inverters is the threshold voltage by transistor
It is determined with drift characteristic, these factors are by technique, and voltage, temperature (PVT's) is affected.
In the embodiment of Fig. 4-6, by the way of RC retardation ratio, wherein capacitor is hardly influenced by PVT, in addition,
Resistance is also much smaller by technique influence property compared with transistor, so hardly being influenced by voltage and temperature.
Therefore, so delay time variation caused by PVT changes can be reduced by constituting delay circuit with capacitor using resistance.
Optionally, in another embodiment, the insensitive delay circuit of PVT in the embodiment of above-mentioned Fig. 4-6 can also wrap
Multiplexer is included, multiple input terminals of the multiplexer are respectively coupled to the output end of multiple negater circuits, output end coupling described the
The RESET input of the RESET input of one trigger and second trigger.
It should be understood that multiplexer includes multiple input terminals and an output end, its role is to believe from multiple inputs
An output is selected in number, the quantity of negater circuit in the insensitive delay circuit of PVT can be adjusted in this way
It is whole, its delay degree to be adjusted.
Phase and frequency detection circuit provided in this embodiment includes: the first trigger, and input end of clock is for inputting
First clock signal, signal output end is for exporting the first signal；Second trigger, input end of clock is for inputting second
Clock signal, signal output end is for exporting second signal；Reset circuit, input terminal are respectively coupled to the letter of the first trigger
The signal output end of number output end and the second trigger；The insensitive delay circuit of PVT, input terminal couple the output of reset circuit
End, output end are respectively coupled to the RESET input of the first trigger and the RESET input of the second trigger.Pass through above-mentioned side
Formula can reduce the influence of technique, voltage, temperature using the insensitive delay circuit of PVT, can reduce delay caused by PVT variation
Time change.
It is the structural schematic diagram of one embodiment of charge pump phase and frequency detector provided by the present application refering to Fig. 7, Fig. 7,
The charge pump phase and frequency detector 70 is insensitive including the first trigger 71, the second trigger 72, reset circuit 73, PVT
Delay circuit 74 and charge pump 75.
Wherein, the input end of clock of the first trigger 71 is for inputting the first clock signal CK_REF, signal output end
For exporting the first signal UP；The input end of clock of second trigger 72 is for inputting second clock signal CK_DLY, signal
Output end is for exporting second signal DN；The first input end of charge pump 75 couples the signal output end of the first trigger 71,
Second input terminal couples the signal output end of the second trigger 72, and output end is used for output signal；The input of reset circuit 73
End is respectively coupled to the signal output end of the first trigger 71 and the signal output end of the second trigger 72；The insensitive deferred telegram of PVT
Road 74 input terminal coupling reset circuit 73 output end, output end be respectively coupled to the first trigger 71 the RESET input and
The RESET input of second trigger 72.
It is the structural schematic diagram of one embodiment of phase-locked loop circuit provided by the present application, the phase-locked loop circuit refering to Fig. 8, Fig. 8
80 include charge pump phase and frequency detector 81, loop filter 82, voltage controlled oscillator 83 and frequency divider.
Wherein, charge pump phase and frequency detector 81 is such as the charge pump phase and frequency detection in above-described embodiment
Device, structure is similar with working principle, and which is not described herein again；The input terminal of loop filter 82 couples charge pump phase and frequency
The output end of charge pump in detector 81；The output end of the input terminal coupling loop filter 82 of voltage controlled oscillator 83, output
End is used for output signal；The output end of the input terminal coupling voltage controlled oscillator 83 of frequency divider 84, output end couple charge pump phase
The input end of clock of second trigger in position and frequency detector 81, to form signal feedback.
The foregoing is merely presently filed embodiments, are not intended to limit the scope of the patents of the application, all to utilize this
Equivalent structure or equivalent flow shift made by application specification and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field similarly includes in the scope of patent protection of the application.
Claims (10)
1. a kind of phase and frequency detection circuit characterized by comprising
First trigger, input end of clock is for inputting the first clock signal, and signal output end is for exporting the first signal；
Second trigger, input end of clock is for inputting second clock signal, and signal output end is for exporting second signal；
Reset circuit, input terminal are respectively coupled to the signal output end of first trigger and the signal of second trigger
Output end；
The insensitive delay circuit of PVT, input terminal couple the output end of the reset circuit, and output end is respectively coupled to described
The RESET input of the RESET input of one trigger and second trigger.
2. phase and frequency detection circuit according to claim 1, which is characterized in that
The insensitive delay circuit of PVT includes:
Negater circuit group comprising at least one negater circuit, input terminal couple the output end of the reset circuit, output
End couples the RESET input of first trigger and the RESET input of second trigger.
3. phase and frequency detection circuit according to claim 2, which is characterized in that
Negater circuit group includes multiple negater circuits sequentially coupled；
The input terminal of first negater circuit therein couples the output end of the reset circuit, and output end coupling is next reversed
The input terminal of circuit；
The input terminal of the last one negater circuit therein couples the output end of a upper negater circuit, and output end couples described the
The RESET input of the RESET input of one trigger and second trigger.
4. the phase and frequency detection circuit according to Claims 2 or 3, which is characterized in that
The negater circuit includes:
Not circuit, input terminal of the input terminal as the negater circuit；
Resistance, one end couple the output end of the not circuit, output end of the other end as the negater circuit；
Capacitor, one end couple the other end of the resistance, other end ground connection.
5. phase and frequency detection circuit according to claim 3, which is characterized in that
The phase and frequency detection circuit further includes multiplexer；
Multiple input terminals of the multiplexer are respectively coupled to the output end of multiple negater circuits, output end coupling first touching
Send out the RESET input of device and the RESET input of second trigger.
6. phase and frequency detection circuit according to claim 1, which is characterized in that
The insensitive delay circuit of PVT includes:
First inverter cricuit, input terminal couple the output end of the reset circuit；
Negater circuit group comprising at least one RC retardation ratio circuit, input terminal couple first inverter cricuit；
Second inverter cricuit, input terminal couple the output end of the inverter cricuit group, output end coupling first triggering
The RESET input of the RESET input of device and second trigger.
7. phase and frequency detection circuit according to claim 1, which is characterized in that
The insensitive delay circuit of PVT includes multiple RC retardation ratio circuits sequentially coupled；
The input terminal of first RC retardation ratio circuit therein couples the output end of the reset circuit, and output end coupling is next anti-
To the input terminal of circuit；
The input terminal of the last one RC retardation ratio circuit therein couples the output end of upper RC retardation ratio circuit, and output end couples institute
State the RESET input of the first trigger and the RESET input of second trigger.
8. phase and frequency detection circuit according to claim 1, which is characterized in that
The reset circuit includes:
NAND gate circuit, first input end couple the signal output end of first trigger, and the second input terminal couples institute
State the signal output end of the second trigger.
9. a kind of charge pump phase and frequency detector characterized by comprising
First trigger, input end of clock is for inputting the first clock signal, and signal output end is for exporting the first signal；
Second trigger, input end of clock is for inputting second clock signal, and signal output end is for exporting second signal；
Charge pump, first input end couple the signal output end of first trigger, the second input terminal coupling described the
The signal output end of two triggers, output end are used for output signal；
Reset circuit, input terminal are respectively coupled to the signal output end of first trigger and the signal of second trigger
Output end；
The insensitive delay circuit of PVT, input terminal couple the output end of the reset circuit, and output end is respectively coupled to described
The RESET input of the RESET input of one trigger and second trigger.
10. a kind of phase-locked loop circuit characterized by comprising
Charge pump phase and frequency detector；Wherein, the charge pump phase and frequency detector is as claimed in claim 9
Charge pump phase and frequency detector；
Loop filter, input terminal couple the output end of charge pump in the charge pump phase and frequency detector；
Voltage controlled oscillator, input terminal couple the output end of the loop filter, and output end is used for output signal；
Frequency divider, input terminal couple the output end of the voltage controlled oscillator, and output end couples the charge pump phase and frequency
The input end of clock of second trigger in rate detector.
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| CN201811593784.8A CN109743058B (en) | 2018-12-25 | 2018-12-25 | Phase frequency detection circuit, charge pump phase frequency detector and phase-locked loop circuit |
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| CN201811593784.8A CN109743058B (en) | 2018-12-25 | 2018-12-25 | Phase frequency detection circuit, charge pump phase frequency detector and phase-locked loop circuit |
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| CN109743058B CN109743058B (en) | 2023-06-20 |
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Cited By (1)
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| CN109743058B (en) | 2023-06-20 |
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