CN109743058B - Phase frequency detection circuit, charge pump phase frequency detector and phase-locked loop circuit - Google Patents
Phase frequency detection circuit, charge pump phase frequency detector and phase-locked loop circuit Download PDFInfo
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Abstract
The application discloses phase frequency detection circuitry, charge pump phase frequency detector and phase-locked loop circuit, this phase frequency detection circuitry includes: the first trigger is used for inputting a first clock signal at a clock input end and outputting a first signal at a signal output end; the second trigger, its clock input end is used for inputting the second clock signal, its signal output end is used for outputting the second signal; the input end of the reset circuit is respectively coupled with the signal output end of the first trigger and the signal output end of the second trigger; the input end of the PVT insensitive delay circuit is coupled with the output end of the reset circuit, and the output end of the PVT insensitive delay circuit is respectively coupled with the reset input end of the first trigger and the reset input end of the second trigger. By the method, the influence of the process, the voltage and the temperature can be reduced, and delay time variation caused by PVT variation can be reduced.
Description
Technical Field
The present disclosure relates to the field of circuit technologies, and in particular, to a phase frequency detection circuit, a charge pump phase frequency detector, and a phase-locked loop circuit.
Background
The PFD (phase frequency detector) plays a central role in a phase synchronization circuit (PLL/DLL) as a circuit for detecting a phase difference between an original CLC (phase) and a restored CLC. The PFD can detect the phase difference between the data (data) input from the reception unit display interface (display interface) and the recovery phase difference, and thus plays a key role in detecting the data recovery BUR.
However, the performance of existing PFDs is strongly affected by process, supply voltage and temperature (PVT) variations, causing the detector to degrade.
Disclosure of Invention
The application mainly provides a phase frequency detection circuit, a charge pump phase frequency detector and a phase-locked loop circuit, which can reduce the influence of a process, a power supply voltage and temperature (PVT) on a PFD.
The application adopts a technical scheme to provide a phase and frequency detection circuit, this detection circuit includes: the first trigger is used for inputting a first clock signal at a clock input end and outputting a first signal at a signal output end; the second trigger, its clock input end is used for inputting the second clock signal, its signal output end is used for outputting the second signal; the input end of the reset circuit is respectively coupled with the signal output end of the first trigger and the signal output end of the second trigger; the input end of the PVT insensitive delay circuit is coupled with the output end of the reset circuit, and the output end of the PVT insensitive delay circuit is respectively coupled with the reset input end of the first trigger and the reset input end of the second trigger.
Wherein the PVT insensitive delay circuit comprises: and the input end of the reversing circuit group is coupled with the output end of the reset circuit, and the output end of the reversing circuit group is coupled with the reset input end of the first trigger and the reset input end of the second trigger.
The reversing circuit group comprises a plurality of reversing circuits which are coupled in sequence; the input end of the first reversing circuit is coupled with the output end of the reset circuit, and the output end of the first reversing circuit is coupled with the input end of the next reversing circuit; the input end of the last reversing circuit is coupled with the output end of the reversing circuit, and the output end of the last reversing circuit is coupled with the reset input end of the first trigger and the reset input end of the second trigger.
Wherein the reverse circuit includes: an inverter circuit having an input terminal as an input terminal of the inverter circuit; one end of the resistor is coupled with the output end of the NOT circuit, and the other end of the resistor is used as the output end of the reversing circuit; one end of the capacitor is coupled with the other end of the resistor, and the other end of the capacitor is grounded.
The phase and frequency detection circuit further comprises a multiplexer; the multiplexer has a plurality of input terminals coupled to the output terminals of the plurality of inverting circuits, respectively, and an output terminal coupled to the reset input terminal of the first flip-flop and the reset input terminal of the second flip-flop.
Wherein the PVT insensitive delay circuit comprises: the input end of the first reversing circuit is coupled with the output end of the reset circuit; an inverting circuit group comprising at least one RC delay circuit, the input end of which is coupled with the first inverting circuit; and the input end of the second reversing circuit is coupled with the output end of the reversing circuit group, and the output end of the second reversing circuit is coupled with the reset input end of the first trigger and the reset input end of the second trigger.
Wherein the PVT insensitive delay circuit comprises a plurality of RC delay circuits coupled in sequence; the input end of the first RC delay circuit is coupled with the output end of the reset circuit, and the output end of the first RC delay circuit is coupled with the input end of the next reversing circuit; the input end of the last RC delay circuit is coupled with the output end of the last RC delay circuit, and the output end of the last RC delay circuit is coupled with the reset input end of the first trigger and the reset input end of the second trigger.
Wherein, reset circuit includes: the first input end of the NAND gate is coupled with the signal output end of the first trigger, and the second input end of the NAND gate is coupled with the signal output end of the second trigger.
Another technical solution adopted in the present application is to provide a charge pump phase and frequency detector, the detector comprising: the first trigger is used for inputting a first clock signal at a clock input end and outputting a first signal at a signal output end; the second trigger, its clock input end is used for inputting the second clock signal, its signal output end is used for outputting the second signal; the first input end of the charge pump is coupled with the signal output end of the first trigger, the second input end of the charge pump is coupled with the signal output end of the second trigger, and the output end of the charge pump is used for outputting signals; the input end of the reset circuit is respectively coupled with the signal output end of the first trigger and the signal output end of the second trigger; the input end of the PVT insensitive delay circuit is coupled with the output end of the reset circuit, and the output end of the PVT insensitive delay circuit is respectively coupled with the reset input end of the first trigger and the reset input end of the second trigger.
Another technical solution adopted in the present application is to provide a phase-locked loop circuit, which includes: a charge pump phase and frequency detector; wherein the charge pump phase and frequency detector is a charge pump phase and frequency detector as described above; the input end of the loop filter is coupled with the output end of the charge pump in the charge pump phase and frequency detector; the input end of the voltage-controlled oscillator is coupled with the output end of the loop filter, and the output end of the voltage-controlled oscillator is used for outputting signals; the input end of the frequency divider is coupled with the output end of the voltage-controlled oscillator, and the output end of the frequency divider is coupled with the clock input end of the second trigger in the charge pump phase and frequency detector.
The phase and frequency detection circuit provided by the application comprises: the first trigger is used for inputting a first clock signal at a clock input end and outputting a first signal at a signal output end; the second trigger, its clock input end is used for inputting the second clock signal, its signal output end is used for outputting the second signal; the input end of the reset circuit is respectively coupled with the signal output end of the first trigger and the signal output end of the second trigger; the input end of the PVT insensitive delay circuit is coupled with the output end of the reset circuit, and the output end of the PVT insensitive delay circuit is respectively coupled with the reset input end of the first trigger and the reset input end of the second trigger. By adopting the PVT insensitive delay circuit, the influence of the process, the voltage and the temperature can be reduced, and the delay time change caused by PVT change can be reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a circuit schematic of a first embodiment of a phase and frequency detection circuit provided herein;
FIG. 2 is a timing diagram of FIG. 1;
FIG. 3 is a circuit schematic of a second embodiment of the phase and frequency detection circuit provided herein;
FIG. 4 is a first circuit schematic of the PVT insensitive delay circuit of FIG. 3;
FIG. 5 is a second circuit schematic of the PVT insensitive delay circuit of FIG. 3;
FIG. 6 is a third circuit schematic of the PVT insensitive delay circuit of FIG. 3;
FIG. 7 is a schematic diagram of an embodiment of a charge pump phase and frequency detector provided herein;
fig. 8 is a schematic structural diagram of an embodiment of a pll circuit provided in the present application.
Detailed Description
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, fig. 1 is a circuit schematic diagram of a first embodiment of a phase and frequency detection circuit provided herein, and the phase and frequency detection circuit 10 includes a first flip-flop 11, a second flip-flop 12, a reset circuit 13, and a delay circuit 14.
The clock input end of the first flip-flop 11 is used for inputting a first clock signal ck_ref, and the signal output end of the first flip-flop 11 is used for outputting a first signal UP; the clock input end of the second trigger 12 is used for inputting a second clock signal CK_DLY, and the signal output end is used for outputting a second signal DN; the input end of the reset circuit 13 is coupled with the signal output end of the first trigger 11 and the signal output end of the second trigger 12 respectively; an input terminal of the delay circuit 14 is coupled to an output terminal of the reset circuit 13, and output terminals thereof are respectively coupled to the reset input terminal of the first flip-flop 11 and the reset input terminal of the second flip-flop 12.
Optionally, the first flip-flop 11 and the second flip-flop 12 are D flip-flops, and a truth table of the D flip-flops is as follows:
| D | CLK | Q | QN |
| 0 | clock rising edge | 0 | 1 |
| 1 | Clock rising edge | 1 | 0 |
| × | 0 | last Q | last QN |
| × | 1 | last Q | last QN |
Referring also to fig. 2, fig. 2 is a timing diagram of fig. 1.
In the case of delay hysteresis (late delay clock case), the UP signal becomes 1 in synchronization with the ck_ref rising edge, and the DN signal becomes 1 in synchronization with the ck_dly rising edge. After the UP signal and DN signal become 1, the path through the reset circuit 13 and the delay circuit 14 carries out logic delay, the delay time is t d，rst Delayed UP messageThe number and DN signals return to 0. After the pulses of the UP and DN signals occurring on the PFD are accumulated by a subsequent charge pump (not shown), the phase synchronization circuit is started and the pulse amplitudes of the UP and DN signals are made the same under the action of the feedback circuit.
In the case of the delay advance (early delay clock case), the DN signal becomes 1 in synchronization with the CK_DLY rising edge, and the UP signal becomes 1 in synchronization with the CK_REF rising edge. After the UP signal and DN signal become 1, the path through the reset circuit 13 and the delay circuit 14 carries out logic delay, the delay time is t d，rst After the delay the UP and DN signals return to 0. After the pulses of the UP and DN signals occurring on the PFD are accumulated by a subsequent charge pump (not shown), the phase synchronization circuit is started and the pulse amplitudes of the UP and DN signals are made the same under the action of the feedback circuit.
The PFD in the above embodiment can correctly detect the phase difference and the detection speed is high. The PFD described above has its drawbacks. For example, the pulse amplitudes of the UP signal and the DN signal are determined according to the path delay times of the reset circuit 13 and the delay circuit 14, and when the influence of PVT variations on the pulse amplitudes of the UP signal and the DN signal is large, the influence on the circuit is large.
Referring to fig. 3, fig. 3 is a circuit schematic of a second embodiment of the phase and frequency detection circuit provided herein, and the phase and frequency detection circuit 20 includes a first flip-flop 21, a second flip-flop 22, a reset circuit 23, and a PVT insensitive delay circuit 24.
The clock input end of the first flip-flop 21 is used for inputting a first clock signal ck_ref, and the signal output end of the first flip-flop 21 is used for outputting a first signal UP; the clock input end of the second flip-flop 22 is used for inputting a second clock signal CK_DLY, and the signal output end is used for outputting a second signal DN; the input end of the reset circuit 23 is coupled with the signal output end of the first trigger 21 and the signal output end of the second trigger 22 respectively; the input terminal of the PVT insensitive delay circuit 24 is coupled to the output terminal of the reset circuit 23, and the output terminals thereof are respectively coupled to the reset input terminal of the first flip-flop 21 and the reset input terminal of the second flip-flop 22.
In comparison with the first embodiment described above, the PVT-insensitive delay circuit 24 is used in this embodiment instead of the delay circuit 14 in the above embodiment, so that its influence on the process, the power supply voltage, and the temperature (PVT) is reduced.
Specifically, as shown in fig. 4, fig. 4 is a first circuit schematic of the PVT insensitive delay circuit of fig. 3.
The PVT insensitive delay circuit 24 in this embodiment comprises at least one inverting circuit 241 having an input coupled to the output of the reset circuit and an output coupled to the reset input of the first flip-flop and the reset input of the second flip-flop.
Wherein the reverse circuit group comprises a plurality of reverse circuits 241 coupled in sequence; the input end of the first inverting circuit is coupled to the output end of the reset circuit 23, and the output end of the first inverting circuit is coupled to the input end of the next inverting circuit 241; the input terminal of the last inverting circuit 241 is coupled to the output terminal of an inverting circuit 241, and the output terminal thereof is coupled to the reset input terminal of the first flip-flop 21 and the reset input terminal of the second flip-flop 22.
Wherein the reverse circuit 241 includes: an inverter circuit having an input terminal as an input terminal of the inverter circuit; one end of the resistor is coupled with the output end of the NOT circuit, and the other end of the resistor is used as the output end of the reversing circuit; one end of the capacitor is coupled with the other end of the resistor, and the other end of the capacitor is grounded.
Specifically, as shown in fig. 5, fig. 5 is a second circuit schematic of the PVT insensitive delay circuit of fig. 3.
Wherein the PVT insensitive delay circuit 24 comprises: a first inverting circuit 243 having an input coupled to the output of the reset circuit 23; an inverting circuit set 245 including at least one RC delay circuit, an input terminal of which is coupled to the first inverting circuit 243; the second inverting circuit 247 has an input coupled to the output of the inverting circuit group 245 and an output coupled to the reset input of the first flip-flop 21 and the reset input of the second flip-flop 22.
Specifically, as shown in fig. 6, fig. 6 is a third circuit schematic of the PVT insensitive delay circuit of fig. 3.
Wherein the PVT insensitive delay circuit 24 includes a plurality of RC delay circuits 249 coupled in sequence; the input end of the first RC delay circuit is coupled with the output end of the reset circuit 23, and the output end of the first RC delay circuit is coupled with the input end of the next reversing circuit; the input end of the last RC delay circuit is coupled to the output end of the last RC delay circuit, and the output end of the last RC delay circuit is coupled to the reset input end of the first trigger 21 and the reset input end of the second trigger 22.
It will be appreciated that in the embodiment of fig. 1, the delay time of using an inverter chain is determined by the threshold voltage and drift characteristics of the transistors, and these factors are greatly affected by the process, voltage, and temperature (PVT).
In the embodiments of fig. 4-6, RC delay is used, where the capacitance is hardly affected by PVT, and in addition, the resistance is much less affected by the process than the transistor, and therefore hardly affected by voltage and temperature.
Therefore, the delay circuit is formed by using the resistor and the capacitor, so that delay time variation caused by PVT variation can be reduced.
Optionally, in another embodiment, the PVT insensitive delay circuit in the embodiment of fig. 4-6 above may further include a multiplexer, wherein a plurality of inputs of the multiplexer are coupled to the outputs of the plurality of inverting circuits, respectively, and an output of the multiplexer is coupled to the reset input of the first flip-flop and the reset input of the second flip-flop.
It will be appreciated that the multiplexer comprises a plurality of inputs and an output which is operative to select an output from a plurality of input signals in such a way that the number of inverting circuits in the PVT insensitive delay circuit can be adjusted to adjust the degree of delay thereof.
The phase and frequency detection circuit provided in this embodiment includes: the first trigger is used for inputting a first clock signal at a clock input end and outputting a first signal at a signal output end; the second trigger, its clock input end is used for inputting the second clock signal, its signal output end is used for outputting the second signal; the input end of the reset circuit is respectively coupled with the signal output end of the first trigger and the signal output end of the second trigger; the input end of the PVT insensitive delay circuit is coupled with the output end of the reset circuit, and the output end of the PVT insensitive delay circuit is respectively coupled with the reset input end of the first trigger and the reset input end of the second trigger. By adopting the PVT insensitive delay circuit, the influence of the process, the voltage and the temperature can be reduced, and the delay time change caused by PVT change can be reduced.
Referring to fig. 7, fig. 7 is a schematic diagram of an embodiment of a charge pump phase and frequency detector 70 provided herein, the charge pump phase and frequency detector 70 includes a first flip-flop 71, a second flip-flop 72, a reset circuit 73, a PVT insensitive delay circuit 74, and a charge pump 75.
The clock input terminal of the first flip-flop 71 is used for inputting a first clock signal ck_ref, and the signal output terminal thereof is used for outputting a first signal UP; the clock input terminal of the second flip-flop 72 is used for inputting a second clock signal ck_dly, and the signal output terminal thereof is used for outputting a second signal DN; the first input terminal of the charge pump 75 is coupled to the signal output terminal of the first flip-flop 71, the second input terminal thereof is coupled to the signal output terminal of the second flip-flop 72, and the output terminal thereof is used for outputting a signal; the input end of the reset circuit 73 is coupled to the signal output end of the first trigger 71 and the signal output end of the second trigger 72 respectively; an input of the PVT insensitive delay circuit 74 is coupled to an output of the reset circuit 73, and its output is coupled to the reset input of the first flip-flop 71 and the reset input of the second flip-flop 72, respectively.
Referring to fig. 8, fig. 8 is a schematic diagram of an embodiment of a phase-locked loop circuit provided herein, and the phase-locked loop circuit 80 includes a charge pump phase and frequency detector 81, a loop filter 82, a voltage-controlled oscillator 83, and a frequency divider.
The charge pump phase and frequency detector 81 is the same as that in the above embodiment, and the structure and the working principle are similar, and are not repeated here; an input of the loop filter 82 is coupled to an output of the charge pump in the charge pump phase and frequency detector 81; an input terminal of the voltage-controlled oscillator 83 is coupled to an output terminal of the loop filter 82, and an output terminal thereof is used for outputting a signal; an input of the frequency divider 84 is coupled to an output of the voltage controlled oscillator 83, and an output thereof is coupled to a clock input of a second flip-flop in the charge pump phase and frequency detector 81 to form a signal feedback.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application or other related technical fields are included in the scope of the patent application.
Claims (7)
1. A phase and frequency detection circuit, comprising:
the first trigger is used for inputting a first clock signal at a clock input end and outputting a first signal at a signal output end;
the second trigger, its clock input end is used for inputting the second clock signal, its signal output end is used for outputting the second signal;
the input end of the reset circuit is respectively coupled with the signal output end of the first trigger and the signal output end of the second trigger;
the input end of the PVT insensitive delay circuit is coupled with the output end of the reset circuit, and the output end of the PVT insensitive delay circuit is respectively coupled with the reset input end of the first trigger and the reset input end of the second trigger;
wherein the PVT insensitive delay circuit comprises: a first inverting circuit group including at least one inverting circuit, an input terminal of which is coupled to an output terminal of the reset circuit, and an output terminal of which is coupled to a reset input terminal of the first flip-flop and a reset input terminal of the second flip-flop;
or, the PVT insensitive delay circuit includes:
the input end of the first reverse circuit is coupled with the output end of the reset circuit;
a second inverting circuit group including at least one RC delay circuit, the input end of which is coupled with the first inverting circuit;
the input end of the second reversing circuit is coupled with the output end of the second reversing circuit group, and the output end of the second reversing circuit is coupled with the reset input end of the first trigger and the reset input end of the second trigger;
or, the PVT insensitive delay circuit includes:
a plurality of RC delay circuits coupled in sequence;
the input end of the first RC delay circuit is coupled with the output end of the reset circuit, and the output end of the first RC delay circuit is coupled with the input end of the next RC delay circuit;
the input end of the last RC delay circuit is coupled with the output end of the last RC delay circuit, and the output end of the last RC delay circuit is coupled with the reset input end of the first trigger and the reset input end of the second trigger.
2. The phase and frequency detection circuit of claim 1, wherein,
the first reversing circuit group comprises a plurality of reversing circuits which are coupled in sequence;
the input end of the first reversing circuit is coupled with the output end of the reset circuit, and the output end of the first reversing circuit is coupled with the input end of the next reversing circuit;
the input end of the last reversing circuit is coupled with the output end of the reversing circuit, and the output end of the last reversing circuit is coupled with the reset input end of the first trigger and the reset input end of the second trigger.
3. The phase and frequency detection circuit according to claim 1 or 2, wherein,
the inverting circuit includes:
an inverter circuit having an input as an input of the inverter circuit;
one end of the resistor is coupled with the output end of the NOT circuit, and the other end of the resistor is used as the output end of the reversing circuit;
one end of the capacitor is coupled with the other end of the resistor, and the other end of the capacitor is grounded.
4. The phase and frequency detection circuit of claim 2, wherein,
the phase and frequency detection circuit further comprises a multiplexer;
the input ends of the multiplexer are respectively coupled with the output ends of the reversing circuits, and the output ends of the multiplexer are coupled with the reset input end of the first trigger and the reset input end of the second trigger.
5. The phase and frequency detection circuit of claim 1, wherein,
the reset circuit includes:
and the first input end of the NAND gate is coupled with the signal output end of the first trigger, and the second input end of the NAND gate is coupled with the signal output end of the second trigger.
6. A charge pump phase and frequency detector, comprising:
the first trigger is used for inputting a first clock signal at a clock input end and outputting a first signal at a signal output end;
the second trigger, its clock input end is used for inputting the second clock signal, its signal output end is used for outputting the second signal;
the first input end of the charge pump is coupled with the signal output end of the first trigger, the second input end of the charge pump is coupled with the signal output end of the second trigger, and the output end of the charge pump is used for outputting signals;
the input end of the reset circuit is respectively coupled with the signal output end of the first trigger and the signal output end of the second trigger;
the input end of the PVT insensitive delay circuit is coupled with the output end of the reset circuit, and the output end of the PVT insensitive delay circuit is respectively coupled with the reset input end of the first trigger and the reset input end of the second trigger;
wherein the PVT insensitive delay circuit comprises: a first inverting circuit group including at least one inverting circuit, an input terminal of which is coupled to an output terminal of the reset circuit, and an output terminal of which is coupled to a reset input terminal of the first flip-flop and a reset input terminal of the second flip-flop;
or, the PVT insensitive delay circuit includes:
the input end of the first reverse circuit is coupled with the output end of the reset circuit;
a second inverting circuit group including at least one RC delay circuit, the input end of which is coupled with the first inverting circuit;
the input end of the second reversing circuit is coupled with the output end of the second reversing circuit group, and the output end of the second reversing circuit is coupled with the reset input end of the first trigger and the reset input end of the second trigger;
or, the PVT insensitive delay circuit includes:
a plurality of RC delay circuits coupled in sequence;
the input end of the first RC delay circuit is coupled with the output end of the reset circuit, and the output end of the first RC delay circuit is coupled with the input end of the next RC delay circuit;
the input end of the last RC delay circuit is coupled with the output end of the last RC delay circuit, and the output end of the last RC delay circuit is coupled with the reset input end of the first trigger and the reset input end of the second trigger.
7. A phase locked loop circuit comprising:
a charge pump phase and frequency detector; wherein the charge pump phase and frequency detector is the charge pump phase and frequency detector of claim 6;
a loop filter having an input coupled to an output of a charge pump in the charge pump phase and frequency detector;
the input end of the voltage-controlled oscillator is coupled with the output end of the loop filter, and the output end of the voltage-controlled oscillator is used for outputting signals;
and the input end of the frequency divider is coupled with the output end of the voltage-controlled oscillator, and the output end of the frequency divider is coupled with the clock input end of the second trigger in the charge pump phase and frequency detector.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1549452A (en) * | 2003-05-12 | 2004-11-24 | 瑞昱半导体股份有限公司 | Phase frequency detecting circuit for phaselocked loop circuit |
| US7940088B1 (en) * | 2009-03-31 | 2011-05-10 | Pmc-Sierra, Inc. | High speed phase frequency detector |
| US8461890B1 (en) * | 2011-07-20 | 2013-06-11 | United Microelectronics Corp. | Phase and/or frequency detector, phase-locked loop and operation method for the phase-locked loop |
| CN103259539A (en) * | 2012-02-02 | 2013-08-21 | 联发科技股份有限公司 | Phase frequency detector |
| CN103633999A (en) * | 2012-08-20 | 2014-03-12 | 南亚科技股份有限公司 | Phase-locked loop and method for clock delay adjustment |
| CN204442344U (en) * | 2013-10-31 | 2015-07-01 | 是德科技股份有限公司 | Charge pump phase-frequency detector and phase-locked loop circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7274764B2 (en) * | 2003-11-20 | 2007-09-25 | Avago Technologies General Ip (Singapore) Pte. Ltd | Phase detector system with asynchronous output override |
| KR100719693B1 (en) * | 2006-02-15 | 2007-05-17 | 주식회사 하이닉스반도체 | Phase locked loop for operating stably insensible of variations of process, voltage, and temperature and operation method with the same |
| US7859344B2 (en) * | 2008-04-29 | 2010-12-28 | Renesas Electronics Corporation | PLL circuit with improved phase difference detection |
| KR101045072B1 (en) * | 2009-12-28 | 2011-06-29 | 주식회사 하이닉스반도체 | Phase locked loop and method for driving the same |
-
2018
- 2018-12-25 CN CN201811593784.8A patent/CN109743058B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1549452A (en) * | 2003-05-12 | 2004-11-24 | 瑞昱半导体股份有限公司 | Phase frequency detecting circuit for phaselocked loop circuit |
| US7940088B1 (en) * | 2009-03-31 | 2011-05-10 | Pmc-Sierra, Inc. | High speed phase frequency detector |
| US8461890B1 (en) * | 2011-07-20 | 2013-06-11 | United Microelectronics Corp. | Phase and/or frequency detector, phase-locked loop and operation method for the phase-locked loop |
| CN103259539A (en) * | 2012-02-02 | 2013-08-21 | 联发科技股份有限公司 | Phase frequency detector |
| CN103633999A (en) * | 2012-08-20 | 2014-03-12 | 南亚科技股份有限公司 | Phase-locked loop and method for clock delay adjustment |
| CN204442344U (en) * | 2013-10-31 | 2015-07-01 | 是德科技股份有限公司 | Charge pump phase-frequency detector and phase-locked loop circuit |
Non-Patent Citations (2)
| Title |
|---|
| "自偏置自适应电荷泵锁相环";魏建军等;《四川大学学报(工程科学版)》;20100331;第42卷(第2期);第188-194页 * |
| Wei Deng等."A 0.022mm2 970μW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuits".《2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers》.2013,第248-250页. * |
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| CN109743058A (en) | 2019-05-10 |
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