CN110190847B - Decimal N frequency dividing circuit and method applied to frequency synthesizer - Google Patents

Decimal N frequency dividing circuit and method applied to frequency synthesizer Download PDF

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CN110190847B
CN110190847B CN201910344541.9A CN201910344541A CN110190847B CN 110190847 B CN110190847 B CN 110190847B CN 201910344541 A CN201910344541 A CN 201910344541A CN 110190847 B CN110190847 B CN 110190847B
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CN110190847A (en
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黄海生
杨毅
李鑫
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Xian University of Posts and Telecommunications
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Xian University of Posts and Telecommunications
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/1806—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the frequency divider comprising a phase accumulator generating the frequency divided signal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

In order to solve the problem of structural parasitism of a fractional frequency division circuit of a Sigma-delta modulator adopting a MASH1-1-1 structure, the invention provides a fractional N frequency division circuit and a method applied to a frequency synthesizer. The decimal N frequency dividing circuit comprises a MASH1-1-1 Sigma-delta modulator, a frequency dividing counting circuit Ncount and a prepositive P/(P+1) prescaler; the device also comprises a pseudo random sequence generating circuit Dither and an adder; the pseudo-random sequence generating circuit Dither is used for generating an n-bit pseudo-random sequence and sending the n-bit pseudo-random sequence to the n-bit adder I; and the N-bit adder I is used for summing the decimal value N_frac [ N-1:0] received by the decimal N frequency dividing circuit and the N-bit pseudorandom sequence in each clock period, and sending the summation result corresponding to each clock period to the input end of the MASH1-1-1 Sigma-delta modulator.

Description

Decimal N frequency dividing circuit and method applied to frequency synthesizer
Technical Field
The invention belongs to the technical field of frequency synthesizers, and relates to a decimal N frequency dividing circuit and a decimal N frequency dividing method applied to a frequency synthesizer.
Background
When the radio frequency chip processes signals, the radio frequency chip needs to filter, amplify and down-convert the received signals, and then A/D (analog/digital) conversion is carried out on analog signals obtained by down-conversion, so that digital signals which can be processed by a baseband circuit are generated. The local oscillator frequency used for down-conversion is generated by multiplying a reference frequency generated by a crystal oscillator by a frequency synthesizer in which a frequency divider is critical to providing a plurality of high precision frequency signals. The frequency divider in the traditional frequency synthesizer is of an integer frequency division structure, so that in order to generate adjacent channel frequencies with smaller frequency intervals, the reference frequency is required to be smaller, the frequency division coefficient is larger, and the noise immunity is poor; on this basis, a fractional divider based on Sigma-delta modulation technology is presented, which can obtain higher frequency resolution and extremely low phase spurious, but due to the limitation of the digital circuit itself, the fractional divider based on Sigma-delta modulation technology actually performs integer division at every instant, and then performs fractional division in a statistical sense in one period. Most circuits use Sigma-delta modulators with MASH1-1-1 structure due to circuit complexity and power consumption, but when the input decimal value is the negative integer power of 2 or the sum and difference of the negative integer powers, the output end has a limited circulation problem, namely the structure parasitic of the modulator, so that burrs appear in the frequency domain, and the burrs deteriorate the overall phase noise of the frequency synthesizer.
Disclosure of Invention
In order to solve the problem of structural parasitism of a fractional frequency division circuit of a Sigma-delta modulator adopting a MASH1-1-1 structure, the invention provides a fractional N frequency division circuit and a method applied to a frequency synthesizer.
The technical scheme of the invention is as follows:
a fractional-N frequency dividing circuit applied to a frequency synthesizer comprises a MASH1-1-1 Sigma-delta modulator, a frequency dividing counting circuit Ncount and a prepositive P/(P+1) prescaler; the special feature is that:
the device also comprises a pseudo random sequence generating circuit Dither and an adder;
the pseudo-random sequence generating circuit Dither is used for generating an n-bit pseudo-random sequence and sending the n-bit pseudo-random sequence to the n-bit adder I;
and the N-bit adder I is used for summing the decimal value N_frac [ N-1:0] received by the decimal N frequency dividing circuit and the N-bit pseudorandom sequence in each clock period, and sending the summation result corresponding to each clock period to the decimal input end of the MASH1-1-1 Sigma-delta modulator.
Further, the pseudo random sequence has an average value of 0 in one division period.
Further, the pseudo random sequence generating circuit Dither includes an m-sequence generating circuit and an output sequence generating circuit;
the m-sequence generating circuit comprises 3 two-input exclusive-OR gates xor 1-xor 3 and 24 registers reg 0-reg 23 connected in series;
wherein:
the input ends of the two input exclusive-OR gates xor3 are respectively connected with the output ends Q of registers reg22 and reg23;
the input ends of the two input exclusive-OR gates xor2 are respectively connected with the output ends Q of registers reg0 and reg 17;
the input ends of the two-input exclusive-OR gate xor1 are respectively connected with the output ends of the two-input exclusive-OR gate xor3 and the two-input exclusive-OR gate xor 2; the output end of the two-input exclusive-OR gate xor1 is connected with the input end D of the register reg 0;
the output sequence generating circuit comprises two-input exclusive-or gates xor4 and xor5, two-input AND gates and1 and2, two-input OR gate 1 and registers D_reg0 and D_reg1;
two input ends of the two-input exclusive-OR gate xor4 are respectively connected with output ends Q of registers reg0 and reg 3;
two input ends of the two-input exclusive-OR gate xor5 are respectively connected with the output end Q of the two-input exclusive-OR gate xor4 and the output end Q of the register reg 6;
two input ends of the two-input AND gate and1 are respectively connected with the output ends Q of registers reg0 and reg 3;
the two input ends of the two-input AND gate and2 are respectively connected with the output end Q of the two-input exclusive-OR gate xor4 and the output end Q of the register reg 6;
the two input ends of the two-input OR gate 1 are respectively connected with the output ends of the two-input AND gate and1 and the two-input AND gate and 2;
the input end of the register D_reg0 is connected with the output ends of the two-input exclusive-OR gate xor5, and the output of the register D_reg0 is dither [0];
the input end of the register D_reg1 is connected with the output ends of two input OR gates 1, and the output end of the register D_reg0 is dither [1];
during reset, the values of registers reg 0-reg 23 are: 0100_1110_1011_0101_0111_1011.
The invention also provides a decimal N frequency dividing method applied to the frequency synthesizer, which is characterized in that:
1) Summing the decimal value N_frac [ N-1:0] received by the decimal N frequency dividing circuit with the N-bit pseudorandom sequence in each clock cycle;
2) Generating a modulation sequence of-3 to 4 by the MASH1-1-1 Sigma-delta modulator according to the summation result of the step 1), and adding the modulation sequence of-3 to 4 to the integer value received by the fractional-N frequency dividing circuit so as to generate a frequency dividing ratio;
3) The frequency division counting circuit Ncount divides the output signal clk of the pre-P/(P+1) prescaler according to the frequency division ratio to generate a control signal Mod and an expected frequency signal Outclk; the control signal Mod is used for controlling the pre-P/(P+1) prescaler to carry out P frequency division or P+1 frequency division, when the control signal Mod is 1, the pre-P/(P+1) prescaler carries out P+1 frequency division, and when the control signal Mod is 0, the pre-P/(P+1) prescaler carries out P frequency division.
Further, in step 1), the average value of the n-bit pseudo random sequence in one frequency division period is 0.
Compared with the prior art, the invention has the advantages that:
1. the invention can effectively break the original output sequence period of the modulator and can output a modulation sequence with smooth frequency spectrum and no burr after adding the pseudo-random sequence to some decimal input values which have very poor randomness and have shorter output sequence period of the modulator.
2. The invention has good pseudo-random decimal input value for the output sequence of the modulator, and can further disorder the output period of the modulation sequence, so that the frequency spectrum of the output modulation sequence is smoother, and the generation of burrs is greatly reduced.
3. After the pseudo-random sequence is added, the performance of the whole circuit is improved on the premise of not changing the output result of the whole circuit.
4. The invention deforms m sequence under the precondition of not changing output period of random sequence, in one output period, outputs of 3 registers are used to generate pseudo random sequence values of 1, 0, -1 and2 through an output sequence generating circuit.
Drawings
Fig. 1 is a functional block diagram of an embodiment of a fractional-N circuit of the present invention.
Fig. 2 is a schematic diagram of a fractional-N frequency circuit of the present invention.
Fig. 3 is a circuit diagram of an M Counter in the divide count circuit Ncount.
Fig. 4 is a circuit diagram of an a Counter in the divide count circuit Ncount.
FIG. 5 is a circuit diagram of a MASH1-1-1 Sigma-delta modulator (adder one and pseudo-random sequence generating circuit Dither are not part of the modulator circuit and are shown to more clearly illustrate the signal flow direction).
Fig. 6 is a circuit diagram of the pseudo random sequence generating circuit Dither.
FIG. 7 is a simulation result of modeling a MASH1-1-1 Sigma-delta modulator in ADS (Advanced Design System) software prior to addition of a pseudorandom sequence, wherein: (a) is a modulator output sequence spectrum graph with an input value of 0.25, (b) is a modulator output sequence spectrum graph with an input value of 0.75, and (c) is a modulator output sequence spectrum graph with an input value of 0.4637. (a) In (c), the left plot shows the actual value of the MASH1-1-1 Sigma-delta modulator output sequence, and the right plot shows the spectrogram of the MASH1-1-1 Sigma-delta modulator output sequence.
FIG. 8 is a simulation result of modeling a MASH1-1-1 Sigma-delta modulator in ADS (Advanced Design System) software after addition of a pseudorandom sequence, wherein: (a) is a modulator output sequence spectrum graph with an input value of 0.25, (b) is a modulator output sequence spectrum graph with an input value of 0.75, and (c) is a modulator output sequence spectrum graph with an input value of 0.4637. (a) In (c), the left plot shows the actual value of the MASH1-1-1 Sigma-delta modulator output sequence, and the right plot shows the spectrogram of the MASH1-1-1 Sigma-delta modulator output sequence.
In fig. 1:
n_int [7:0] is an integer value in the input MASH1-1-1 Sigma-delta modulator;
n_frac [19:0] is the fractional value of the input MASH1-1-1 Sigma-delta modulator;
n_div [7:0] is the frequency division ratio generated by the MASH1-1-1 Sigma-delta modulator and input into the frequency division counting circuit Ncount;
dither [19:0] is a pseudo-random sequence signal generated by a pseudo-random sequence generating circuit Dither;
outclk is the final output frequency signal of the frequency dividing circuit;
mod is a control signal of a prepositive 8/9 prescaler;
clk is the clock signal output by the 8/9 prescaler;
clk_in is a high-frequency signal of an external input 8/9 prescaler;
dither_en is the enable signal of the pseudo random sequence injected into the MASH1-1-1 Sigma-delta modulator;
fbreset is a forced stop signal of a VCO (voltage controlled oscillator) algorithm control module in the frequency synthesizer to the Ncount frequency division counter, and the forced stop signal resets the Ncount frequency division counter circuit to a reset value of 0.
In fig. 2:
m Counter is a 5-bit Counter;
a Counter is a 3-bit Counter;
input Reg is a register for storing the division ratio N_div [7:0];
aclk is a signal of control A Counter output by M Counter;
fbreset is a forced stop signal of a VCO (voltage controlled oscillator) algorithm control module in the frequency synthesizer for the Ncount frequency division counter, and the forced stop signal resets the M counter and the a counter, and the reset value is 0.
In fig. 3:
m_count is a 5-bit adder for performing +1 operation on an input signal every clock cycle;
clk is the clock input to all registers in FIG. 3;
resetb is the reset signal of all registers in fig. 3, with a reset value of 0;
fbreset is a forced stop signal of a VCO (voltage controlled oscillator) algorithm control module in the frequency synthesizer for the Ncount frequency division counter, and the forced stop signal resets a register div_comp_reg0-4 with a reset value of 0.
Ndiv [7:3] is the frequency division of MASH1-1-1 Sigma-delta modulator 5 bits higher than Ndiv [7:0].
In fig. 4:
clk is the clock input to all registers in FIG. 4;
resetb is the reset signal of all registers in fig. 4, with reset value 0;
a_count is a 3-bit adder for performing +1 operation on an input signal every clock cycle;
ndiv [2:0] is the lower 3 bits of the MASH1-1-1 Sigma-delta modulator divide ratio Ndiv [7:0];
y is an internal control signal generated by the A Counter;
fbreset is a forced stop signal of a VCO (voltage controlled oscillator) algorithm control module in the frequency synthesizer for the Ncount frequency division counter, and the forced stop signal resets a register divcomp_reg0-2 with a reset value of 0.
In fig. 5:
sum2[20], sum3[20] and sum4[20] are the highest bits of the output values of the adders two to four respectively;
sum2[19:0], sum3[19:0] and sum4[19:0] are respectively the low 20 bits of the four output values of the adder two to the adder four;
diff1, diff2[2:0], diff [3:0] are the output values of the highest order of the output values of the adder two, the adder three and the adder four through a noise shaping circuit respectively.
In fig. 6:
dither [19:0] is a pseudo-random sequence output by a pseudo-random sequence generating circuit Dither, wherein, dither [19] to Dither [2] are multiplexing of the output value Dither [1] of the register D_reg1.
Detailed Description
The invention is further described below with reference to the accompanying drawings, taking the 8-bit integer value N_int [7:0] as an integer value of the input fractional-N frequency circuit, and the 20-bit fractional value N_frac [19:0] as an example.
Referring to FIG. 1, a fractional-N frequency divider for a frequency synthesizer according to an embodiment of the present invention includes a MASH1-1-1 Sigma-delta modulator, a frequency division counter circuit Ncount, a pseudo-random sequence generating circuit Dither, an adder I, and a pre-8/9 prescaler.
The input end of the MASH1-1-1 Sigma-delta modulator is respectively connected with the integer value N_int [7:0] and the output end of the adder I, the output end of the MASH1-1 Sigma-delta modulator is connected with the input end of the frequency division counting circuit Ncount, and the enabling end of the MASH1-1-1 Sigma-delta modulator is connected with the enabling signal dither_en of the pseudo-random sequence;
the control signal output end of the frequency division counting circuit Ncount is connected with the front 8/9 prescaler, the control signal frequency division clock output end of the frequency division counting circuit Ncount is simultaneously connected with the clock input end of the MASH1-1-1 Sigma-delta modulator and the clock input end of the pseudo random sequence generating circuit Dither, the clock input end of the frequency division counting circuit Ncount is connected with the clock output end of the front 8/9 prescaler, and the control end of the frequency division counting circuit Ncount is connected with the forced stop signal fbreset;
the output of the pseudo random sequence generating circuit dith is connected with one of the input ends of the adder I.
The other input end of the adder I is respectively connected with the fractional value N_frac [19:0] of the fractional-N frequency dividing circuit.
The working principle of the decimal N-frequency circuit of the invention is as follows:
in each clock period, adding a decimal value N_frac [19:0] and a pseudo-random sequence dither [19:0] by an adder I, sending the result of the adder I into a MASH1-1-1 Sigma-delta modulator, and after the MASH1-1-1 Sigma-delta modulator generates a modulation sequence (namely-3, -2, -1, 0, 1, 2, 3, 4) of-3-4 according to the output result of the adder I, adding the modulation sequence of-3-4 and an integer value N_int [7:0] to generate a frequency division ratio Ndiv [7:0];
the generated frequency division ratio Ndiv [7:0] is sent into a frequency division counting circuit Ncount, and the frequency division counting circuit Ncount counts according to the frequency division ratio Ndiv [7:0] to generate a control signal Mod;
the control signal Mod controls the preposed 8/9 prescaler to carry out 8 frequency division or 9 frequency division, and carries out counting frequency division again on the frequency signal clk input into the frequency division counting circuit Ncount to obtain the expected signal frequency; due to the limitations of the digital circuit itself, the fractional-N frequency dividing circuit performs integer frequency division at each instant, and performs fractional frequency division in a statistical sense within one frequency division period.
As shown in fig. 2, the frequency division counting circuit Ncount mainly comprises a 5-bit counter M counter and a 3-bit counter a counter, when the register Input Reg obtains an 8-bit frequency division ratio Ndiv [7:0], the lower 3-bit Ndiv [2:0] of the frequency division ratio Ndiv [7:0] is Input into the 3-bit counter a counter, the upper 5-bit Ndiv [7:3] is Input into the 5-bit counter M counter, and the control signal Mod is set to 1, so that the pre-8/9 prescaler first works in a 9-frequency division mode, and the 5-bit counter M counter and the 3-bit counter a counter start counting the output frequency clk_in of the phase-locked loop at the same time; because the full range of the 5-bit counter M counter is larger than that of the 3-bit counter A counter, the 3-bit counter A counter counts to the full range first, a control signal Mod is set to 0 through the function of a full range identification circuit, a pre-8/9 prescaler is controlled to divide 8, when the 5-bit counter M counter counts to the full range state, a clock signal Outclk with one period is output, and the M counter and the A counter are set to wait for a new frequency division.
FIG. 3 shows a circuit of a 5-bit counter M counter, wherein M_count is a 5-bit adder, and the M_count is output to an input value +1 in each clock cycle; clock inputs of all registers are clk, reset signals of the registers Comp_reg0-4 and Fb_reg are resetb, and the registers are low in effectiveness, and reset value is 0; in a round of counting period, after the high 5 bits N_div [7:3] of the frequency division ratio N_div [7:0] are obtained, the 5 bits adder M_count starts counting, the output values of the registers div_comp_reg0-4 and the output values of the registers Comp_reg0-4 are respectively compared through the full range identification circuit 301, when the output values are consistent, the fact that the M Counter counts to the full range is indicated, aclk outputs to be 1, setting operation is carried out on the registers div_comp_reg0-4, and the setting value is 2; in the figure 302, when aclk output is 1, the pulse generation circuit outputs, at the time of the next rising edge of the clock, the out clk at a high level for four clock cycles, and then outputs at a low level until the next aclk=1 appears, and the out clk is used as the final output frequency signal of the whole fractional-N frequency circuit.
FIG. 4 shows a 3-bit Counter A Counter circuit, wherein A_count is a 3-bit adder for performing +1 operations on the input signal every clock cycle; the clock inputs and reset signals of all registers are clk and resetb, and the reset value is 0. In one round of counting period, after the frequency division ratio N_div [7:0] is lower by 3 bits N_div [2:0], the adder A_count starts to count, the output value of the register Divcomp_reg0-2 is compared with the output value of the register Comp_reg0-2 through the full range identification circuit 401, and when the output value of the register Divcomp_reg0-2 is equal to the output value of the register Comp_reg0-2, the value of y outputs 1 and Mod outputs 0; or the 0 state judging circuit 402 compares the 0 value with the output values of the registers divcomp_reg0-2 respectively, when the values are equal, the y value outputs 1, the mod outputs 0, the 3-bit Counter A Counter stops counting, after waiting for the 5-bit Counter M Counter to reach the full range, the aclk output is 1, the A Counter is cleared, and at the moment, the next frequency division ratio is loaded into the frequency division counting circuit Ncounter to perform the next frequency division counting.
Mod is 1, the front 8/9 prescaler is controlled to divide 9, mod is 0, and the front 8/9 prescaler is controlled to divide 8.
In one counting cycle, the total of M divided by 9 and a divided by 8 are counted, so that the frequency division ratio obtained finally is ndiv=8m+a. The value of the M counter is 2-31, and the value of the A counter is 0-7, so that the obtained frequency division ratio is calculated as follows: 16 (2X 8) to 255 (31X 8+7).
FIG. 5 shows a MASH1-1-1 Sigma-delta modulator circuit, wherein the input clocks of all registers are the final output frequency signal Outclk of the fractional-N frequency circuit, the reset inputs are resetb, and the reset value is 0. In order to facilitate the comparison experiment, a pseudo-random sequence enabling control signal dither_en is added, when a decimal value N_frac [19:0] is input, if the enabling signal dither_en is 0, the input decimal value N_frac [19:0] is directly injected into an adder II to start accumulation, when the enabling signal dither_en is 1, a pseudo-random sequence generating circuit Dither generates a pseudo-random sequence Dither [19:0], and the input decimal value N_frac [19:0] are summed in the adder I, and the summation result of the adder I is fed into the adder II; the second adder and the third adder, the fourth adder and3 20-bit registers (namely, the registers 20-bit Reg-2, 20-bit Reg-3 and 20-bit Reg-4) form a pipeline adder, after each adder sums once, sum2[19:0], sum3[19:0] and sum4[19:0] are respectively sent into 20-bit registers 20-bit Reg-2, 20-bit Reg-3 and 20-bit Reg-4 to delay for one clock period, and then the highest bits of sum2[19:0], sum3[19:0] and sum4[19:0] are respectively connected with 0 to form 21-bit data, and then the 21-bit data are respectively sent into the second adder, the third adder and the fourth adder to form an accumulator, and sum2[20], sum3[20] and sum4[20] are input into a noise shaping circuit 501; the noise shaping circuit includes a three-stage noise shaping unit: the first stage noise shaping unit is composed of a register diff1_reg1 and a register diff1_reg0; the second stage noise shaping unit is composed of a register diff2_reg1, a register diff2_reg0, two-input NAND gates nand1 and nand2, a two-input OR gate 1 and an NOT gate inv 2; the third stage noise shaping unit is composed of registers diff3_reg0-2, two-input NAND gates nand3-6, NOT gates inv3, inv4, inv6, inv7, two-input OR gate 2-3, two-input exclusive-OR gate xor1, xor3, xor4, and two-input NOR gate nor 1.
The sum2[20] generates diff1 after passing through the first-stage noise shaping unit and is used as the carry bit of the adder five; sum3[20] generates diff2[1:0] through a second-stage noise shaping unit, and expands the lower-order unchanged highest bit into A5[7:0] as the input of an adder five; sum4[20] generates diff3[2:0] through a third-stage noise shaping unit, and expands the lowest two unchanged highest bits of the diff3[2:0] into B5[7:0] to serve as the input of an adder five; summing diff1, A5[7:0] and B5[7:0] through an adder to obtain a modulation sequence sum5[7:0] of-3-4;
the expansion mode is as follows:
A5[7:0]＝{diff2[1],diff2[1],diff2[1],diff2[1],diff2[1],diff2[1],diff2[1],diff2[0]}
B5[7:0]＝{diff3[2],diff3[2],diff3[2],diff3[2],diff3[2],diff3[2],diff3[1],diff3[0]}
the adder six is used for summing the input integer value N_int [7:0] and the obtained modulation sequence sum5[7:0] to obtain the frequency division ratio Ndiv [7:0] input into the frequency division counting circuit Ncount.
Fig. 6 is a pseudo random sequence generating circuit Dither including an m-sequence generating circuit 601 and an output sequence generating circuit 602; the characteristic polynomial of the m-sequence corresponding to the m-sequence generating circuit 601 is:
f(x)＝1+x+x 18 +x 23 +x 24
the output sequence generation circuit 602 is essentially a modification of the m-sequence output.
In the pseudo-random sequence generating circuit dith, the input clocks of all registers are Outclk, the reset signal is resetb, and the values of the registers reg0 to reg23 during reset are: "0100_1110_1011_0101_0111_1011", D_reg0, D_reg1 reset are both 0; the outputs of the registers reg0, reg3 and reg6 are deformed by an output sequence generating circuit to be used as the outputs of a pseudo random sequence generating circuit Dither, and when the outputs of the registers reg0, reg3 and reg6 are all 0, dither [1:0] =0; when one of the outputs of registers reg0, reg3, reg6 is 1, dither [1:0] =1; when there are two 1 in the registers reg0, reg3, reg6 outputs, dither [1:0] = -2; when there are three 1's in the registers reg0, reg3, reg6 outputs, dither [1:0] = -1.
The invention eliminates the principle of parasitic structure of MASH1-1-1 Sigma-delta modulator:
a pseudo-random sequence is added to the decimal input part of the MASH1-1-1 Sigma-delta modulator in each clock period, so that the inherent period of the output sequence of the MASH1-1-1 Sigma-delta modulator is broken, the pseudo-random sequence with extremely short output period of the MASH1-1-1 Sigma-delta modulator is avoided, and structural parasitism is eliminated. Preferably, a pseudo-random sequence with an average value of 0 in the frequency division period is added (the average value is obtained by summing n-bit pseudo-random sequences corresponding to all clock periods in the frequency division period and dividing the sum by the number of clock periods), but if the period of the generated pseudo-random sequence is long enough, the average value of the generated pseudo-random sequence in one frequency division period is small enough, and the influence on the whole circuit is not great.
Simulation control verifies:
for a MASH1-1-1 Sigma-delta modulator without pseudo random sequence, modeling simulation results in ADS (Advanced Design System) software are shown in FIG. 7, and it can be seen that when the input value is 0.25 (corresponding to graph (a)), 0.75 (corresponding to graph (b)), the frequency spectrum at a fixed frequency point is very high, and the output sequence of the modulator has obvious periodicity; at an input value of 0.4637 (corresponding to fig. (c)), a large amount of glitches still exist, although the output sequence of the modulator has good randomness.
As shown in FIG. 8, the simulation result of the MASH1-1-1 Sigma-delta modulator added with the pseudo-random sequence in the ADS shows that the output sequence of the MASH1-1 modulator after the pseudo-random sequence is injected has good randomness if the output period of the previous modulation sequence is too short; if the output sequence with good randomness is provided, the burr of the output sequence frequency spectrum can be effectively restrained after the pseudo-random sequence is added, the output sequence of the modulator can be smoother, and the average value of the output sequence of the MASH1-1-1 Sigma-delta modulator in one frequency division period is not changed after the pseudo-random sequence is added, so that the output result of the whole circuit is not influenced.
As can be seen from the values at (c) m1 in fig. 7 and (c) m1 in fig. 8, the low frequency quantization noise of the output sequence of the MASH1-1-1 Sigma-delta modulator after adding the pseudo random sequence is increased by about 5dB compared with that before adding the pseudo random sequence, and the influence on the output result of the whole circuit is small.

Claims (4)

1. A fractional-N frequency dividing circuit applied to a frequency synthesizer comprises a MASH1-1-1 Sigma-delta modulator, a frequency dividing counting circuit Ncount and a prepositive P/(P+1) prescaler; the method is characterized in that:
the device also comprises a pseudo-random sequence generating circuit Dither and an n-bit adder I;
the pseudo-random sequence generating circuit Dither is used for generating an n-bit pseudo-random sequence and sending the n-bit pseudo-random sequence to the n-bit adder I;
the N-bit adder I is used for summing the decimal value N_frac [ N-1:0] received by the decimal N frequency dividing circuit and the N-bit pseudorandom sequence in each clock period, and sending the summation result corresponding to each clock period to the decimal input end of the MASH1-1-1 Sigma-delta modulator;
the pseudo-random sequence generating circuit Dither comprises an m-sequence generating circuit and an output sequence generating circuit;
the m-sequence generating circuit comprises 3 two-input exclusive-OR gates xor 1-xor 3 and 24 registers reg 0-reg 23 connected in series;
wherein:
the input ends of the two input exclusive-OR gates xor3 are respectively connected with the output ends Q of registers reg22 and reg23;
the input ends of the two input exclusive-OR gates xor2 are respectively connected with the output ends Q of registers reg0 and reg 17;
the input ends of the two-input exclusive-OR gate xor1 are respectively connected with the output ends of the two-input exclusive-OR gate xor3 and the two-input exclusive-OR gate xor 2; the output end of the two-input exclusive-OR gate xor1 is connected with the input end D of the register reg 0;
the output sequence generating circuit comprises two-input exclusive-or gates xor4 and xor5, two-input AND gates and1 and2, two-input OR gate 1 and registers D_reg0 and D_reg1;
two input ends of the two-input exclusive-OR gate xor4 are respectively connected with output ends Q of registers reg0 and reg 3;
two input ends of the two-input exclusive-OR gate xor5 are respectively connected with the output ends of the two-input exclusive-OR gate xor4
An output terminal Q of the register reg 6;
two input ends of the two-input AND gate and1 are respectively connected with the output ends Q of registers reg0 and reg 3;
two input ends of the two-input AND gate and2 are respectively connected with the output ends of the two-input exclusive-OR gate xor4
An output terminal Q of the register reg 6;
the two input ends of the two-input OR gate 1 are respectively connected with the output ends of the two-input AND gate and1 and the two-input AND gate and 2;
the input end of the register D_reg0 is connected with the output ends of the two-input exclusive-OR gate xor5, and the output of the register D_reg0 is dither [0];
the input end of the register D_reg1 is connected with the output ends of two input OR gates 1, and the output end of the register D_reg0 is dither [1];
during resetting, the values of registers reg 0-reg 23 are as follows: 0100_1110_1011_0101_0111_1011.
2. The fractional-N frequency divider circuit for use in a frequency synthesizer as recited in claim 1, wherein: the n-bit pseudo-random sequence has an average value of 0 in one division period.
3. A fractional-N frequency division method applied to a frequency synthesizer based on the fractional-N frequency division circuit applied to a frequency synthesizer according to claim 1 or2, characterized by:
1) Summing the decimal value N_frac [ N-1:0] received by the decimal N frequency dividing circuit with the N-bit pseudorandom sequence in each clock cycle;
2) Generating a modulation sequence of-3-4 by the MASH1-1-1 Sigma-delta modulator according to the summation result of the step 1), and adding the modulation sequence of-3-4 to the integer value received by the fractional-N frequency dividing circuit so as to generate a frequency dividing ratio;
3) The frequency division counting circuit Ncount divides the output signal clk of the pre-P/(P+1) prescaler according to the frequency division ratio to generate a control signal Mod and an expected frequency signal Outclk; the control signal Mod is used for controlling the pre-P/(P+1) prescaler to carry out P frequency division or P+1 frequency division, when the control signal Mod is 1, the pre-P/(P+1) prescaler carries out P+1 frequency division, and when the control signal Mod is 0, the pre-P/(P+1) prescaler carries out P frequency division.
4. A fractional-N frequency division method applied to a frequency synthesizer as claimed in claim 3, characterized by: in the step 1), the average value of the n-bit pseudo random sequence in a frequency division period is 0.
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