CN112134561B - Narrow-band frequency modulation digital precision frequency synthesizer - Google Patents
Narrow-band frequency modulation digital precision frequency synthesizer Download PDFInfo
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- 238000012986 modification Methods 0.000 description 1
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- 238000005070 sampling Methods 0.000 description 1
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
A narrow-band frequency modulation digital precision frequency synthesizer relates to the technical field of frequency modulation broadcasting, and aims to solve the problem that the existing narrow-band frequency modulation method cannot meet the frequency resolution requirement of frequency modulation broadcasting programs; when the DMA controller receives the DRQ request signal, the DMA controller obtains one data from the frequency division value sequence in the memory and transmits the data to the register; the output frequency of the system clock is a fixed value, and a counter is adopted for counting; the comparator compares the numerical values output by the counter and the register, and when the two numerical values are unequal, the comparator outputs a low level; when the two values are equal, the comparator outputs a high level, a signal is output outwards, a zero clearing signal is sent to the counter, and a DRQ request signal is sent to the DMA controller; the precise frequency signal is output to the outside of the synthesizer at the output end.
Description
Technical Field
The invention relates to the technical field of frequency modulation broadcasting, in particular to a narrow-band frequency modulation digital precision frequency synthesizer.
Background
When designing a digital electronic system, a method of frequency division of a high-frequency clock of the system is often adopted to generate a specified frequency signal, for example, a timer in a singlechip is used for carrying out N frequency division on a system clock with frequency of F, so that frequency F1=F/N can be generated; if n+1 frequency division is performed, frequency f2=f/(n+1) is generated; however, this approach does not produce frequencies between F1 and F2. And as the output frequency increases, the frequency division value N correspondingly decreases, resulting in a significant increase in the interval between the steps of the two frequencies F1 and F2, and poorer frequency resolution for higher frequencies.
The standard GB/T4311-2000 of frequency modulation broadcasting in China prescribes that frequency modulation is adopted for frequency modulation, and the frequency deviation is +/-75 KHz under the modulation degree of 100%. The digitized voice voltage data is required to be converted into analog quantity by D/A conversion according to the conventional modulation mode, and then modulated by a voltage-controlled oscillator. This approach not only has more circuit elements and is more distorted and noisy. When multiple analog modulation circuits are mounted close together, crosstalk between different programs can also result due to frequency occupancy. The method comprises the steps of modulating multiple programs to several lower intermediate frequency signals respectively by a singlechip, and performing secondary modulation and transmission by a later-stage circuit (adopting the prior art). The circuit has less circuit elements and more modulation channels, the circuit is free from debugging, and crosstalk among the channels is avoided.
Each voltage value of the fm broadcast sound signal corresponds to a frequency, i.e., a linear V/F conversion. Therefore, the design goal is to output square waves by the singlechip, so that different frequencies are correspondingly output by different sound data. Specifically, a singlechip design with the model of STM32F407 is adopted, a timer is utilized to output square waves, and integer frequency division is only needed to be carried out by setting a reload register ARR. The traditional frequency division mode increases with the output frequency, the frequency stepping interval of frequency division is larger and larger, and the frequency resolution requirement of the frequency modulation broadcast program can not be met. For example, the singlechip divides the frequency of the 168MHz main clock in the turnover mode, and can output 1MHz square wave when the frequency division value is equal to 84; when the frequency division value is 83, the output square wave frequency is 1.012MHz; however, the frequency resolution required for an 8-bit sound signal must be less than 0.586KHz, and the performance must be improved by at least a factor of 20 to meet the requirements.
Disclosure of Invention
The invention provides a narrow-band frequency modulation digital precise frequency synthesizer for solving the problem that the conventional narrow-band frequency modulation method cannot meet the frequency resolution requirement of frequency modulation broadcast programs.
The narrow-band frequency modulation digital precision frequency synthesizer is realized by a singlechip and specifically comprises a timer consisting of a system clock, a counter, a register and a comparator, a D trigger, an output end, a DMA controller, a memory, a computing unit and an input end; the frequency value is input from the input end, calculated by the calculating unit, a frequency division value sequence is obtained, and the frequency division value sequence is stored in the memory;
when the DMA controller receives the DRQ request signal each time, acquiring one data from the frequency division value sequence in the memory, and transmitting the data to the register;
the output frequency of the system clock is a fixed value, and a counter is adopted for counting; the comparator compares the numerical values output by the counter and the register, and when the two numerical values are unequal, the comparator outputs a low level; when the two values are equal, the comparator outputs high level, and sends a rising edge signal to the clock input end of the D trigger, and simultaneously sends a zero clearing signal to the counter and sends a DRQ request signal to the DMA controller; the input end of the D trigger is connected with the Q-bar output end, and the input end of the D trigger is connected with the output end, so that the precise frequency signal is output to the outside of the synthesizer at the output end.
The invention has the beneficial effects that:
the invention adopts DMA of the singlechip to drive the timer, and the frequency modulation generates square wave signals with sufficient precision for the modulation of broadcast programs.
The V/F converter designed by the singlechip has higher response speed, and the new frequency takes effect immediately as long as the DMA sends the new frequency division value to the timer. The maximum delay time is thus one overflow period of the timer.
The synthesizer can continuously output square waves with higher frequency precision, and breaks through the frequency interval limitation of frequency division of the traditional timer. The timer supporting DMA function in STM32F4 serial SCM is utilized, after software setting, the timer can continuously and stably output fixed precise frequency without software intervention, and in the multichannel FM broadcasting digital modulation circuit designed by the technology, the timer has the advantages of simple circuit, small volume and no debugging, and all programs are well isolated and can not be mutually crosstalked. The device model machine has good effect after actual trial.
Drawings
FIG. 1 is a schematic diagram of a narrow-band FM digital precision frequency synthesizer according to the present invention;
FIG. 2 is a schematic diagram of the narrow-band FM digital precision frequency synthesizer according to the present invention;
FIG. 3 is a flow chart of a calculation unit in the narrow-band FM digital precision frequency synthesizer according to the present invention;
fig. 4 is a frequency division schematic diagram of the narrow-band fm digital precision frequency synthesizer according to the present invention.
Detailed Description
Referring to fig. 1 to 4, the present embodiment is described as a narrow-band fm digital precision frequency synthesizer, which is implemented by a single-chip microcomputer, wherein the single-chip microcomputer includes a system clock 1, a counter 2, a register 3, a comparator 4, a d flip-flop 5, an output terminal 6, a dma controller 7, a memory 8, a calculation unit 9, and an input terminal 10; the output frequency of the system clock 1 is a fixed value, and the counter 2 is used for counting;
the counter 2 outputs a value, and the value in the register 3 is compared by the comparator 4, and when the two are not equal, the comparator outputs a low level; when the counter 2 outputs a value equal to the value in the register 3, the comparator 4 outputs a high level, sends a rising edge signal to the clock input end of the D flip-flop 5, simultaneously sends a clear signal to the counter 2, and simultaneously sends a DRQ request signal to the DMA controller 7;
the D input end of the D trigger 5 is connected with the Q-bar output end, so that the rising edge of each clock input can turn over the D trigger 5;
the Q input end of the D trigger 5 is connected with the output end 6, so that a precise frequency signal is output to the outside of the device at the output end 6;
the output frequency value is input from an input end 10, is calculated by a calculation unit 9 to obtain a frequency division value sequence, and is stored in a memory 8; if the output frequency is required to be fixed, the sequence of division values stored in the memory 8 need only be calculated once and is not changed; if a change in the output frequency is required, each frequency change requires a change in the sequence of divider values stored in the memory 8;
the DMA controller 7 obtains a data from the frequency division value sequence in the memory 8 and transmits the data to the register 3 each time the DRQ request signal is received; the DMA controller 7 is provided with a DMA address register, the DMA controller is set to work in a circulation mode, the starting address of the DMA is the first address of the frequency division value sequence in the memory 8, and the ending address of the DMA is the last address of the frequency division value sequence in the memory 8; each DRQ request signal transmits one data, and the DMA address is added with 1 after the transmission is completed, and when the accumulation of the DMA address register reaches the end address of the DMA, the DMA address register can automatically restore to be the starting address of the DMA.
In the present embodiment, when the output frequency value is fixed, the frequency division value sequence stored in the memory 8 is calculated only once and is not changed any more; when the output frequency value changes, each frequency value change requires a change in the sequence of division values stored in the memory 8.
In this embodiment, a DMA address register is set in the DMA controller 7, where the DMA controller is set to operate in a cyclic mode, the start address of the DMA address register is the first address of the frequency division value sequence in the memory 8, and the end address of the DMA address register is the end address of the frequency division value sequence in the memory 8; each DRQ request signal transmits one data, and the DMA address is added with 1 after the transmission is completed, and when the accumulation of the DMA address register reaches the end address of the DMA, the DMA address register automatically restores to be the starting address of the DMA.
In this embodiment, the narrowband frequency modulation principle performed by the narrowband frequency modulation digital precision frequency synthesizer is as follows: modulating a carrier signal with an angle frequency omega by adopting a modulating signal with the angle frequency omega, and outputting a frequency modulation signal when the frequency modulation index is m:
V＝cos(ω+m*sinΩt)t＝cosωt*cos(m*sinΩt)t-sinωt*sin(m*sinΩt)t
if m < <1, cos (m.sin. OMEGA.t) t.apprxeq.1, and sin (m.sin. OMEGA.t) t.apprxeq.m.sin. OMEGA.t
Substituting the above formula to obtain: v.apprxeq.cos ωt+m.cos (ω+Ω) t/2-m.cos (ω - Ω) t/2
Therefore, the narrowband frequency modulation signal V consists of a carrier signal and an upper sideband signal and a lower sideband signal, and the amplitude of the sideband signal is equal to half of the frequency modulation index; if the frequency modulation index m is very small near zero, then the narrowband frequency modulation signal: v.apprxeq.cos ωt. It is generally considered that the maximum instantaneous phase shift caused by the frequency modulation is much smaller than 30 deg., referred to as narrowband frequency modulation.
Fig. 2 and 3 are applicable to embodiments satisfying two different applications, respectively; fig. 2 is applicable to the case where the output frequency needs to be changed, and fig. 3 is applicable to the case where the output frequency is fixed; the design goal in both cases is to reduce the length M of the sequence of division values as much as possible in order to save storage space.
In this embodiment, referring to fig. 2, the narrowband frequency modulation implementation procedure is as follows: the period of the timer may be changed by dynamically setting the overflow upper limit for the next count before each count overflow reloads. The frequency modulation method enables the average frequency of the overall output to be close to the design frequency, and a signal with enough precision is generated.
For example, to generate a signal with a period of T and a frequency f= 1.000586MHz, the timer may generate signals with two frequencies of f1=1 MHz X times and f2=1.012 MHz Y times. As long as L T periods have elapsed, which start and end times can coincide, the average frequency of the synthesized signal with F1 and F2 is equal to F. The two signals with the frequencies of F1 and F2 are staggered and distributed as uniformly as possible, so that the narrow-band frequency modulation is realized. For convenience of design, a design scheme is adopted in which the length m=x+y of the frequency division value sequence is a fixed value in the case that the output frequency needs to be changed.
In the present embodiment, the frequency resolution requirement determines the length M of the frequency division value sequence. If one frequency f1 is synthesized by M T1 and the next frequency f2 is synthesized by M T2, the step difference Δ of two synthesized periods is accumulated M times to reach one period T of the master clock. The method comprises the following steps: t=m (1/f 1-1/f 2), so that the length M of the divided value sequence can be determined in case the output frequency needs to be changed.
Referring to fig. 3, in this embodiment, the input parameters of the design function of the computing unit include three parameters, i.e., a synthesis target frequency, a timer clock frequency, and a length of a frequency division value sequence, and the output parameter is a buffer array corresponding to the frequency, in which the frequency division values for DMA transfer to the ARR register each time are uniformly filled. The specific process is as follows:
step one, inputting a synthesis target frequency and a timer clock frequency, determining the length M of a frequency division value sequence, calculating a numerical value N, and filling all frequency division value sequence buffer areas with the numerical value N; the method comprises the following steps:
storing a frequency division value sequence in a buffer area of the memory 8, and if all data in the frequency division value sequence are N, the cycle of the DRQ signal is T1; if all data in the frequency division value sequence are N+1, the DRQ signal period is T2; for any signal with period T to be output, there is the following proportional relationship:
wherein X is the number of numerical values N in the frequency division value sequence, Y is the number of numerical values equal to N+1 in the frequency division value sequence; after calculating the simplest integer ratio of X and Y, under the condition that the output frequency is fixed, the length M=X+Y of the frequency division value sequence can be obtained; so that for sets of circuit arrangements outputting different frequencies, their M values are different;
storing in a buffer of the memory 8 a frequency division value number which is a frequency division value sequence consisting of two values of N and n+1, the n=timer clock frequency/synthesis target frequency-1;
step two, judging whether the clock frequency value of the timer can be divided by the synthesized target frequency value, if so, executing step three; if not, all the stored frequency division arrays in the buffer area are N, and the operation is exited;
step three, step length K=M/Y; setting a variable i=0;
step four, changing the index of the frequency division array into a value of (i+1) at the position of (i x K), and then adding 1 to the value of i;
step five, judging whether i is equal to Y, if so, exiting to obtain frequency division value data which are arranged in sequence; if not, returning to the fourth step.
In this embodiment, since the numerical range is not so large, the speed is increased by fixed point number calculation. To reduce fixed point calculation errors, multiplication needs to be calculated first, division needs to be calculated last, and care needs to be taken to prevent overflow of possible numerical values in the multiplication calculation process.
In this embodiment, the single chip microcomputer is STM32F407 of STM32F4 series, and the timers have two groups, wherein the timers of TIM1 and TIM8 input high frequency 168MHz clock and support DMA, and the timers of low frequency 84MHz clock input and support DMA have TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7. So that a single chip can modulate 8 sets of programs at the same time at maximum. The synthesis of high frequency requires a longer frequency division buffer, so the timer of the high frequency is selected preferentially to synthesize the high frequency program, and the timer of the low frequency is left to synthesize other low frequency programs.
In order to make the duty ratio of the output square wave be as close as possible to 50%, a pin for setting the output comparison function of the timer works in a turnover mode, at the moment, the pin of the singlechip is connected to the output end of a D trigger in a chip, and the output comparison signal of the timer is connected to the clock end of the D trigger. Because the pin level toggles only once each time the timer overflows, the output frequency is half the timer overflow frequency. This corresponds to a half reduction in the clock frequency of the timer input.
Before the timer overflows and reloads each time, the numerical value in the reloading register is changed in time, and the frequency division is realized by using two values of N or N+1 alternately. Two hardware devices, namely a timer and a DMA (direct memory access) inside the STM32F407 singlechip are needed.
In this embodiment, the timer overflow may be automatically reloaded, and the shadow register function is provided, and the modification of the reload register will not be immediately effective until the next time the timer overflows. This feature ensures that the square wave period of the timer output is not interrupted accidentally and the reload register can be modified at any time. The timer overflows to trigger the DMA, and the DMA is used for modifying the reloading register, so that only software is required to prepare data for the synthesized frequency at one time, the rest work is given to the timer and the DMA hardware, and then the signal with the designated frequency can be continuously output without the intervention of the software, so that the system has high operation efficiency.
In this embodiment, when the timer overflows, an Update event is generated to trigger the DMA controller 7, and care must be taken in the program to start the clocks of the two hardware before any one of the devices is set, or the two hardware may not work in a coordinated manner. Taking the call of the ST firmware library function to set DMA2 and TIM8 as an example:
setting a singlechip with the model STM32F407 according to the following steps, and transmitting a frequency division value sequence to a TIM8 part by using a DMA2_Stream1 part in the singlechip, so that the TIM8 can output a precise frequency signal outwards through a PC7 pin of the singlechip;
step A, initializing a DMA controller 7;
step B, starting the DMA controller 7;
step C, setting the update event of the timer to trigger the DMA controller 7;
step D, setting a pin of an output port PC7 of the timer as an output end 6;
step E, mapping a PC7 pin to the output end of the timer output comparison channel 2;
step F, starting a timer and enabling an output port function of the timer at the same time;
and G, starting a timer to update an event output function.
If the sequence of the steps is incorrect, the timer and the DMA controller cannot work together, and the narrowband frequency modulation function cannot be correctly realized.
In the present embodiment described with reference to fig. 4, each sound voltage value of a program corresponds to a sequence of divided values, and the hardware can automatically output a specified frequency by setting the start address and length of the sequence to DMA. Enumerating all sound voltage values, and storing all corresponding frequency division value sequences in a two-dimensional array. Fig. 4 illustrates the principle of using DMA2_chan7_stream1 in a single chip microcomputer to drive TIM8 to generate fm broadcast if signal with a center frequency of 2000 KHz.
The center frequency 2000KHz corresponds to the sound voltage value 127, and when the sound voltage value is equal to 2, the corresponding frequency is 1926.1719KHz. When the TIM8 overflows each time, the DMA controller sequentially obtains a frequency division data from the array corresponding to the voltage value to update the TIM8- > ARR register, and can output 1926.1719KHz frequency. If the sound voltage changes, other frequency division value sequences are replaced for DMA transmission, and the hardware automatically outputs corresponding frequencies.
Whenever the sound voltage value changes, the corresponding frequency can be synthesized theoretically only by resetting the memory read address of the DMA controller. However, this approach introduces significant phase noise because the DMA adjustment requires temporary interruption of the DMA. Therefore, the DMA buffer is fixed, and the data mode of the buffer is changed. The DMA controller is enabled to continuously transmit data to a timer in a fixed buffer, and when the sound voltage value changes, software copies a new frequency division value sequence to the buffer, so that DMA is not disturbed, and the accuracy and stability of output signals are ensured.
In this embodiment, the upper limit of the output frequency of the narrow-band frequency modulation performed by the practical test STM32F407 single-chip microcomputer is about 7MHz, limited by the timer and DMA hardware in the single-chip microcomputer. If the output frequency is set to be too high, irregular instantaneous interruption of the output square wave occurs. That is, in the system, the singlechip is not limited by the traditional integral frequency division, and can output any frequency lower than 7MHz.
In the synthesizer according to the present embodiment, the main noise in the narrowband fm output signal is the upper and lower side frequency signals, and the side frequency amplitude can be very small as long as the frequency modulation index is sufficiently small. If the number of N frequency divisions is equal to the number of n+1 frequency divisions, the amplitude of the side frequency reaches a maximum value, and the frequency modulation index m can be calculated:
m＝1/(2N+1)
therefore, when outputting a fm broadcast intermediate frequency signal having a center frequency around 2MHz, the N value is 42, and thus the worst case can be calculated as: there are upper and lower side frequency signals of 24KHz higher or lower than the output signal, the amplitude of which is 0.6% of the total amplitude of the output signal; can be ignored when used as a broadcast modulator.
The analog V/F conversion circuit generally adopts an integrating circuit with deep negative feedback, so that the accuracy is high, but the accuracy of one actual circuit is not easy to analyze. The conversion accuracy designed by the singlechip can be directly calculated.
When the crystal clock accuracy is sufficiently high, the frequency accuracy of the digital V/F conversion output is determined by the frequency resolution. The longer the frequency division buffer, the higher the frequency resolution. However, when the frequency-division buffer is used for a broadcast modulator with an intermediate frequency of 2MHz, the time interval between two adjacent data is 62.5us because of inputting a sound sampling voltage signal with the frequency of 16KHz, and 125 periods with the frequency of 2MHz can be accommodated, so that the length of the frequency-division buffer exceeds 125, and the meaning is lost. The actual system designs frequency data corresponding to all voltages with the frequency division buffer zone length of 96, and can see that the error is largest at the design frequency of 2.030469MHz, the actual synthesized frequency is 2.030723MHz, and the relative error is 0.0125%.
Namely: if the output frequency is F, the length M of the frequency division value sequence is the shortest limit period G=M/F for frequency dynamic adjustment; the period of the frequency dynamic adjustment must be greater than the shortest limit period; this problem need not be considered if the frequency-fixed output is not dynamically adjusted. If the dynamics are forced to take a period shorter than G, the accuracy of the output frequency will be degraded, and the design requirement for the original calculated frequency division value sequence with length M will not be met.
The V/F converter designed by the singlechip is high in response speed, and the new frequency takes effect immediately as long as the DMA sends the new frequency division value to the timer. The maximum delay time is thus one overflow period of the timer.
According to the implementation mode, software intervention is not needed after setting, square waves with higher frequency precision can be continuously output, and the frequency interval limit of frequency division of the traditional timer is broken through. STM32F4 series singlechip has a plurality of timers, still supports complicated DMA function, can realize some functions that need not software intervention and just can work automatically. In the multichannel FM broadcasting digital modulation circuit designed by the technology, because of no analog circuit link, the multichannel FM broadcasting digital modulation circuit has the advantages of simple circuit, small volume and no debugging, and all programs are well isolated and can not cross each other. The device model machine has good effect after actual trial.
Claims (5)
1. The narrow-band frequency modulation digital precision frequency synthesis device is realized by a singlechip and specifically comprises a timer consisting of a system clock (1), a counter (2), a register (3) and a comparator (4), a D trigger (5), an output end (6), a DMA controller (7), a memory (8), a calculation unit (9) and an input end (10); the method is characterized in that:
the frequency value is input from an input end (10), calculated by a calculating unit (9) to obtain a frequency division value sequence, and stored in a memory (8);
each time the DMA controller (7) receives a DRQ request signal, acquiring one data from the frequency division value sequence in the memory (8) and transmitting the data to the register (3);
the output frequency of the system clock (1) is a fixed value, and a counter (2) is adopted for counting; the comparator (4) compares the values output by the counter (2) and the register (3), and when the two values are unequal, the comparator (4) outputs a low level; when the two values are equal, the comparator (4) outputs a high level, sends a rising edge signal to the clock input end of the D trigger (5), simultaneously sends a zero clearing signal to the counter (2), and sends a DRQ request signal to the DMA controller (7);
the input end of the D trigger (5) is connected with the Q inverse output end, and the Q input end of the D trigger (5) is connected with the output end (6) to realize that a precise frequency signal is output to the outside of the synthesis device at the output end (6);
the calculating unit (9) calculates the frequency value, and the process of obtaining the frequency division value sequence is as follows:
step one, inputting a synthesis target frequency and a timer clock frequency, determining the length M of a frequency division value sequence, calculating a numerical value N, and filling all frequency division value sequence buffer areas with the numerical value N; the method comprises the following steps:
storing a frequency division value sequence in a buffer area of the memory (8), and if all data in the frequency division value sequence are N, setting the cycle of the DRQ signal as T1; if all data in the frequency division value sequence are N+1, the DRQ signal period is T2; for any signal with period T to be output, there is the following proportional relationship:
wherein X is the number of numerical values N in the frequency division value sequence, Y is the number of numerical values equal to N+1 in the frequency division value sequence; after calculating the simplest integer ratio of X and Y, obtaining the length m=x+y of the frequency division value sequence;
storing a frequency division value sequence consisting of two values of N and N+1 in a buffer area of the memory (8), wherein N=timer clock frequency/synthesis target frequency-1;
step two, judging whether the clock frequency value of the timer can be divided by the synthesized target frequency value, if so, executing step three; if not, all the stored frequency division arrays in the buffer area are N, and the operation is exited;
step three, step length K=M/Y; setting a variable i=0;
step four, changing the index of the frequency division array into a value of n+1 at the position of i x K, and then adding 1 to the value of i;
step five, judging whether i is equal to Y, if so, exiting to obtain frequency division value data which are arranged in sequence; if not, returning to the fourth step.
2. The narrow-band fm digital precision frequency synthesizer according to claim 1, wherein:
when the output frequency value is fixed, the frequency division value sequence stored in the memory (8) is only calculated once and is not changed any more; when the output frequency value is changed, each frequency value change requires a change in the sequence of division values stored in the memory (8).
3. The narrow-band fm digital precision frequency synthesizer according to claim 1, wherein: the DMA controller (7) is internally provided with a DMA address register, the DMA controller is set to work in a circulation mode, the initial address of the DMA address register is the first address of the frequency division value sequence in the memory (8), and the end address of the DMA address register is the end address of the frequency division value sequence in the memory (8); each DRQ request signal transmits one data, and the DMA address is added with 1 after the transmission is completed, and when the accumulation of the DMA address register reaches the end address of the DMA, the DMA address register automatically restores to be the starting address of the DMA.
4. The narrow-band fm digital precision frequency synthesizer according to claim 1, wherein: triggering a DMA controller (7) by adopting timer overflow, reloading a register (3) by adopting the DMA controller (7), and realizing frequency modulation by adopting a method of dynamically changing the next overflow time of the timer by using DMA; the timer triggers the DMA controller (7) as follows;
step A, initializing a DMA controller (7);
step B, starting a DMA controller (7);
step C, setting a DMA controller (7) triggered by an update event of the timer;
step D, setting a pin of an output port PC7 of the timer as an output end (6);
step E, mapping the PC7 pin to the output end of the timer output comparison channel;
step F, starting a timer and enabling an output port function of the timer at the same time;
and G, starting a timer to update an event output function.
5. The narrow-band fm digital precision frequency synthesizer according to claim 1, wherein: if the output frequency is F and the length M of the frequency division value sequence is set, there is a shortest limit period g=m/F for frequency dynamic adjustment, and the period for frequency dynamic adjustment must be greater than the shortest limit period.
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| CN110190847A (en) * | 2019-04-26 | 2019-08-30 | 西安邮电大学 | A kind of fractional-N divide circuit and method applied to frequency synthesizer |
| CN111490839A (en) * | 2020-04-20 | 2020-08-04 | 吉林省广播电视研究所(吉林省广播电视局科技信息中心) | Frequency modulation broadcasting frequency measurement demodulation electronic system |
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| CN110190847A (en) * | 2019-04-26 | 2019-08-30 | 西安邮电大学 | A kind of fractional-N divide circuit and method applied to frequency synthesizer |
| CN111490839A (en) * | 2020-04-20 | 2020-08-04 | 吉林省广播电视研究所(吉林省广播电视局科技信息中心) | Frequency modulation broadcasting frequency measurement demodulation electronic system |
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