WO2020041967A1

WO2020041967A1 - Phase locked loop circuit and device using same

Info

Publication number: WO2020041967A1
Application number: PCT/CN2018/102654
Authority: WO
Inventors: 简思平; 曹炜; 李光明; 俞波
Original assignee: 华为技术有限公司
Priority date: 2018-08-28
Filing date: 2018-08-28
Publication date: 2020-03-05
Also published as: CN111837339A; CN111837339B

Abstract

A phase locked loop circuit, relating to the field of digital circuits and used for tracking and generating a clock signal. The phase locked loop circuit comprises a reference phase generating circuit and a clock signal generating circuit of which target frequencies are equal. The reference phase generating circuit generates a second reference phase signal according to a first reference phase signal, and the clock signal generating circuit generates an output clock signal according to the second reference phase signal, phase differences among the first reference phase signal, the second reference phase signal, and the output clock signal being 0. Because there is no feedback branch between the reference phase generating circuit and the clock signal generating circuit, stray and jitter in the clock signal generating circuit will not be feed back to the reference phase generating circuit. Therefore, the overall performance of the phase locked loop circuit is improved and the precision of the output clock signal is improved.

Description

Phase-locked loop circuit and equipment using same

Technical field

The present application relates to the technical field of electronic circuits, and in particular, to frequency phase tracking control technology.

Background technique

Phase-locked loop (PLL) technology is widely used in electronic circuits in the fields of communications, radar, aerospace, measurement, television, and control. In integrated circuits, especially in high-speed and high-performance integrated circuits, phase-locked loop technology is particularly important. For example: use a phase-locked loop to provide a high-speed ADC / DAC (Analog, Digital Converter, Digital Analog Converter) with a low-jitter (Jitter) clock, or use a phase-locked loop to send and receive communications. The upper and lower mixers of the transceiver provide low phase noise and small spurious carrier signals. In addition, in a high-speed communication link, the PLL can be set in an optical network communication chip or a modern high-speed Serdes (serial deserialization) chip for clock extraction and clock synchronization.

At present, most phase-locked loops use inner and outer loop structures, including inner-loop PLL circuits and outer-loop PLL circuits. The outer loop PLL circuit provides a reference phase signal for the inner loop PLL circuit, and the inner loop PLL circuit generates an output clock by using the reference phase signal provided by the outer loop PLL circuit. The inner loop PLL circuit is usually a digital-to-analog hybrid PLL, and its loop bandwidth is wider to obtain lower phase noise and jitter. The bandwidth of the outer loop PLL circuit is narrow, and the frequency accuracy of the reference phase signal output by the outer loop PLL circuit is high. In actual work, the inner loop PLL circuit will produce more spurs and other bad factors, and the feedback loop will pass the bad factors such as spurs to the outer loop PLL circuit. The spurs conduct each other in the outer loop PLL circuit and the inner loop PLL circuit, so that the overall performance of the phase locked loop is degraded, resulting in a decrease in the accuracy of the output clock signal.

Summary of the Invention

The embodiments of the present application provide a phase-locked loop circuit, which can solve the problems of spur conduction in the phase-locked loop circuit, the degradation of the overall performance of the phase-locked loop, and the accuracy of the output clock signal to a certain extent.

According to a first aspect, an embodiment of the present application provides a phase-locked loop circuit for generating an output clock signal. The phase-locked loop circuit includes a reference phase generation circuit and a clock signal generation circuit. The reference phase generation circuit includes A first phase detector, a first loop filter, a first digital integrator, and a first feedback circuit. The first phase detector is used to receive and compare a first reference phase signal and a first feedback phase signal, and compare the The result is output as a first comparison result to the first loop filter; the first loop filter is used to perform low-pass filtering on the received first comparison result and output to the first digital integrator; the first digital The integrator is configured to generate the second reference phase signal according to the filtered first comparison result; the first feedback circuit is configured to receive the second reference phase signal and output the first reference phase signal to the first phase detector ; The clock signal generating circuit is configured to receive the second reference phase signal and generate the output according to the second reference phase signal Signal; wherein the target frequency and the phase of said reference clock signal generating circuit is equal to a target frequency generating circuit, said first phase reference phase signal, the second reference phase signal and the output clock signal are both 0.

Because the second reference phase signal containing more spurs and clock jitter generated by the output clock generating circuit will not be fed back to the reference phase generating circuit through a feedback loop, the spurs and jitter will not be caused in the reference phase generating circuit and The clock signal generating circuits communicate with each other, thereby reducing clock jitter, improving the accuracy of the above-mentioned output clock signal, and improving the system performance of the phase-locked loop circuit. In addition, since the above-mentioned first digital integrator replaces the traditional voltage-controlled oscillator, the reference phase generating circuit is implemented as a pure digital circuit, which not only ensures the frequency and phase tracking performance of the phase-locked loop circuit, but also reduces the power of the phase-locked loop circuit Consumption and area.

In a possible design, the first digital integrator is configured to control a phase change amount of the second reference phase signal within one clock period according to a first frequency control word, and the first frequency control word is the filtered first A comparison result. The first frequency control word is used to control the second reference phase signal generated by the first digital integrator, so that the second reference phase signal is more accurate and the spurs in the signal are less.

In a possible design, the reference phase generating circuit further includes a second digital integrator, the second digital integrator is configured to generate a first reference phase signal according to a second frequency control word, and the second frequency control word is used to control The phase change amount of the first reference phase signal in one clock cycle. The second frequency control word is used to control the first reference phase signal generated by the second digital integrator, so that the second reference phase signal is more accurate and the spurs in the signal are less.

In a possible design, the first digital integrator includes a first register, and the first register is used to store the first frequency control word; the second digital integrator includes a first register, and the second register is used for The second frequency control word is stored. The frequency of the digital integrator is configured by an internal register, which is beneficial to reduce the circuit area and increase the flexibility of frequency configuration.

In a possible design, the first digital integrator and the second digital integrator are digital accumulators. The digital accumulator is simple to implement, which is conducive to saving hardware resources and reducing circuit area.

In a possible design, the second reference phase signal is a stepped sawtooth wave signal, and the number of steps of the stepped sawtooth wave signal in one period is equal to the first frequency control word, and the stepped frequency of the stepped sawtooth wave It is equal to the frequency of the working clock of the first digital integrator. The ladder sawtooth wave signal can better contain the frequency information in the first digital integrator.

In a possible design, the first reference phase signal is a stepped sawtooth wave signal, and the number of steps of the stepped sawtooth wave signal in one period is equal to the second frequency control word, and the stepped frequency of the stepped sawtooth wave It is equal to the frequency of the working clock of the second digital integrator. The ladder sawtooth wave signal can better contain the frequency information in the second digital integrator.

In a possible design, the reference phase generating circuit further includes a first interpolation circuit, which is configured to synchronize the frequency of the first reference phase signal with the frequency of the second reference phase signal, and synchronize The subsequent first reference phase signal is output to the first phase detector. The first interpolation circuit synchronizes the above-mentioned first reference phase signal, so that the first phase detector can compare the received signals in the same clock domain.

In a possible design, the reference phase generating circuit further includes a second interpolation circuit and a third interpolation circuit, wherein the second interpolation circuit is configured to compare the frequency of the filtered first comparison result with the second reference The frequency of the phase signal is synchronized, and the synchronized first filtered result is output to the first digital integrator; the first feedback circuit includes a third interpolation circuit, and the third interpolation circuit is configured to use the second reference The frequency of the phase signal is synchronized with the frequency of the first reference phase signal, and the synchronized second reference phase signal is fed back to the first phase detector. The second interpolation circuit and the third interpolation circuit respectively synchronize the received phase signals, so that the first phase detector and the second phase detector can compare the received signals in the same clock domain. In addition, because the third interpolation circuit synchronizes the high-frequency phase signal to the low-frequency phase signal, the first phase detector can perform phase comparison in the low-frequency frequency domain, further saving hardware resources.

In a possible design, the first interpolation circuit, the second interpolation circuit, and the third interpolation circuit are linear interpolation circuits. The structure of the linear interpolation circuit is relatively simple, which can save hardware resources and reduce power consumption.

In a possible design, the reference phase generating circuit further includes a low-pass filter, which is configured to perform low-pass filtering on the first comparison result output by the first phase detector, and perform low-pass filtering The first comparison result of is output to the above-mentioned first loop filter.

In one possible design, the above-mentioned low-pass filter is an infinite impulse response filter IIR. Infinite impulse response filter IIR can low-pass filter the signal and improve the filtering performance.

In a possible design, the clock signal generating circuit includes a second phase detector, a second loop filter, a voltage controlled oscillator, and a second feedback circuit, wherein the second phase detector is configured to receive the second phase detector The reference phase signal and the second feedback phase signal are used to calculate a phase difference and output the phase difference to the second loop filter; the second loop filter is configured to receive the phase difference, perform low-pass filtering on the phase difference, and output the filtered phase A differential to voltage-controlled oscillator; the voltage-controlled oscillator is configured to receive the filtered phase difference and generate an output clock signal according to the filtered phase difference; and the second feedback circuit is configured to output the output from the voltage-controlled oscillator The clock signal is converted into a second feedback phase signal, and the second feedback phase signal is output to the second phase detector. The clock signal generating circuit tracks the second reference phase signal, aligns the phase of the generated output clock signal with the phase of the second reference phase signal, thereby aligns the phase of the output clock signal with the first reference phase signal, and realizes the output clock signal. Purpose of alignment with the phase of the input first reference phase signal.

In a possible design, the target frequency of the reference phase generating circuit f _t1 = f _clk2 × FCW2, where f _clk2 is the frequency of the working clock input to the second digital integrator, and FCW2 is the second frequency control word. ; The target frequency of the clock signal generating circuit f _t2 = f _clk1 × FCW1, where f _clk1 is the frequency of the working clock input to the first digital integrator, and FCW1 is the first frequency control word. The target frequency of the reference phase generating circuit is adjusted by changing the first frequency control word, and the target frequency of the clock signal generating circuit is adjusted by changing the second frequency control word, so that the target frequencies of the two are equal, thereby tracking the first reference phase signal. .

In a second aspect, a baseband processor is provided in an embodiment of the present application. The baseband processor includes a radio frequency transceiver and a phase locked loop circuit. The radio frequency transceiver is used to convert a low frequency digital signal into a radio frequency signal. The circuit is used to provide a high frequency carrier to the radio frequency transceiver, wherein the phase locked loop circuit is the phase locked loop circuit as in the first aspect and its possible design.

Because the second reference phase signal containing more spurs and clock jitter generated by the output clock generating circuit will not be fed back to the reference phase generating circuit through a feedback loop, the spurs and jitter will not be caused in the reference phase generating circuit and The clock signal generating circuits communicate with each other, thereby reducing clock jitter, improving the accuracy of the above-mentioned output clock signal, and improving the system performance of the phase-locked loop circuit. In addition, since the above-mentioned first digital integrator replaces the traditional voltage-controlled oscillator, the reference phase generating circuit is implemented as a pure digital circuit, which not only ensures the frequency and phase tracking performance of the phase-locked loop circuit, but also reduces the power of the phase-locked loop circuit. Consumption and area.

According to a third aspect, an embodiment of the present application provides an optical module for transmitting and receiving optical signals. The optical module includes a clock synthesizing circuit, a multiplexer, and a laser. The multiplexer provides a transmitting clock. The multiplexer is used to combine multiple signals into one signal. The laser is used to convert the one signal into an optical signal and transmit. The clock synthesizing circuit includes a phase-locked loop circuit. The phase-locked loop circuit is a phase-locked loop circuit as in the first aspect and its possible designs.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to explain the technical solutions in the embodiments of the present application or the prior art more clearly, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

FIG. 1 is a schematic diagram of a terminal device according to an embodiment of the present application.

FIG. 2 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the present application.

FIG. 3 is a waveform diagram of a ladder sawtooth wave signal generated by a first digital integrator in an embodiment of the present application.

FIG. 4 is a schematic diagram of a more specific phase-locked loop circuit in an embodiment of the present application.

5 (a) is a schematic diagram of another more specific phase-locked loop circuit in the embodiment of the present application;

FIG. 5 (b) is a schematic diagram of another more specific phase-locked loop circuit in the embodiment of the present application.

FIG. 6 is a schematic diagram of an optical module circuit according to an embodiment of the present application.

detailed description

In the following, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

The embodiment of the present application uses a terminal device 100 shown in FIG. 1 as an example for description. The terminal device 100 may be a mobile phone, a portable computer, or a tablet computer. The terminal device 100 may include devices or circuits such as an application processor 110 (Application Processor, AP), a memory 120, and a baseband processor 130. The application processor 110 is used to receive and process multimedia data buffered in the memory 120; the baseband 130 processor is used to process radio frequency signals, modulate and demodulate, encode and decode channels and sources, and process signaling. The above-mentioned baseband processor 130 may include a radio frequency transceiver 132 and one or more phase-locked loop circuits 200. The radio frequency transceiver 132 is configured to convert a low-frequency digital signal into a radio frequency signal, and the phase-locked loop circuit 200 is configured to pass a reference. The phase signal generates a high-frequency carrier wave and outputs it to the radio frequency transceiver 132. Similarly, the radio frequency transceiver 132 is further configured to receive radio frequency signals, and convert the radio frequency signals into low-frequency digital signals according to a carrier signal provided by the phase-locked loop circuit 200.

As shown in FIG. 2, a specific implementation of the phase-locked loop circuit 200 according to the present application is shown. The phase-locked loop circuit 200 includes a reference phase generating circuit 210 and a clock signal generating circuit 220. The reference phase generating circuit 210 is configured to receive a first reference phase signal V _ref1 and generate a second reference phase signal V _ref2 according to V _ref1 ; the clock signal generating circuit 220 is configured to receive the second reference phase signal V _ref2 and to generate a second reference phase signal V _ref2 according to V _ref2 An output clock signal V _{cout is} generated. The phase difference between the first reference phase signal V _ref1 and the second reference phase signal V _ref2 is 0, and the phase difference between the output clock signal V _cout and the second reference phase signal V _ref2 is also 0. The first reference phase signal V _{ref1 is} determined according to a tracking clock (hereinafter also referred to as a second working clock) of the phase-locked loop circuit 200, and may also be determined through an ultra-high-precision reference clock.

Specifically, the reference phase generating circuit 210 includes a first phase detector 212, a first loop filter 214, a first digital integrator 216, and a first feedback circuit 218. The first phase detector 212 is configured to compare the received first reference phase signal V _ref1 and the first feedback phase signal V _fb1 , and output the obtained first comparison result V _comp1 to the first loop filter 214. . A first loop filter 214 for a first comparison result V _comp1 low-pass filtering, comparing the first and the filtering result V _comp1 output to the first digital integrator 216. The first digital integrator 216 is configured to generate a second reference phase signal V _ref2 according to the filtered first comparison result V _comp1 . The first feedback circuit 218 is configured to feed back the second reference phase signal V _ref2 generated by the first digital integrator 216 to the first phase detector 212. The first target frequency f _{t1 of the} reference phase generating circuit 210 and the second target frequency f _{t2 of the} clock signal generating circuit 220 are equal. The first target frequency f _t1 may be determined by the first reference phase signal V _ref1 received by the reference phase generation circuit 210, and the second target frequency f _t2 may be determined by the second reference phase signal V _ref2 received by the clock signal generation circuit 220. . In addition, the phases of the first reference phase signal V _ref1 , the second reference phase signal V _ref2, and the output clock signal V _cout are all aligned, and the target frequencies of the reference phase generation circuit 210 and the clock signal generation circuit 220 are equal, so the reference phase generation circuit The frequency and phase of 210 and clock signal generating circuit 220 are synchronized.

Because the first feedback circuit 218 of the reference phase generating circuit 210 only feeds back the reference phase signal generated by the first digital integrator 216 to the first phase detector 212, the output clock generating circuit 220 contains more spurs and clock jitter. The second reference phase signal V _ref2 will not be fed back to the reference phase generating circuit 210, so that spurs and jitters will not be transmitted between the reference phase generating circuit 210 and the clock signal generating circuit 220, thus reducing clock jitter and improving The accuracy of the output clock signal V _cout improves the system performance of the phase-locked loop circuit 200. In addition, since the above-mentioned first digital integrator 216 replaces the conventional voltage-controlled oscillator, the reference phase generating circuit 210 is implemented as a pure digital circuit, which can guarantee the frequency and phase tracking performance of the phase-locked loop circuit 200 on the one hand; Since the function of the first digital integrator 216 is realized in the analog circuit, the power consumption of the phase-locked loop circuit 200 is lower and the area is smaller.

In one embodiment, the first phase detector 212 may be a subtractor or a comparator, so as to implement a phase comparison of two reference phase signals. The first loop filter 214 is used to filter the stray signals far from the center frequency in the first comparison result V _comp1 output by the first phase detector 212. In one embodiment, the first loop filter 214 may be a PI LPF (Proportional-Integral Loop Filter, proportional integral loop filter); in another embodiment, the first loop filter 214 may be Use proportional integral filter to realize. The above first feedback circuit 218 may include an interpolation circuit, and may also include a register, etc., which is not limited in this application.

The first digital integrator 216 is configured to generate a second reference phase signal V _ref2 , and the second reference phase signal V _ref2 may be a high-frequency periodic signal. In one embodiment, the second reference phase signal V _ref2 is a high-frequency stepped sawtooth wave signal. The second reference phase signal V _ref2 may also be other periodic signals such as a high-frequency square wave signal and a high-frequency sine wave signal. Taking the high-frequency stepped sawtooth wave signal as an example to explain the basic principle of the first digital integrator 216.

The filtered first comparison result V _{comp1 is} used as a first Frequency Control Word (FCW) FCW1 to control the phase change amount of the second reference phase signal V _ref2 in one clock cycle. As shown in FIG. 3, the ladder digital signal generated by the first digital integrator 216 according to the clock signal and the filtered first comparison result V _comp1 , the horizontal axis t is time, and the vertical axis p is phase. a comparison result as a first V _comp1 FCW1 frequency control word controls the stepped ramp signal. Specifically, the stepped sawtooth wave signal is obtained by downsampling the periodic sawtooth wave signal at a certain frequency, where the downsampling frequency is the frequency f _clk1 of the first working clock CLK1 driving the first digital integrator 216. In one embodiment, the first digital integrator 216 may be implemented by a digital accumulator with a limited bit width. When the accumulated value exceeds the expression range of the bit width, the accumulated value is reset to form a sawtooth wave of a specific frequency. . In the stepped sawtooth wave signal shown in FIG. 3, each stepped sawtooth wave signal period includes 16 “steps”, wherein the duration of each “step” is the inverse of the frequency of the first working clock CLK1, that is, 1 / f _clk1 , that is, each time the first digital integrator 216 downsamples to obtain a “step”. When the above-mentioned first digital integrator 216 is implemented by a digital accumulator, the digital accumulator may be an accumulator with a bit width of 5, so that the ladder sawtooth wave signal in one cycle drops to 0 after reaching 16, and the above “step The number of "" is controlled by the first frequency control word FCW1.

FIG. 4 shows a more specific implementation of the phase-locked loop circuit 200 according to the present application. The reference phase generating circuit 210 further includes a second digital integrator 211 and a low-pass filter 213. The second digital integrator 211 is configured to generate the first reference phase signal V _ref1 according to the second frequency control word FCW2, wherein the second frequency control word FCW2 is used to control the phase of the first reference phase signal V _ref1 in one clock cycle. The amount of change. The working principle of the second digital integrator 211 is similar to that of the first digital integrator 216, and details are not described herein again. It should be noted that the above-mentioned second frequency control word FCW2 may be a frequency control word provided in a register provided inside the second digital integrator 211, or may be input from the outside of the phase-locked loop circuit 200 to the second digital integrator 211. The frequency control word is not limited in this application. The low-pass filter 213 is configured to perform low-pass filtering on the received first comparison result V _comp1 output by the first phase detector 212 and output the filtered result to the first loop filter 214. The low-pass filter 213 may be implemented by one or more stages of an infinite impulse response filter (Infinite Impulse Response filter, IIR), for example, by a two-stage cascaded IIR.

The first target frequency f _{t1 of the} reference phase generation circuit 210 may be determined by the first reference phase signal V _ref1 received by the reference phase generation circuit 210, and the second target frequency f _{t2 of the} clock signal generation circuit 220 may be received by the clock signal generation circuit 220. The second reference phase signal V _{ref2 is} determined. Specifically, the first target frequency f _t1 = f _clk2 × FCW2 and the second target frequency f _t2 = f _clk1 × FCW1, where f _clk2 is the second working clock CLK2 (ie, the tracking clock) input to the second digital integrator 211 ), FCW2 is the second frequency control word that controls the second digital integrator 211; f _clk1 is the frequency of the first working clock CLK1 input to the first digital integrator 216, and FCW1 is the frequency that controls the first digital integrator 216 First frequency control word. The second working clock CLK2 is not only used to drive the second digital integrator 211, but also used to drive the first phase detector 212, low-pass filter 213, and loop filter 214. The first working clock CLK1 is used to drive the first A digital integrator 216. By controlling the sizes of the first frequency control word FCW1 and the second frequency control word FCW2, the first target frequency f _t1 corresponding to the reference phase generating circuit 210 and the second target frequency f _t2 corresponding to the clock signal generating circuit 220 are equal. It should be noted that the above-mentioned target frequency may also be referred to as a target synthesis frequency, or a synthesis frequency.

In the phase-locked loop circuit 200 shown in FIG. 4, the clock signal generating circuit 220 includes a second phase detector 222, a second loop filter 224, a voltage-controlled oscillator 226, and a second feedback circuit 228. The second phase detector 222 is configured to receive the second reference phase signal V _ref2 and the second feedback phase signal V _fb2 generated by the second feedback circuit 228, and compare the second reference phase signal V _ref2 and the second feedback phase signal V. _fb2 is subtracted, and the obtained phase difference V _{comp2 is} output to the second loop filter 224. In one embodiment, the second phase detector 222 may be a subtractor or a comparator. The second loop filter 224 is configured to perform low-pass filtering on the received second comparison result V _comp2 and output the filtered second comparison result V _comp2 to the voltage controlled oscillator 226. The voltage-controlled oscillator 226 is configured to receive the filtered second comparison result V _comp2 and generate an output clock signal V _cout according to the filtered second comparison result V _comp2 . In one embodiment, the voltage-controlled oscillator 226 may include an SDM (sigma-delta modulator, Sigma-delta modulator) circuit and a DCO (Digitally Controlled Oscillator, numerically controlled oscillator) circuit. The SDM circuit is used to refine the control scale of the DCO circuit and perform proportional integral control on the DCO circuit. The DCO circuit is used to generate a high-frequency periodic signal, such as a high-frequency square wave or a high-frequency signal, under the control of the SDM circuit. Sine wave. In one embodiment, the DCO circuit may be a numerically controlled LC (capacitive inductance) oscillator, or a numerically controlled RC (resistance capacitor) oscillator.

The second feedback circuit 228 is configured to convert the output clock signal V _cout generated by the voltage controlled oscillator 226 into a second feedback phase signal V _fb2 , and output the second feedback phase signal V _fb2 to the second phase detector 222. Specifically, the feedback circuit includes a frequency divider 2281, a counter 2282, a TDC (Time to Digital Converter) circuit 2283, a divider 2284, and an adder 2285. The frequency divider 2281 is configured to divide the output clock signal V _cout generated by the voltage-controlled oscillator 226 to obtain a low-frequency signal. The counter 2282 is used to calculate how many integer clock cycles the above-mentioned output clock signal V _cout has after frequency division, that is, to calculate an integer part in the phase of the output clock signal V _cout . The TDC circuit 2283 is configured to convert the frequency-divided output clock signal V _cout into a corresponding digital signal, that is, convert a non-integer part of the output clock signal V _cout into a digital signal. The adder 2285 is configured to add the integer part of the second feedback phase signal V _fb2 output by the counter 2282 and the non-integer part of the second feedback phase signal V _fb2 output by the TDC circuit 2283 to obtain a complete feedback phase signal, that is, the second The feedback phase signal V _fb2 is output to the second phase detector 222. In addition, the divider 2284 is configured to perform division calculation on the frequency-divided output clock signal V _cout and output the calculation result to the SDM circuit. The frequency divider 2281, the counter 2282, the TDC circuit 2283, and the divider 2284 in the second feedback circuit 228 are usually analog circuits, and phase noise is generated when the output clock signal V _cout is fed back. Since the phase noise is transmitted to the second phase detector 222 only through the second feedback circuit 228, but not to the digital circuit in the reference phase generating circuit 210, the clock jitter of the phase-locked loop circuit 200 is reduced, and Stray.

During the phase-locked loop circuit 200 being unstable to stable, the second feedback circuit 228 feeds back the output clock signal V _{cout with a} higher frequency generated by the voltage-controlled oscillator 226 to the second phase detector 222, and at the same time, The second phase detector 222 calculates a phase difference. As the phases of the output clock signal V _cout and the second reference phase signal V _ref2 are gradually aligned, the phase difference calculated by the second phase detector 222 gradually becomes smaller and approaches zero. When the phase difference between the output clock signal V _cout and the second reference phase signal V _ref2 is 0, the phase difference calculated by the second phase detector 222 is 0. At this time, the phase-locked loop circuit 200 is locked and the circuit is in a stable state.

In one embodiment, the reference phase generating circuit 210 may further include an interpolation circuit, so that the first phase detector 212 can compare the first reference phase signal V _ref1 and the first feedback phase signal V _fb1 in the same clock domain. The difference circuit may be a linear interpolation circuit, or other types of interpolation circuits. For example, the above-mentioned linear interpolation circuit is implemented by a multiplier, a divider, and two adders. FIG. 5 (a) is another more specific implementation manner of the reference phase generating circuit 210 according to the present application. The reference phase generating circuit 210 further includes a first interpolation circuit 215, which is configured to integrate the second digital integrator 211. The frequency of the generated first reference phase signal V _ref1 is synchronized with the frequency of the second reference phase signal V _ref2 , and the synchronized first reference phase signal V _{ref1 is} output to the first phase detector 212. Since the second reference phase signal V _ref2 fed back by the first feedback circuit 218 to the first phase detector 212 is a high-frequency signal, and the first reference phase signal V _ref1 generated by the second digital integrator 211 is a low-frequency signal, the required The first interpolation circuit 215 synchronizes the low-frequency first reference phase signal V _ref1 to a high-frequency clock domain, so that the two reference phase signals can be compared in the same clock domain, and the clock domain is a high-frequency clock domain.

FIG. 5 (b) is another more specific implementation of the reference phase generating circuit 210 according to the present application. The reference phase generating circuit 210 further includes a second interpolation circuit 217 and a third interpolation circuit 219. The second interpolation circuit 217 is configured to synchronize the frequency of the filtered first comparison result V _comp1 generated by the first loop filter 214 with the frequency of the second reference phase signal V _ref2 , and synchronize the filtered first The comparison result V _{comp1 is} output to the first digital integrator 216. The third interpolation circuit 219 is used to synchronize the frequency of the second reference phase signal V _ref2 generated by the first digital integrator 216 with the frequency of the first reference phase signal V _ref1 , and output the synchronized result to the first phase detector 212. Because the second interpolation circuit 217 and the third interpolation circuit 219 synchronize the frequencies of the signals, the first phase detector 212 can compare the signal phases in the low-frequency clock domain, which further reduces the power consumption of the phase-locked loop circuit 200. Saves hardware area.

The phase-locked loop circuit 200 provided in the embodiment of the present application may be independently provided in an ASIC (Application-Specific Integrated Circuit), or may be provided in the ASIC together with other circuits / modules / units.

FIG. 6 is a schematic diagram of an optical module circuit 600 provided according to the present application. The optical module circuit can be used in an optical modem in a home optical fiber communication device, and an optical transceiver in a base station. The optical module circuit includes a digital logic processing circuit 610, a clock synthesizing circuit 620, a driving circuit 630, a laser 640, a multiplexer 650, a splitter 660, a clock recovery circuit 670, and a photoreceptor 680. The digital logic processing circuit 610 is used for receiving and generating digital signals, and processing the digital signals. The clock synthesizing circuit 620, also known as a frequency synthesizer, is used to provide a transmission clock to the multiplexer 650. The multiplexer 650 is used to combine multiple low-speed signals into one signal that can be transmitted in a high-speed channel. The driving circuit 630 is used to drive a laser 640. The laser 640 can convert an electrical signal into an optical signal through, for example, a laser diode (LD), and emit the same. The photoreceptor 680 is used to receive and convert optical signals, for example, to convert optical signals to electrical signals through a photodiode (PD). The converted electrical signal passes through a clock recovery circuit 670, which is used to generate a recovered clock with the same frequency and phase as the transmitting end, and uses the recovered clock to sample the received data to recover the data sent by the transmitting , So as to achieve symbol synchronization between the transceiver. The splitter 660 is configured to convert the recovery data transmitted on the high-speed channel into data of multiple low-speed channels, and forward the data to the corresponding low-speed channels. The digital logic processing circuit 610 performs further processing on the data.

In the optical module circuit 600, the clock synthesizing circuit 620 and the clock recovery circuit may both include a phase-locked loop circuit 200 provided in the embodiment of the present application. In one embodiment, the optical module circuit 600 may be provided in an ASIC or packaged in a semiconductor package. In another embodiment, a part of the circuit / unit / module included in the optical module circuit 600 is provided in an ASIC or is packaged in a semiconductor package, and the ASIC / semiconductor package is provided in a printed circuit board , Printed circuit board); another part is arranged on the PCB in the form of a separate device, and forms an electrical coupling with the above-mentioned ASIC / semiconductor package.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the circuit is only a logical function division. In actual implementation, there may be another division manner. For example, multiple circuits or components may be combined or Can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or circuits, and may be electrical, mechanical or other forms.

The above is only a specific implementation of this application, but the scope of protection of this application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in this application. It should be covered by the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

A phase-locked loop circuit for generating an output clock signal includes a reference phase generating circuit and a clock signal generating circuit, wherein:

The reference phase generating circuit includes a first phase detector, a first loop filter, a first digital integrator, and a first feedback circuit, wherein:

The first phase detector is configured to receive a first reference phase signal and a first feedback phase signal, compare the phases of the first reference phase signal and the first feedback phase signal, and use a comparison result as a first The comparison result is output to the first loop filter;

The first loop filter is configured to perform low-pass filtering on the received first comparison result, and output the first comparison result after low-pass filtering to the first digital integrator;

The first digital integrator is configured to generate the second reference phase signal according to the filtered first comparison result;

The first feedback circuit is configured to receive the second reference phase signal and output the first reference phase signal to the first phase detector.

The clock signal generating circuit is configured to receive the second reference phase signal and generate the output clock signal according to the second reference phase signal;

Wherein, the target frequency of the reference phase generating circuit and the target frequency of the clock signal generating circuit are equal, the phase difference between the first reference phase signal and the second reference phase signal is 0, and the second reference phase The phase difference between the signal and the output clock signal is zero.
The phase-locked loop circuit according to claim 1, wherein the first digital integrator is configured to control a phase change amount of the second reference phase signal within one clock period according to a first frequency control word, and The first frequency control word is a first comparison result after the filtering.
The phase-locked loop circuit according to claim 1 or 2, wherein the reference phase generating circuit further comprises a second digital integrator, and the second digital integrator is configured to generate the first digital integrator according to a second frequency control word. A reference phase signal, and the second frequency control word is used to control a phase change amount of the first reference phase signal within one clock cycle.
The phase-locked loop circuit according to any one of claims 1 to 3, wherein the reference phase generating circuit further comprises a first interpolation circuit, and the first interpolation circuit is configured to convert the first reference phase signal The frequency of is synchronized with the frequency of the second reference phase signal, and the synchronized first reference phase signal is output to the first phase detector.
The phase-locked loop circuit according to any one of claims 1 to 3, wherein the reference phase generating circuit further comprises a second interpolation circuit and a third interpolation circuit, wherein:

The second interpolation circuit is configured to synchronize the frequency of the filtered first comparison result generated by the first loop filter with the frequency of the second reference phase signal, and synchronize the filtered filter Output the first comparison result to the first digital integrator;

The first feedback circuit includes the third interpolation circuit, and the third interpolation circuit is configured to compare the frequency of the second reference phase signal generated by the first digital integrator with the frequency of the first reference phase signal. The frequency is synchronized, and the synchronized second reference phase signal is fed back to the first phase detector.
The phase-locked loop circuit according to claim 1, wherein the clock signal generating circuit comprises a second phase detector, a second loop filter, a voltage controlled oscillator, and a second feedback circuit, wherein:

The second phase detector is configured to receive the second reference phase signal and the second feedback phase signal, subtract the second reference phase signal and the second feedback phase signal, and output the obtained phase difference to The second loop filter;

The second loop filter is configured to receive the phase difference, perform low-pass filtering on the phase difference, and output the filtered phase difference to a voltage controlled oscillator;

The voltage-controlled oscillator is configured to receive the filtered phase difference and generate an output clock signal according to the filtered phase difference;

The second feedback circuit is configured to convert the output clock signal generated by the voltage-controlled oscillator into the second feedback phase signal, and output the second feedback phase signal to the second phase detector .
A baseband processor, the baseband processor includes a radio frequency transceiver and a phase locked loop circuit, the radio frequency transceiver is used to convert a low frequency digital signal into a radio frequency signal, and the phase locked loop circuit is used to provide the radio frequency transceiver Provide a high frequency carrier, wherein the phase locked loop circuit is a phase locked loop circuit according to any one of claims 1-6.
An optical module is used for transmitting and receiving optical signals. The optical module includes a clock synthesizing circuit, a multiplexer, and a laser. The clock synthesizing circuit is configured to provide a transmitting clock to the multiplexer. The multiplexer is used for combining multiple signals into one signal, and the laser is used for converting the one signal into an optical signal and transmitting, wherein the clock synthesizing circuit includes any one of claims 1-6 PLL circuit