CN204376874U - Clock generation circuit - Google Patents
Clock generation circuit Download PDFInfo
- Publication number
- CN204376874U CN204376874U CN201520075793.3U CN201520075793U CN204376874U CN 204376874 U CN204376874 U CN 204376874U CN 201520075793 U CN201520075793 U CN 201520075793U CN 204376874 U CN204376874 U CN 204376874U
- Authority
- CN
- China
- Prior art keywords
- phase
- clock
- locked loop
- circuit
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The utility model discloses a kind of clock generation circuit, it comprises: the second delay phase-locked loop that the first delay phase-locked loop for the T/H sampling clock that aligns, the clock for generation of leggy export and utilize the clock of the second delay phase-locked loop and produce the phase generating circuit of time analog to digital conversion circuit clock.This circuit is applicable to producing flexible and changeable different lane, the various phase clock signals of different stage, because employ DLL, each phase place directly postpones or interval can well control, not with technique, voltage, or variations in temperature, be especially suitable as the clock generation circuit of timing interleaved ADC.
Description
Technical field
The utility model relates to a kind of clock generation circuit.
Background technology
High-speed, high precision analog to digital conversion circuit (ADC) has a wide range of applications in a lot of fields, and no matter from satellite communication, data communication or multimedia application, all be unable to do without the high-speed, high precision analog to digital conversion circuit of high-speed, high precision.In the system framework of current high-speed, high precision analog to digital conversion circuit, be all generally the structure adopting timing interleaved, be woven into the analog to digital conversion circuit of a high speed with the analog to digital conversion circuit of multiple low speed.
In the framework of timing interleaved ADC general at present, multiple (being generally 4 or 8) independently ADC samples to same input signal, and the moment of each ADC sampling, produced by clock control circuit, such as phase-locked loop (PLL) or delay phase-locked loop (DLL).At last numeric field, their output is synthesized the digital signal that a high sampling rate exports.As depicted in figs. 1 and 2.In the ADC of this framework, high to the requirement of clock, for the clock delivering to each ADC, except having strict requirement to its jitter, its skew (departing from the size of ideal position) also seriously governs the performance of whole ADC.This all proposes strict requirement to the clock generation circuit of timing interleaved ADC.
In order to the needs making clock more easily meet high-speed ADC application, paper " A 480mW 26GS10 bit Time-Interleaved ADC with 48.5dB SNDR up to Nyquist in 65nm CMOS " (IEEE, JSSC, VOL.46, NO.12, DECEMBER 2011) in put forward the structure of T/H hierarchy.With traditional structure unlike, not that the ADC of every bar lane uses a T/H (track and hold) circuit, but whole timing interleaved ADC only uses a T/H, and the output of T/H is received again each analog to digital conversion circuit (subADC), as shown in Figure 3.Such benefit only has the clock request of T/H to be the highest, and the requirement of the clock of subADC can reduce.And the clock of T/H directly can use through simple buffering with outside high-quality clock, the clock of subADC produces clock by the clock generation circuit of inside again.
When the clock type that T/H with subADC uses is identical, is all such as CMOS level, can very easily the clock of T/H and the clock of subADC be alignd.When both clock types are different, such as T/H uses LVDS level, and subADC uses CMOS level, just needs special clock generation circuit to produce them and they to be alignd.This situation is often occur in actual applications, and such as outside high-quality input clock is LVDS level signal usually, and T/H is in order to realize high-speed sampling, does not often also use CMOS level.And for such use, also there is no corresponding clock resolution.
Utility model content
The utility model object is: provide a kind of clock generation circuit, especially when the clock type of T/H and the clock type of subADC inconsistent time, delay phase-locked loop is used to align the clock of clock of T/H and the clock of subADC, simultaneously, the subStage that the delay phase-locked loop of leggy is subADC is used to produce not with technique, voltage, the delay of steady change and non-overlapping.
The technical solution of the utility model is: a kind of clock generation circuit, it comprises: for the first delay phase-locked loop of the T/H sampling clock that aligns, for generation of the second delay phase-locked loop that the clock of leggy exports, and utilize the clock of the second delay phase-locked loop and produce the phase generating circuit of clock required for time analog to digital conversion circuit, wherein said first delay phase-locked loop is used for the T/H sampling clock of different level and an inner clock to align, and generate the input that the second delay phase-locked loop delivered to by the clock exported, and described second delay phase-locked loop receives the clock that the first delay phase-locked loop produces, and the clock of leggy is produced with time delay chain, and phase generating circuit is delivered to after the logical time delay same with the first delay phase-locked loop, and phase generating circuit generates secondary clock required for analog to digital conversion circuit.The utility model uses delay phase-locked loop to align the clock of T/H and the internal clocking of time analog to digital conversion circuit (subADC) thus, meanwhile, and directly postpone and non-overlapping isochronon with the clock that the multiphase clock that delay phase-locked loop produces realizes subADC inside; When the clock type of T/H and subADC different time, use 2 DLL, first delay phase-locked loop is used for the clock that aligns, and the second delay phase-locked loop is used for producing multiphase clock, and uses phase generating circuit to produce the clock required for each stage of each subADC.When the clock type of T/H is the same with subADC, first delay phase-locked loop (DLL1) not necessarily, the second delay phase-locked loop (DLL2) only can be used to produce multiple phase place, and then produce the clock required for each stage of each subADC by phase generating circuit.
On the basis of technique scheme, comprise following attached technical scheme further:
Described first delay phase-locked loop comprises the phase discriminator alignd for varying level type and the time delay module matched with the second delay phase-locked loop and phase generating circuit.
Described second delay phase-locked loop comprises the time delay chain producing leggy and the time delay module matched with the first delay phase-locked loop.
The multipath clock that described phase generating circuit exports according to the second delay phase-locked loop, produces the clock signal required for analog to digital conversion circuit by gate, and the time delay module in the logical signal of gate and the first delay phase-locked loop matches.
Described first delay phase-locked loop comprises phase discriminator, charge pump, a time delay chain, a filter capacitor, dummy logical circuit, frequency-halving circuit, and divide by four circuit, wherein Fs is the LVDS clock of T/H, be input to frequency-halving circuit simultaneously, divide by four circuit, with in phase discriminator, the output of phase discriminator connects charge pump, its output charge produces control voltage vctrl1 to filter capacitor charging, vctrl1 controls the time delay of time delay chain, the input signal of time delay chain comes from frequency-halving circuit, the second delay phase-locked loop is given as its input signal in output one tunnel of time delay chain, dummy logical circuit is delivered on one tunnel, and dummy logical circuit is used for the second delay phase-locked loop and phase generating circuit does the coupling postponed.
The utility model advantage is:
The utility model is applicable to producing flexible and changeable different lane, the various phase clock signals of different stage, because employ delay phase-locked loop, each phase place directly postpones or interval can well control, not with technique, voltage, or variations in temperature, be especially suitable as the clock generation circuit of timing interleaved ADC.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the utility model is further described:
Fig. 1 is the enforcement block diagram of the timing interleaved ADC of present technology.
Fig. 2 is the sequential chart of the timing interleaved ADC of prior art.
Fig. 3 is the enforcement block diagram of the interleaved ADC of prior art T/H hierarchy structure.
Fig. 4 is enforcement block diagram of the present utility model.
Embodiment
Embodiment: in the following description, for illustrative purposes, sets forth specific detail, provides understanding of the present invention to facilitate.But those skilled in the art are it is to be understood that can implement the present invention when not having these details.Those skilled in the art will recognize that can in every way and use various device to perform with described embodiment of the present invention.
In addition, connection between parts in accompanying drawing is not limited to the connection by the effect of direct mode device, when not departing from the present invention and knowing, the connection between the parts illustrated in accompanying drawing can be modified or be changed by the intermediate member adding or reduce wherein.
For convenience of description, say in the particular instance provided at this specification, the ADC framework sharing the timing interleaved of a T/H with 4 subADC illustrates, and the sample frequency designing this ADC is 1.2GHz, and the clock level type of input is LVDS.
As shown in Figure 4, the utility model provides a kind of specific embodiment of clock generation circuit, it comprises the first delay phase-locked loop for the T/H sampling clock that aligns, for generation of the second delay phase-locked loop that the clock of leggy exports, and utilize the clock of the second delay phase-locked loop and produce the phase generating circuit of clock required for time analog to digital conversion circuit, wherein the first delay phase-locked loop is used for the T/H sampling clock of different level and an inner clock to align, and generate the input that the second delay phase-locked loop delivered to by the clock exported, and the second delay phase-locked loop receives the clock that the first delay phase-locked loop produces, and the clock of leggy is produced with time delay chain, and phase generating circuit is delivered to after the logical time delay same with the first delay phase-locked loop, and phase generating circuit generates secondary clock required for analog to digital conversion circuit.
First delay phase-locked loop comprises BANG BANG phase discriminator, charge pump, a time delay chain, filter capacitor, dummy logical circuit, frequency-halving circuit and a divide by four circuit.Fs is the LVDS clock of T/H, is input in frequency-halving circuit, divide by four circuit and phase discriminator simultaneously.The output of phase discriminator connects charge pump, its output charge produces control voltage vctrl1 to filter capacitor charging, vetrl1 controls the time delay of time delay chain, the input signal of time delay chain comes from frequency-halving circuit, the second delay phase-locked loop is given as its input signal in output one tunnel of time delay chain, and dummy logical circuit is delivered on a road.Dummy logical circuit is mainly used to the second delay phase-locked loop and phase generating circuit does the coupling postponed.
Fs is 1.2GHz, and time delay chain 13 is operated in 600MHz, and clk_dum is operated in 300MHz, so phase discriminator is operated in 300MHz.Therefore, for Fs, every 4, along just comparing with the phase place of clk_dum, this function realizes by divide by four circuit, and it produces an en_pd signal, enable phase discriminator every the edge of 4 Fs.When after the first delay phase-locked loop locking, the edge of Fs should be alignment with the edge of clk_dum, if that is there is a clock, it, along being and Fclk2 alignment, so passes through same delay logic unit, and its output edge should be align with Fs.
Second delay phase-locked loop also comprises phase discriminator, charge pump, filter capacitor, time delay chain, one group of delay unit and frequency-halving circuit etc.The clock Fclk2 that first delay phase-locked loop exports is input to the phase discriminator of the second delay phase-locked loop, time delay chain and delay unit.Phase discriminator wherein in the second delay phase-locked loop, charge pump, connection between filter capacitor and time delay chain and the first delay phase-locked loop similar.Time delay chain uses 16 grades of delay cells, and the one-period of Fclk2 is evenly divided into 16 parts, and these 16 clock, through after two circuit, are equivalent to the clock of 300MHz evenly be divide into 32 parts, i.e. ph0, ph1...ph31.Ph32 and ph33 just exists as dummy clock, and phase generating circuit below does not need to use this two clocks.
Phase generating circuit is 32 phase places that the second delay phase-locked loop is exported, and use the phase place of gate production required for ADC, it comprises one group of combinational logic circuit.Often need a switch to turn off before another one switch OFF prerequisite in ADC, or two switches directly to produce the non-overlapping time, these 32 clock signal combinations can be used to realize.
After first and second delay phase-locked loop all locks, because L1_MDAC1_sample_p is produced by ph0, so its edge is alignment with the clk_dum in DLL1, thus be also alignment with Fs, so just achieve the function of the clock of T/H and the clock alignment of subADC inside, and other clock of subADC, also achieve the fixed phase relationship with the clock of T/H.
The utility model is applicable to producing flexible and changeable different lane, the various phase clock signals of different stage, because employ delay phase-locked loop, each phase place directly postpones or interval can well control, not with technique, voltage, or variations in temperature, be especially suitable as the clock generation circuit of timing interleaved ADC.
Certain above-described embodiment, only for technical conceive of the present utility model and feature are described, its object is to person skilled in the art can be understood content of the present utility model and implement according to this, can not limit protection range of the present utility model with this.All equivalent transformations of doing according to the Spirit Essence of the utility model main technical schemes or modification, all should be encompassed within protection range of the present utility model.
Claims (5)
1. a clock generation circuit, it is characterized in that it comprises: for the first delay phase-locked loop of the T/H sampling clock that aligns, for generation of the second delay phase-locked loop that the clock of leggy exports, and utilize the clock of the second delay phase-locked loop and produce the phase generating circuit of clock required for time analog to digital conversion circuit, wherein said first delay phase-locked loop is used for the T/H sampling clock of different level and an inner clock to align, and generate the input that the second delay phase-locked loop delivered to by the clock exported, and described second delay phase-locked loop receives the clock that the first delay phase-locked loop produces, and the clock of leggy is produced with time delay chain, and phase generating circuit is delivered to after the logical time delay same with the first delay phase-locked loop, and phase generating circuit generates secondary clock required for analog to digital conversion circuit.
2. a kind of clock generation circuit as claimed in claim 1, is characterized in that: described first delay phase-locked loop comprises the phase discriminator alignd for varying level type and the time delay module matched with the second delay phase-locked loop and phase generating circuit.
3. a kind of clock generation circuit as described in claim 2, is characterized in that: described second delay phase-locked loop comprises the time delay chain producing leggy and the time delay module matched with the first delay phase-locked loop.
4. a kind of clock generation circuit as described in claim 3, it is characterized in that: the multipath clock that described phase generating circuit exports according to the second delay phase-locked loop, produce the clock signal required for analog to digital conversion circuit by gate, and the time delay module in the logical signal of gate and the first delay phase-locked loop matches.
5. a kind of clock generation circuit as claimed in claim 1, it is characterized in that: described first delay phase-locked loop comprises phase discriminator, charge pump, a time delay chain, a filter capacitor, dummy logical circuit, frequency-halving circuit, and divide by four circuit, wherein Fs is the LVDS clock of T/H, be input to frequency-halving circuit simultaneously, divide by four circuit, with in phase discriminator, the output of phase discriminator connects charge pump, its output charge produces control voltage vctrl1 to filter capacitor charging, vctrl1 controls the time delay of time delay chain, the input signal of time delay chain comes from frequency-halving circuit, the second delay phase-locked loop is given as its input signal in output one tunnel of time delay chain, dummy logical circuit is delivered on one tunnel, and dummy logical circuit is used for the second delay phase-locked loop and phase generating circuit does the coupling postponed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520075793.3U CN204376874U (en) | 2015-02-03 | 2015-02-03 | Clock generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520075793.3U CN204376874U (en) | 2015-02-03 | 2015-02-03 | Clock generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204376874U true CN204376874U (en) | 2015-06-03 |
Family
ID=53333050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520075793.3U Active CN204376874U (en) | 2015-02-03 | 2015-02-03 | Clock generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204376874U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020041967A1 (en) * | 2018-08-28 | 2020-03-05 | 华为技术有限公司 | Phase locked loop circuit and device using same |
-
2015
- 2015-02-03 CN CN201520075793.3U patent/CN204376874U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020041967A1 (en) * | 2018-08-28 | 2020-03-05 | 华为技术有限公司 | Phase locked loop circuit and device using same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10541693B2 (en) | Method and apparatus for source-synchronous signaling | |
| US7522084B2 (en) | Cycle time to digital converter | |
| CN104113342B (en) | High-speed data synchronous circuit used for high-speed digital-to-analog converter | |
| US7486746B2 (en) | Clock and data recovery with extended integration cycles | |
| US8634503B2 (en) | Fast lock clock-data recovery for phase steps | |
| US20130207703A1 (en) | Edge selection techniques for correcting clock duty cycle | |
| US9054941B2 (en) | Clock and data recovery using dual manchester encoded data streams | |
| CN103427830B (en) | A kind of half-blindness type over-sampling clock data recovery circuit with high lock-in range | |
| US9154291B2 (en) | Differential signal skew adjustment method and transmission circuit | |
| CN103516355A (en) | Delay control circuit and clock generation circuit including the same | |
| WO2016101836A1 (en) | Clock delay method and device, delay phase locked loop and digital clock management unit | |
| US7990295B2 (en) | Data transfer apparatus | |
| CN204376874U (en) | Clock generation circuit | |
| US6035409A (en) | 1000 mb phase picker clock recovery architecture using interleaved phase detectors | |
| CN105553470B (en) | A kind of serializer based on half rate clock restoring circuit | |
| US9571077B1 (en) | Dynamic update technique for phase interpolator device and method therefor | |
| CN104660222B (en) | The d type flip flop and five frequency dividing circuits of a kind of current switching formula | |
| CN102916700B (en) | Data transmission device and method | |
| CN205596095U (en) | Serializer based on half rate clock recovery circuit | |
| CN103684473A (en) | High-speed serial-parallel conversion circuit based on FPGA | |
| JP2009165064A (en) | Frequency dividing circuit and frequency dividing method | |
| Liu et al. | 180.5 Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance | |
| US6665360B1 (en) | Data transmitter with sequential serialization | |
| Kadayinti et al. | A clock retiming circuit for repeaterless low swing on-chip interconnects | |
| El-Shafie et al. | A novel N-bit SAR implementation for All-Digital DLL circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C53 | Correction of patent for invention or patent application | ||
| CB03 | Change of inventor or designer information |
Inventor after: Zhang Jianyun Inventor before: Kuang Xigen |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: KUANG XIGEN TO: ZHANG JIANYUN |