WO2016101836A1

WO2016101836A1 - Clock delay method and device, delay phase locked loop and digital clock management unit

Info

Publication number: WO2016101836A1
Application number: PCT/CN2015/097729
Authority: WO
Inventors: 包朝伟; 崔社涛; 姚（韋華）荣; 王佩宁
Original assignee: 深圳市国微电子有限公司
Priority date: 2014-12-26
Filing date: 2015-12-17
Publication date: 2016-06-30
Also published as: CN104579320A; CN104579320B

Abstract

A clock delay method and device, a delay phase locked loop and a digital clock management unit. The clock delay method comprises: step 1, delaying an input clock for T_i through a delay line (44), so as to obtain an output clock; step 2, comparing the input clock with the output clock, and if the input clock lags behind the output clock, returning to step 1 and delaying the input clock for (T_i+ T_x)/2 through the delay line (44) once again; and if the input clock is ahead of the output clock, returning to step 1 and delaying the input clock for (T_y+ T_i)/2 through the delay line (44) once again; and until the input clock is aligned with the output clock, outputting the output clock as aligned with the input clock. By means of the technical solution, alignment is realized in a dichotomic-type successive approximation method, at most, N clock cycles are needed, and in the case where the input clock is significantly different from the output clock, the locking speed of a DLL is accelerated, thereby increasing the operating speed of a chip system.

Description

Description Title: Clock delay method, device, delay phase locked loop and digital clock management unit

[0001] The present invention relates to the field of electronic technology, and in particular, to a clock delay method, a device, a delay phase locked loop, and a digital chime management unit.

Background technique

[0002] There are digital clock management (DCM) units in Field Programmable Gate Array (FPGA), which mainly provide three functions: 吋 clock to skew, frequency synthesis and phase shift. The 吋 clock to skew is implemented by a delay locked loop (DLL).

[0003] Input 吋 (CLKIN) During transmission, due to the influence of the load capacitance and the distribution network of the 吋 clock, the phase of the arrival is inconsistent, resulting in skew (Skew). The delay-locked loop aligns the phase of the input cesium clock with the output cesium clock (CLKOUT) to eliminate skew.

[0004] The principle of the existing delay-locked loop aligning the phases of the input chirp and the output chirp is as follows: The phase detector (PD) detects the phase difference between CLKIN and CLKOUT, and sends it to the logic control unit (Logic), the logic control unit. (Logic) The output control signal controls the flipping of the shift register (Counter). Each time the shift register (Co unter) is flipped, the number of delay units used in the delay line is increased or decreased by one, and accordingly, the shift register ( Counter) Each time it is flipped, the delay time of one delay unit is increased or decreased (hereinafter, the delay time of one delay unit is simply referred to as unit delay time), that is, the prior art is through a shift register (Counter). - the next time the flip is repeated or decreased by one unit delay to achieve alignment, if the delay line includes 2

Delay unit, the shift register (Counter) needs to flip 2 W owes at most, the unit delay in the delay line is usually very small, if it is 0.1 ns, then the shift register (Counter) increases or decreases every time it is flipped. A delay of 0.1 ns.

[0005] When the difference between CLKIN and CLKOUT is large, using the above prior art, it is necessary to shift the register a plurality of times to achieve the clock alignment. For example, in an FPGA chip with a large chip area (such as 2 million gates of F PGA), the phase difference between CLKIN and CLKOUT is usually 2 ns due to the delay of the transmission line and the parasitic capacitance of the 吋网络 network. If the frequency of CLKIN is 100 MHz, Its cycle is 10ns, want to achieve CLK The phase alignment of IN and CLKOUT requires CLKOUT to be pushed back 8ns, and each delay cell in the delay line can provide a delay of 0.1ns. Then 80 delay units are required to provide the delay, that is, the shift register needs to be flipped. 80 times, the phase of CLKIN and CLKOUT can be aligned, resulting in a long lockout delay of the phase-locked loop and a slow locking speed, which will affect the operating speed of the chip system.

technical problem

The invention provides a clock delay method, a device, a delay phase-locked loop and a digital chime management unit, and how to quickly realize an input chirp and an output chirp when the input chirp and the output chirp are greatly different. Alignment issues.

Problem solution

Technical solution

[0007] In order to solve the above technical problem, the present invention adopts the following technical solutions:

[0008] A chirping delay method includes:

[0009] Step one, delaying the input clock by 1⁄4 through the delay line to obtain an output clock;

[0010] Step 2: Comparing the input chirp clock and the output chirp clock, if the input chirp clock lags the output chirp clock, returning to step one, re-delaying the input chirp clock by the delay line T _i+1 1 ₁₊₁ is (T _i+ T _x ) 12, if the input clock is ahead of the output clock, it returns to step one, and the input delay is delayed by the delay line T' _i+1 , T ' _i+ ^ (Τ _γ + Τ\ ) /2; until the input chirp and output chirp are aligned, outputting an output chirp aligned with the input chirp; where 1\ is 1 to 1\ and , one that is larger than 1\ and distance 1\, T _y is T, ST i and 0 are smaller than T i and the closest to T i , and T is the maximum delay of the delay line.

[0011] A chirp clock delay device, comprising:

[0012] a delay processing unit, configured to delay the input chirp clock by 1⁄4 through the delay line, to obtain an output chirp; and the comparison delay in the comparison processing unit is that the input chirp is delayed by the output chirp, and the delay is re-passed. The line delays the input chirp clock T _i+1 , ^ ₊₁ is (T _i+ T _x ) 12, and the output chirp clock is obtained; the comparison result in the comparison processing unit is the condition that the input chirp is ahead of the output chirp clock Next, the input chirp clock is delayed by T' _i+1 through the delay line, and ₁₊₁ is (T _{y +} T i ) 12, and an output chirp is obtained; until the input chirp and the output chirp are aligned, the output is The input chirp-aligned output chirp; wherein, 1\ is 1 to 1\ and T, the one that is larger than T i and closest to the distance T i , T _y is T, to D i and 0 to T i Small and closest to T i One, τ is the maximum delay of the delay line;

[0013] a comparison processing unit, configured to compare the input clock and the output clock.

[0014] A delay phase locked loop, comprising:

[0015] a logic control unit, configured to generate a binary control signal C _i according to a preset rule _; and regenerate the binary control signal C _i+ under the condition that the input phase clock lags the output clock after the comparison result of the phase detecting unit ₁ ; regenerating the binary control signal C' _i+1 under the condition that the comparison clock of the phase detecting unit is ahead of the output clock _;

[0016] a delay line control unit, configured to control the delay line to delay the input clock by T i according to the binary control signal C i generated by the logic control unit, to obtain an output clock; and to generate a binary control signal according to the logic control unit ^ _{+ 1} controlling the delay line to re-input the input clock delay T _i+1 , ^ ₊₁ is (T _i+ T _x ) 12, obtaining an output chirp; controlling according to the binary control signal C' _i+1 regenerated by the logic control unit The delay line re-intermits the input chirp clock by T' _i+1 , ₁₊₁ is (T _{y +} T i ) 12, and the output chirp is obtained; until the input chirp and the output chirp are aligned, the output and the input are The clock-aligned output 吋 clock; where 1\ is 1 to 1\ and T, which is larger than T i and closest to T i , T _y is T, and is smaller than T i and smaller than D i The nearest one of T i , τ is the maximum delay of the delay line;

[0017] The phase detecting unit is configured to compare the input clock and the output clock, and output the comparison result to the logic control unit.

[0018] A digital cuckoo clock management unit comprising the cuckoo clock delay device described above, or a delay phase locked loop.

Advantageous effects of the invention

Beneficial effect

[0019] The clock delay method, device, delay phase-locked loop and digital chime management unit provided by the present invention, if the output chirp obtained after delaying Ti is not aligned with the input chirp, if the input chirp is delayed The output of the cesium clock indicates that Ti is not enough. In the range where Ti and Tx (Tx is T1 to Ti and T, which is larger than Ti and the closest to Ti, τ is the maximum delay of the delay line), the interval is taken as the intermediate value ( Ti+Tx) /2 is re-delayed. If the input clock is ahead of the output cesium, then Ti is too large, in Ty (Ty

The intermediate value of the interval between TI and Ti and 0 which is smaller than Ti and closest to Ti (Ty+ Ti)

/2 re-delay, therefore, the present invention uses a two-point successive approximation to achieve alignment, compared to the prior art method of increasing or decreasing unit delays one by one, up to 2N 吋 weeks The period is reduced to a maximum of N 吋 clock cycles. When the input 吋 clock and the output 吋 clock are greatly different, the locking speed of the DLL is accelerated, and the working speed of the chip system is improved.

[0020] Further, the present invention also designs a generation mechanism of the binary control signal α. According to the mechanism designed by the present invention, the generated binary control signal α is not aligned with the input chirp clock after the delay. In this case, the delay of the delay line can be accurately controlled to achieve the alignment of the above-described two-division successive approximation. Correspondingly, the circuit structure of the logic control unit designed by the invention can be realized only by a small number of flip-flops, and the output directly controls the delay line, which is composed of a shift register, a Gray code converter and a Gray code decoder. Compared with the logic control unit, the structure is simpler, the technical difficulty is small, and the risk is low.

Brief description of the drawing

DRAWINGS

1 is a schematic diagram of a cuckoo clock delay device according to an embodiment of the present invention;

2 is a schematic diagram of a delay phase locked loop according to an embodiment of the present invention;

3 is a schematic diagram of a logic control unit in the delay phase locked loop shown in FIG. 2;

4 is a schematic diagram of phases of signals according to an embodiment of the present invention;

[0025] FIG. 5 is another phase diagram different from FIG. 4;

6 is another phase diagram different from FIGS. 4 and 5.

BEST MODE FOR CARRYING OUT THE INVENTION

[0027] The paragraphs describing the best mode of the invention are entered here.

Embodiments of the invention

[0028] In order to improve the alignment speed of the input cesium clock and the output cesium clock, the invention speeds up the locking speed of the DLL, and proposes the following concept: The output 吋 clock obtained after the delay T i is compared with the input 吋 clock, the input 吋 clock is still In the case of lag in the output cesium clock, the input 吋 clock is delayed by T _i+1 through the delay line, and D ₁₊₁ is (T _i+ T _x ) 12 , and the input 吋 clock is still ahead of the output 吋 clock, The input chirp is delayed by T' _i+1 through the delay line, D'_{; +1} is (T _y + T i ) 12, and so on, until the input chirp and the output chirp are aligned. Input 吋 clock still If the lag is delayed from the output 吋, it means that the delay T i is not enough, so the intermediate value is taken in the range of T i and τ _χ (Τ i+T _x

/2 re-delay, the input 吋 clock is still ahead of the output 吋 clock, then the delay T i is too large, so take the intermediate value (T _y + T i ) /2 in the interval of T _y and T i Delay is performed, and so on. If the alignment is not aligned, the corresponding interval is continued to be divided until the input chirp and the output chirp are aligned. The present invention adopts the dichotomy successive approximation method, which is different from the prior art one by one. Or reduce the unit delay of the delay line in a way that requires up to N 吋 clock cycles to achieve alignment. In the case where the input 吋 clock and the output 吋 clock are large, the DLL lock can be significantly accelerated compared to the prior art. Speed, improve the working speed of the chip system.

[0029] The input chirp clock and the output chirp clock described in the present invention are not limited to the case where the input chirp and the output chirp are completely aligned, and the phase difference between the input chirp and the output chirp is preset. In the range, therefore, the case where the phase difference between the input cesium clock and the output cesium clock is small is also aligned. When the input chirp lags the output 吋 clock and the phase difference exceeds the above preset range, the input 吋 clock lags the output 吋 clock. When the input cesium clock is ahead of the output cesium clock and the phase difference exceeds the above preset range, it belongs to the input cesium clock before the output cesium clock.

[0030] The present invention will be further described in detail below with reference to the accompanying drawings.

[0031] The method for delaying the chirp clock according to an embodiment of the present invention includes the following processes:

[0032] S101. Delay the input chirp clock by 1⁄4 through the delay line to obtain an output chirp clock.

[0033] S102. Comparing the input clock and the output clock, if the input clock lags the output clock, returning to S101, and delaying the input clock by the delay line by T _i+1 , 1 \ ₊₁ is (T _i+ T _x ) 12, if the input clock leads the output clock, it returns to S101, and the input delay is delayed by the delay line T' i ₊₁ , T' _i+ ( T _y + T i ) /2; until the input chirp and the output chirp are aligned, outputting an output chirp aligned with the input chirp; wherein, 1\ is 1 to 1\ and Dingzhong, ratio 1\ Large and distance 1\the nearest one, T _y is T , ST i and 0 are smaller than T i and the closest to T i , and T is the maximum delay of the delay line.

[0034] In step S101, the initial value 1 of 1\ can be arbitrarily set as long as it is greater than 0 and less than T. Preferred

The initial value of 1\ is taken as 172, which makes alignment more efficient.

[0035] This embodiment does not limit the composition of the delay line, as long as the input clock can be delayed by T i, T _i+1 _T'i+1 can be. For delay lines of different structures, the value of T i can be adjusted in different ways. For example, for a delay line including a plurality of delay units, the value of T i can be adjusted by adjusting the number of used delay units.

[0036] Preferably, the delay line includes two delay units, and the delay period of each delay unit, that is, the unit delay time is t (the value of t is not limited to 0.1 ns), and the Bay IjT is *t. For the delay unit of this structure, preferably, the initial value 1 of 1\ is 2", that is, the maximum delay of the delay line is half of 2 ^N *t, correspondingly, that is, using 2 ^1 in the delay line Delay units are delayed, that is, half of the delay units are used for delay, and the output clock is obtained. If the input clock lags the output clock, the delay 2 ^*t is not enough, and 2 ^N *t to the maximum delay is used. The median value of 2 ^N *t in the interval (2 ^N +2 ^N ) *t /2 is delayed by the input 吋 clock, ie T ₂ = (2 ^N -'+2 ^N ) *t /2, corresponding , that is, using the delay line (2

/2 delay units re-intermit the input 吋 clock; if the input 超 clock leads the output 吋 clock, then the delay 2 Ni*t is too large, then the intermediate value of 0 to 2 Ni*t is used 2 Ni* t /2 re-delays the input 吋 clock, ie T' ₂ = 2 ^ * _t , correspondingly, that is, using 2 delay units to delay the input 吋 clock, and so on, until the input 吋 and The output clock is aligned and the output is clocked by the input chirp. Then, the value of i is 1 to N1, that is, the operation of the input chirp and the output chirp can be realized by performing N operations at most. In some embodiments, in step S101, a binary control signal C" may be generated according to a preset rule. According to the generated binary control signal C i, the delay line is controlled to delay the input clock by T i if the input clock lag is input in step S102. After outputting the clock, the binary control signal C _{i+1 is} regenerated, and the delay line is controlled to delay the input clock delay T i ₊₁ according to the regenerated binary control signal C _i+1 ; if the input clock is advanced in step S102 inch clock output, regenerate binary control signals C _{'i + 1,} a binary control signal to regenerate C' _{i + 1} re-controlled delay line delaying the input clock inch T _{'i + 1.}

[0037] Preferably, the binary control signal C i includes N bits, and the number from the highest bit to the lowest bit is numbered from 1 to N, that is, i ranges from 1 to N-1.

[0038] Preferably, the initial control unit generates a binary control signal d and a binary control signal in step S101. The first bit (ie, the highest bit) of the bit is 1, and the remaining bits are 0. According to the binary control signal d, the control delay line delays the input 吋 clock, and if the input 吋 clock in S102 lags the output 吋 clock, it is regenerated. Binary control signal C _i+1 , binary control signal C ₁₊₁ compared to binary control signal C i

The i-th bit remains 1, i + 1-bit is converted to 1, the other bits unchanged; The regenerated binary control signal C _{i + 1} re-controlled delay line delaying the input clock inch T _{i + 1;} if input in S102 The cuckoo clock is ahead of the output cuckoo clock. Then regenerating the binary control signal _C'i+1 , the binary control signal _C'i+1 is converted to 0 compared to the binary control signal C i, the i+1th bit is changed to 1, and the remaining bits are unchanged; Generated binary control signal

C ₁₊₁ controls the delay line to delay the input chirp by T' _i+1 .

[0039] The present invention also provides a chirp clock delay device for implementing the above-described chirp delay method. As shown in Fig. 1, as an embodiment, the chopper delay device 1 includes a delay processing unit 11 and a comparison processing unit 12, wherein

[0040] The delay processing unit 11 is mainly used to delay the input chirp clock by T i through the delay line to obtain an output chirp; after the comparison result of the comparison processing unit 12 is that the input chirp is delayed by the output chirp, The input clock is delayed by T _i+1 by a delay line, ₁₊₁ is (T _i+ T _x ) 12, and an output clock is obtained; the comparison result of the comparison processing unit 12 is that the input clock is ahead of the output. Under the condition of the 吋 clock, the input 吋 clock is delayed by T' _i+1 through the delay line, ₁₊₁ is (T _{y +} T i ) 12, and the output 吋 clock is obtained; until the input 吋 clock and the output 吋 clock Align, output the output chirp that is aligned with the input chirp; 1\ is 1 to 1\ and T, the one that is larger than T i and closest to T i , T _y is T, to D and 0 T i is small and the closest to T i , T is the maximum delay of the delay line;

[0041] The comparison processing unit 12 is mainly used to compare the input chirp and the output chirp.

[0042] Preferably, the initial value of T i is T ^ T / ² .

[0043] Preferably, the delay line comprises 2 delay units, each delay unit has a delay of t, and T is 2 N gas T! 3⁄42 ^{N 1} *to

[0044] In some embodiments, the delay processing unit 11 includes a control signal generation module and a processing sub-unit delay, wherein the control signal generating means for generating a N-bit bytes of binary control signal C in accordance with a preset _rule;; delay The processing subunit is configured to control the delay line to delay the input clock by T according to the binary control signal C i generated by the control signal generating module.

[0045] In some embodiments, the control signal generation module is specifically configured to initially generate a binary control signal C _{1 ; a} binary control signal. The highest bit of , is 1 and the remaining bits are 0; the delay processing sub-unit is specifically for generating the binary control signal C ₁ generated by the control signal according to the control signal _{; and} controlling the delay line to delay the input clock by T, . Further, the control signal generating module is further configured to regenerate the binary control signal C _i+1 and the binary control signal C _i+1 under the condition that the comparison result of the comparison processing unit 12 is that the input clock lags the output clock. Compared with the binary control signal C i , the i-th bit remains at 1, the i+1th bit is changed to 1, and the remaining bits are unchanged; The comparison result of the comparison processing unit 12 is that the input clock is ahead of the output clock, and the binary control signal _{C'i+1 is} regenerated, and the binary control signal C'1 _{+1 is} compared to the binary control signal Ci. The bit is transformed into 0, the i+1th bit is converted to 1, and the remaining bits are unchanged. The delay processing subunit is further configured to control the delay line to re-enter the input according to the binary control signal C1 ₊₁ regenerated by the control signal generating module. Clock delay T _i+1 ; controlling the delay line according to the binary control signal c' _i+1 regenerated by the control signal generating module to delay the input clock delay T'_i+1; wherein the binary control signal C i is from the highest bit The lowest digit is numbered from 1 to N, and the value of i ranges from 1 to Nl.

[0046] The present invention also provides a delay phase locked loop for implementing the above-described chirp delay method. As an embodiment, the delay phase locked loop includes: a logic control unit, a delay line control unit, and a phase discrimination unit, where

[0047] the logic control unit is configured to generate a binary control signal C according to a preset rule _; and regenerate the binary control signal C _i+1 under the condition that the comparison result of the phase detecting unit is that the input clock lags behind the output clock _; phase comparison result to the unit ahead of the input clock inch inch clock output conditions, to regenerate the binary control signal C _{'i + 1;}

[0048] The delay line control unit is configured to control the delay line to delay the input clock by T i according to the binary control signal C i generated by the logic control unit to obtain an output clock; the binary control signal ^ ₊₁ regenerated according to the logic control unit Controlling the delay line to re-input the input clock delay T _i+1 , ^ ₊₁ is (T _i+ T _x ) 12, and obtaining an output chirp; according to the binary control signal C' ₁₊₁ regenerated by the logic control unit The delay line re-intermits the input chirp clock by T' _i+1 , ₁₊₁ is (T _y + T i ) 12, and the output chirp is obtained; until the input chirp and the output chirp are aligned, the output and the input are The output clock of the 吋 clock alignment; where 1\ is 1 to 1\ and T, which is larger than T i and closest to T i , T _y is T !3⁄4T i and 0 is smaller than T i and distance T i is the nearest one, τ is the maximum delay of the delay line;

[0049] The phase detecting unit is configured to compare the input clock and the output clock, and output the comparison result to the logic control unit

[0050] Preferably, the initial value of T i is T! Is T /2.

[0051] Preferably, the delay line includes two delay units, each delay unit has a delay of t, and T is 2 N gas T! 3⁄42 ^{N 1} *to

[0052] Preferably, the logic control unit is specifically configured to generate a binary control signal C, a binary control signal, including an N-bit byte. , the highest bit is 1, and the remaining bits are 0; the delay line control unit is specifically used according to The binary control signal C ₁ generated by the logic control unit _; controlling the delay line to delay the input clock Τ [0053] Preferably, the binary control signal C _i+1 is maintained at 1 compared to the binary control signal C i , the first bit The i+1 bit is transformed to 1, and the remaining bits are unchanged; the binary control signal _C'i+1 is converted to 0 by the i-th bit of the binary control signal C i

The i+1 bit is converted to 1, and the remaining bits are unchanged. The binary control signal C i is numbered from 1 to N from the highest bit to the lowest bit, and i ranges from 1 to N-l.

The present invention also provides a digital chime management unit comprising the cuckoo clock delay device or the delay phase locked loop provided by the present invention.

[0055] The structure and working principle of the delay phase locked loop provided by the present invention are further described in detail below by way of example. As shown in FIGS. 2 and 3, the delay phase locked loop includes a logic control unit (SAR).

Logic 41. Multi-channel gate (MUX, used as delay line control unit) 42. Phase detector (PD, used as phase-detection unit) 43, Also includes delay line (44), latch (RS)

Latch) 45 and NOR gate, the internal structure of each component and the connection relationship between the components are as follows:

[0056] The delay line 44 includes two delay units (delay unit 1 to delay unit 2, the delay period of each delay unit, that is, the unit delay time is t, and the input clock CLKIN passes the delay unit 1 to obtain a delay 吋1. After the delay unit 1 and the delay unit 2, the delay clock 2 is obtained. After the delay unit 1 to the delay unit 2 -1, the delay clock 2 N-1 is obtained, and after the delay unit 1 to the delay unit 2, the delay clock is obtained. 2, delay 吋1, delay 吋2 2...delay 吋2 2 Between each adjacent two delay 吋, one unit delay 吋, t, delay line 44, maximum delay 吋2 The initial delay of the gas delay line 44 is ^T ^2 Ni*t;

[0057] The multiplexer 42 is configured to select one of the delay clocks 1 to the delayed clocks 2 as the output clock CLKOUT according to the binary control signal C i input from the logic control unit 41, and input CLKOUT to the phase detector 43. ;

The phase detector 43 compares the phase of CLKIN and the CLKOUT output from the multiplexer 42, and outputs the phase-detecting positive output signal PD_OUTP and the phase-detecting negative output signals PD_OUTN, PD_OUTP and PD_OU TN to the lock according to the comparison result. The output of the memory device 45 and the NOR gate, the NOR gate is a lock (LOCK) signal, and the output of the NOR gate is input to an inverter. The output of the inverter is a reset (RST) signal, and the RST signal output. To the logic control unit 41;

[0059] The latch 45 generates a latch output signal DIN according to PD_OUTP and PD_OUTN input from the phase detector 43 and outputs it to the logic control unit 41; the latch 45 is a NOR gate structure, and if PD_OUTP exhibits a high level 1吋 DIN is high 1; if PD_OUTN is high 1 day, DIN is 0, if PD_OUTP and PD_OUT

N is the same as 0, DIN keeps the last triggered value;

[0060] The logic control unit 41 is a single pulse generator, and its structure is as shown in FIG. 3, including N+1 D flip-flops 1, N D flip-flops 2, N D flip-flops 3, and also includes N connections. a delay module between adjacent D flip-flops 1, and N OR gates connected between D flip-flop 2 and D flip-flop 3, wherein N+1 D flip-flops 1 are triggered by rising edges, with reset The reset terminal is reset to 0, and the N D flip-flops 2 are triggered by the rising edge. There is a reset terminal, the reset terminal is connected to 0吋, and the N D flip-flops 3 are triggered by the rising edge. From the left, the three inputs of the first D flip-flop 1 are respectively connected to a high potential 1 (here can be connected to the power supply by connecting a resistor in series, or by other means to obtain a high level), CLKIN, the above RST signal, The output of one D flip-flop 1 is connected to the inverter and the delay module in turn, and then to one input of the second D flip-flop 1, and the other two inputs of the second D flip-flop 1 are respectively connected to CLKIN. RST signal, the output of the second D flip-flop 1 is connected to one input of the third D flip-flop 1 through another delay module, and the output of the second D flip-flop 1 is also connected. To the input of the first D flip-flop 2 and one input of the first OR gate; the other two inputs of the first D flip-flop 2 are respectively connected to the DIN and RST signals, the first D flip-flop 2 The output terminal is connected to the other input terminal of the first OR gate; the output end of the first OR gate is connected to the input end of the first D flip-flop 3, and the other input terminal of the first D flip-flop 3 is connected to the LOCK signal. The output of the first D flip-flop 3 outputs binary control C i is the highest bit number (i.e., 1 bit); and so on. The delay unit and the delay unit (delay unit 1 to delay unit 2 N) in the delay line 44 may have the same structure, but the unit delay time is smaller than the delay unit.

[0061] The working principle of the delay phase locked loop of this structure is as follows:

[0062] When the RST signal is 0吋, all the D flip-flops in the logic control unit 41 are cleared to zero, and the binary control signal C i including the N-bit byte and the trigger output 1 to the trigger output N are both 0;

[0063] When the RST signal becomes 1吋, after the CLKIN is input, the highest bit conversion of the binary control signal C i is first started, that is, the highest bit (ie, the first bit) is set to 1, and the other bits remain at 0. Generate binary control signals

C is 100...00, which is sent to the multiplexer 42, and the multiplexer 42 selects the delay 2 2 ^N as the input from the delay 吋 1 to the delayed 2 2, that is, delays 2 N for the CLKIN ¹

*t as CLKOUT, phase detector 43 will phase the CLKOUT and CLKIN. If the phase of CLKIN lags behind CLKOUT, the delay 2 ^{N 1} *t is not enough. As shown in Figure 4, PD_OUTP outputs a high level. PD_OUTN outputs a low level, PD_OUTP and PD_OUTN pass through the latch 45 and the output DIN is 1 and is sent to the logic control unit 41. The logic control unit 41 generates a binary control signal C ₂ , that is, on the basis of the highest bit (ie, The first bit) is reserved as 1, the second highest bit (ie, the second bit) is converted to 1, and the remaining bits are unchanged, that is, C ₂ is 110...00; if CLKIN is ahead of CLKOUT, as shown in Figure 5, PD_OUTN is output. High level, PD_OUTP output low level, PD_OUTP and PD_OUTN pass the output DIN of the latch 45 is 0, the logic control unit 41, the logic control unit 41 generates a binary control signal C' ₂ , that is, on the C ^ basis, the highest bit (ie, the first bit) becomes 0, the next highest bit (ie, the second bit) is converted to 1, and the remaining bits are unchanged, that is, C' ₂ is 010...00; if the phase difference between CLKIN and CLKOUT is in the phase detector 43 Within the phase discrimination accuracy, that is, phase alignment, as shown in FIG. 6, the PD_OUTP and PD_OUTN of the phase detector 43 are both 0. After inputting to the NOR gate, the LOCK signal of the DLL becomes 1, and it is determined that the DLL is locked.吋Lock signal control logic control unit 4 1 D flip-flop 3 flips, locks the current value of C i That 100 ... 00;

The above binary control signal C ₂ or C' ₂

It is again sent to the multiplexer 42; taking the binary control signal C ₂ input to the multiplexer 42 as an example, the multiplexer 42 selects the delay cesium from the delay 吋 1 to the delayed 2 2 N ( 2 N- ₁₊ 2 N) /2 as the input, that is, the CLKIN delay (2 ^Ν - '+2 ^Ν ) *t /2 as CLKOUT, the phase detector 43 discriminates the CLKOUT and CLKIN; if CLKIN The phase still lags behind CLKOUT, indicating that the delay (2 NI ₊ 2 N ) *t /2 is not enough.

PD_OUTP output high, PD_OUTN output low, and PD_OUTN PD_OUTP the DIN 45 via the output latch to 1, to the logic control unit 41, the logic control unit 41 generates a binary control signal C _3, i.e. the C ₂ On the basis of the second highest position (ie the second place) is reserved as 1,

The next bit of the next highest bit (ie, the third bit) is changed to 1, and the remaining bits are unchanged. ₃ is 111...00; the binary control signal C _{3 is} again supplied to the multiplexer 42, and the multiplexer 42 selects the delay 吋 clock from the delay 吋 1 to the delayed 2 2 2 [(2 -i+ 2 ^N ) / 2 + 2 ^N ] / 2 as the input, that is, the delay of CLKIN [(2 ^{N 1} + 2 ^N ) / 2 + 2 ^N ] * t /2 as CLKOUT, and so on; if the phase of CLKIN is ahead At CLKOUT, the delay (2 N- i+2 N) * _t /2 is too large, PD_OUTP outputs low level, PD_OUTN outputs high level, PD_OUTP and PD_OUTN pass the latch 45 after the output DIN is 0, send to the logic control unit 41, the logic control unit 41 generates a binary control signal C _'3, C ₂ that is based on the highest order bit (i.e., bit 2) is converted into 0, the second after a high-order (ie 3) Change to 1, the remaining bits are unchanged. ' ₃ is 101...00; binary control Signal C _'3 again conveyed up to mux 42, mux 42 selects the clock delay inch [(2 -i + 2 N) / 2 + 2 Ν clock 1 inch from the delay to the delay clock inches in 2 N - Ψ2 as the input, that is, the CLKIN delay [(2 ^{Ν 1} +2 ^Ν ) / 2 + 2 ^Ν - ¹ ] * t /2 as CLKOUT, and so on; if the phase difference between CLKIN and CLKOUT is in the phase detector 43 Within the phase discrimination accuracy, that is, the phase alignment, the PD_OUTP and PD_OUTN of the phase detector 43 are both 0. After inputting to the NOR gate, the LOCK signal of the DLL becomes 1, and it is determined that the DLL is locked. The 吋 lock signal control logic control unit The D flip-flop 3 in 41 flips, latching the current value of C ₂ , ie 110...00; and so on.

[0065] The present invention implements alignment by means of a two-point successive approximation, which reduces the need for a maximum of 2 ^N chirp cycles to a maximum of N chirps compared to the prior art method of increasing or decreasing unit delays one by one. The cycle, when the input chord and the output cesium are greatly different, accelerates the locking speed of the DLL and improves the working speed of the chip system. The present invention also designs a generation mechanism of the binary control signal C i . According to the mechanism designed by the present invention, the generated binary control signal C i is not aligned with the input chirp clock after the delay T i . The delay of the delay line can be accurately controlled to achieve the alignment of the above-described two-division successive approximation. Correspondingly, the circuit structure of the logic control unit designed by the invention can be realized only by a small number of flip-flops, and the output directly controls the delay line, which is composed of a shift register, a Gray code converter and a Gray code decoder. Compared with the logic control unit, the structure is simpler, the technical difficulty is small, and the risk is low.

[0066] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed in multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in a storage medium (ROM/RAM, disk, optical disk) by a computing device, and at some In some cases, the steps shown or described may be performed in an order different from that described in the above embodiments, or they may be separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof may be fabricated into a single integrated circuit module. to realise. Therefore, the invention is not limited to any specific combination of hardware and software.

The above is a further detailed description of the present invention in connection with the specific embodiments, and the specific embodiments of the invention are not limited to the description. It will be apparent to those skilled in the art that the present invention may be practiced without departing from the spirit and scope of the invention.

Claims

Claim

[Claim 1] A chirp clock delay method, comprising:

Step 1. Delay the input chirp by delay line T "to get the output clock;

Step 2: Comparing the input chirp clock and the output chirp clock, if the input chirp clock lags the output chirp clock, return to step one, and delay the input chirp clock by T _i+1 , T _i again through the delay line. ₊₁ is (T _i+ T _x ) 12, if the input clock is ahead of the output clock, it returns to step one, and the input delay is delayed by T' _i+1 through the delay line, ₁₊₁ is (T _{y +} T i ) /2; until the input chirp and the output chirp are aligned, outputting an output chirp aligned with the input chirp; wherein, ! ^For! ^ to! ^ and Ding Zhong, than! ^ Big and distance! ^The nearest one, 1 is 1 to T i and 0 is smaller than T i and is closest to T i , and T is the maximum delay of the delay line.

The initial value of [Claim 2] inch of the clock delay method as claimed in claim 1, characterized in that, as the working ^ 1 ₁

II.

[Claim 3] The cuckoo clock delay method according to claim 2, wherein the delay line includes 2 N delay units, each of which has a delay of t and T of 2 N*t, 1\ is 2 ^.

[Claim 4] The cuckoo clock delay method according to claim 3, wherein step one comprises:

Generating a binary control signal C _i including N bits according to a preset rule _;

Based on the generated binary control signal C i , the delay line is controlled to delay the input clock by T i .

[Claim 5] The cuckoo clock delay method according to claim 4, wherein step one comprises:

Initially, a binary control signal d, a binary control signal is generated. The highest bit of , is 1, and the remaining bits are 0; according to the binary control signal d, the delay line is controlled to input the clock delay TV

[Claim 6] The cuckoo clock delay method according to claim 5, wherein the step 1 further comprises: if the input chirp clock lags the output cuckoo clock in the second step, regenerating the binary control signal C _{i+ 1} , the binary control signal C ₁₊₁ is kept at ₁ compared to the binary control signal C i , the i+1th bit is changed to 1, and the remaining bits are unchanged; the control is controlled according to the regenerated binary control signal C _i+1 The delay line re-intermits the input chirp clock by T _i+1 ;

If the input clock is ahead of the output clock in step two, the binary control is regenerated. The signal C' _i+1 , the binary control signal C' ₁₊₁ is converted to 0 compared to the binary control signal C i , the i+1th bit is changed to 1, and the remaining bits are unchanged; according to the regenerated binary control The signal C' ₁₊₁ controls the delay line to delay the input clock by T'_i+1;

The binary control signal C i is numbered from 1 to N from the highest bit to the lowest bit, and the value of i ranges from 1 to N-l.

A chopper delay device, comprising:

a delay processing unit, configured to delay the input chirp clock by 1⁄4 through the delay line to obtain an output chirp clock; and after the comparison processing unit compares the result that the input chirp clock lags the output chirp clock, re-pass the delay line The input chirp clock delay T _i+1 , ^ ₊₁ is (T _i+ T _x ) 12, and the output chirp clock is obtained; under the condition that the comparison processing unit compares the input clock before the output chirp clock, The input chirp clock is delayed by T' _i+1 through the delay line, and T' _i+1 is (Τ _γ + Τ\ ) 12 to obtain an output chirp; until the input chirp and the output chirp are aligned, the output is The input chirp-aligned output chirp clock; wherein, 1\ is 1 to 1\ and the middle, the one that is larger than T i and the closest to the distance T i , T _y is T, and the ratio of T i to 0 is T i Small and the closest to T i , T is the maximum delay of the delay line;

A comparison processing unit is configured to compare the input clock and the output clock.

Inch bell according to claim 7 delay means, wherein an initial value of ₁₁ to ₁₁ as the working II.

The chopper delay device according to claim 8, wherein said delay line comprises 2 N delay units, each of which has a delay of t, T is 2 N*t, and 1\ is 2^. . The sinusoidal delay device of claim 9, wherein the delay processing unit comprises a control signal generating module for generating a binary control signal C _i comprising N bits according to a preset rule _;

a delay processing sub-unit for generating a binary control signal generated by the module according to the control signal

C i, controlling the delay line delays the input clock by T i .

A chopper delay device according to claim 10, wherein

The control signal generating module is specifically configured to generate a binary control signal C ₁ initially _; control signal. The highest bit of , is 1, and the remaining bits are 0;

The delay processing sub-unit is specifically configured to control the delay line to delay the input clock by T according to the binary control signal d generated by the control signal generating module.

[Claim 12] The cuckoo clock delay device according to claim 11, wherein

The control signal generating module is further configured to regenerate the binary control signal C _i+1 under the condition that the comparison result of the comparison processing unit is that the input clock lags the output cesium clock, and the binary control signal C _{1+1 is} compared with the binary control The i-th bit of the signal C i is kept at 1, the i+1th bit is changed to 1, and the remaining bits are unchanged; and the binary control is regenerated under the condition that the comparison processing unit compares the input clock before the output cesium clock The signal c' _i+1 , the binary control signal c' _i+1 is converted to 0 compared to the binary control signal C i , the i+1th bit is converted to 1, and the remaining bit invariant delay processing subunit is further used according to The binary control signal C ₁₊₁ regenerated by the control signal generating module controls the delay line to delay the input clock delay T _i+1 ; the binary control signal c′ _i+ ≤ generated by the control signal generating module is ≤ the delay line Re-input the input clock by T'_i+1;

[Claim 13] A delay phase locked loop, comprising:

a logic control unit, configured to generate a binary control signal C _i according to a preset rule _; and regenerate the binary control signal C _i+1 under the condition that the input phase lags behind the output cesium clock; The comparison result of the phase detecting unit is that the input clock is ahead of the output clock, and the binary control signal _{C'i+1 is} regenerated; the delay line control unit is used for the binary control signal C i generated according to the logic control unit. The control delay line delays the input chirp clock T i to obtain an output chirp clock; the delay line re-generates the input chirp delay T i ₊₁ according to the binary control signal regenerated by the logic control unit, 1 ₁₊₁ is (T _i+ T _x ) 12, the output clock is obtained; the delay line is re-generated according to the binary control signal C' ₁₊₁ regenerated by the logic control unit, and the input clock is delayed by T' _i+1 , 1^ ₊₁ is (T _y + T i ) 12, get the output 吋 clock; until the input 吋 clock and output 吋 Clock alignment, outputting an output chirp aligned with the input chirp; wherein 1\ is 1 to 1\ and T, which is larger than T i and closest to T i , T _y is T !3⁄4T i and 0 a medium that is smaller than T i and closest to Ti, and T is the maximum delay of the delay line;

A phase detector unit for comparing the input clock and the output clock, and outputting the comparison result to the logic control unit.

The delay locked loop as claimed in claim 13, wherein an initial value of 1 ₁ 1 ₁ D / 2 delay locked loop as claimed in claim 14, wherein said delay line comprises 2 ^ Delay units, each delay unit has a delay of t, and τ is 2 ^N *t, τ ^2 ^Ν . The delay phase locked loop of claim 15 wherein:

The logic control unit is specifically configured to generate a binary control signal C including a clamp byte.

, binary control signal. The highest bit of , is 1, and the remaining bits are 0;

The delay line control unit is specifically configured to control the delay line to delay the input clock according to the binary control signal C generated by the logic control unit.

The delay phase locked loop of claim 16 wherein:

The binary control signal C ₁₊₁ is kept at ₁ compared to the binary control signal C i , the i+1 bit is changed to 1, and the remaining bits are unchanged;

The binary control signal _C'i+1 is converted to 0 by the i-th bit of the binary control signal C i, and the i+1th bit is converted to 1, and the remaining bits are unchanged;

A digital cuckoo clock management unit, comprising the cuckoo clock delay device according to any one of claims 1 to 12, or the delay phase locked loop according to any one of claims 13 to 17.