CN112165314A - Frequency-adjustable clock generation unit in FPGA chip - Google Patents
Frequency-adjustable clock generation unit in FPGA chip Download PDFInfo
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- CN112165314A CN112165314A CN202011021876.6A CN202011021876A CN112165314A CN 112165314 A CN112165314 A CN 112165314A CN 202011021876 A CN202011021876 A CN 202011021876A CN 112165314 A CN112165314 A CN 112165314A
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- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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Abstract
The invention discloses a clock generation unit with adjustable frequency in an FPGA chip. The clock generation unit includes: an input selector comprising a clock enable terminal, an input selector input terminal, and an input selector output terminal; a lookup table comprising a lookup table input and a lookup table output; a delay chain comprising a delay chain input and n delay chain outputs, each delay chain output having a different delay relative to the delay chain input; and the delay selector comprises a delay selection end, n delay selector input ends and a delay selector output end, and the n delay selector input ends are respectively connected with the n delay chain output ends. The clock generation unit of the invention utilizes the input selector, the lookup table, the delay chain and the delay selector to obtain a stable clock signal with adjustable frequency.
Description
Technical Field
The invention relates to the field of FPGA (field programmable gate array) chips, in particular to a clock generation unit with adjustable frequency in an FPGA chip.
Background
With the continuous development of semiconductor technology, FPGA chips have been widely introduced in many fields such as artificial intelligence, big data analysis, cloud computing, network communication, image processing, robots, chip verification, and the like. In some fields, FPGA chips are even replacing the position of CPU, GPU or DSP, becoming the dominant chip. However, the use of FPGA chips from hardware circuits to logic designs requires very specialized techniques, and serious errors may occur due to slight carelessness, resulting in the failure of the entire system to work properly. Among the many factors that render an FPGA chip inoperable, it is the most common problem that no effective clock is available inside the FPGA due to hardware design defects. Therefore, how to provide a proper reference clock for the FPGA on the basis of the existing hardware becomes a problem to be solved urgently.
Aiming at the problem that the existing hardware FPGA is lack of a reference clock, at present, three solutions are mainly provided. The first solution is a hardware revamp scheme. The hardware-revising scheme provides a reference clock to the FPGA by redesigning and manufacturing the FPGA hardware. Since this solution requires redesign and remanufacture of the hardware, the solution is long to implement, costly, and may introduce other risks during the remanufacturing process. The second solution is a hardware repair solution. The hardware maintenance scheme provides a reference clock for the FPGA in modes of flying wires and the like, so certain hardware maintenance cost needs to be invested. The flying wire mode requires that the hardware board card has a corresponding reference clock source, and the special clock pin of the FPGA needs to have a flying wire leading-in point, which are not available. In addition, secondary damage to hardware is easily caused in the flying wire process, and the reliability of a clock introduced through flying wire maintenance cannot be guaranteed. A third solution uses other interface analog clock signals in communication with the FPGA to clock the FPGA. The scheme not only requires an interface which is arranged outside the FPGA and is communicated with the FPGA, but also requires the communication interface to simulate the clock, and meanwhile, a pin of the simulation clock is required to be connected to a special pin of the FPGA clock. The third solution has high requirements on hardware environment and cannot meet the requirements generally. In addition, this solution also fails to guarantee the reliability of the clock.
In view of the above problem, the applicant proposed in another patent application a clock unit within an FPGA chip capable of stably and reliably generating a clock signal of a fixed frequency inside the FPGA chip. However, in some usage scenarios, FPGA chips require clock signals of different frequencies in order to meet the requirements of different applications.
Therefore, there is a need to provide an economical and reliable solution that is capable of providing a frequency tunable reference clock for an FPGA chip.
Disclosure of Invention
In view of the above, the present invention provides a clock generation unit with adjustable frequency in an FPGA chip, which can solve the above technical problems.
The technical scheme of the invention is as follows:
a frequency tunable clock generation unit within an FPGA chip, comprising:
an input selector comprising a clock enable terminal, an input selector input terminal, and an input selector output terminal;
a lookup table comprising a lookup table input and a lookup table output, the lookup table configured to: when the input end of the lookup table is at a low level, the output end of the lookup table outputs a high level, and when the input end of the lookup table is at a high level, the output end of the lookup table outputs a low level;
the delay chain comprises a delay chain input end and n delay chain output ends, wherein n is a positive integer, and each delay chain output end has different delay relative to the delay chain input end;
a delay selector, including a delay selection terminal, n delay selector input terminals and a delay selector output terminal, where the n delay selector input terminals are respectively connected to the n delay chain output terminals, and the delay selector is configured to output a level of one of the n delay selector input terminals at the delay selector output terminal according to a signal input by the delay selection terminal;
wherein the input selector input is connected to the delay selector output, the input selector output is connected to the lookup table input, the lookup table output is connected to the delay chain input, and the input selector is configured to: and when the clock enable terminal is at a high level, the input selector output terminal outputs the level of the input selector input terminal.
According to a preferred embodiment of the present invention, an ith delay chain output terminal of the n delay chain output terminals has a delay D with respect to the delay chain input terminalDCiWherein i is a positive integer less than or equal to n.
According to a preferred embodiment of the invention, the look-up table output is further connected to a clock output.
According to a preferred embodiment of the present invention, a clock buffer is connected between the output terminal of the lookup table and the clock output terminal.
According to a preferred embodiment of the present invention, the input selector output has an input selector delay D with respect to the input selector inputISThe output end of the lookup table has a lookup table delay D relative to the input end of the lookup tableLUTSaid delay selector output having a delay D with respect to said delay selector inputDSWhen the output end of the delay selector outputs the level of the input end of the ith delay selector, the period of the clock signal output by the clock output end is T-2 (D)DCi+DDS+DIS+DLUT)。
According to a preferred embodiment of the present invention, the frequency of the clock signal is 1/(2 (D)DCi+DDS+DIS+DLUT))。
According to a preferred embodiment of the present invention, the delay chain includes n delay units connected in series, each delay unit generates a delay t, the n delay chain output terminals are respectively connected to the output terminals of the n delay units, and the ith delay chain output terminal is delayed with respect to a delay D of the delay chain input terminalDCi＝i×t。
An FPGA chip implementing a frequency tunable clock generation unit according to the above description.
According to the technical scheme, the clock generation unit with adjustable frequency in the FPGA chip obtains a stable clock signal with adjustable frequency by utilizing the input selector, the lookup table, the delay chain and the delay selector. The clock generation unit of the invention does not need to change or maintain the FPGA on hardware, not only can save the cost caused by hardware version change or hardware maintenance, but also can avoid the risk caused by hardware version change or hardware maintenance, and is an economic and reliable solution.
Drawings
The disclosure of the present invention will become more readily understood with reference to the accompanying drawings. It is easily understood by those skilled in the art that these drawings are only for illustrating the technical solutions of the present invention and are not intended to limit the scope of the present invention. In the figure:
fig. 1 is a schematic structural diagram of a clock generation unit with adjustable frequency in an FPGA according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic structural diagram of a clock generation unit with adjustable frequency in an FPGA according to an embodiment of the present invention. As shown in fig. 1, the clock generation unit includes an input selector, a lookup table, a delay chain, and a delay selector.
In this embodiment, the input selector includes an enable terminal, an input selector input terminal, and an input selector output terminal. The signal from the selector input to the selector output will cause a selector delay DIS. The input end of the input selector is connected with the output end of the delay selector, and the output end of the input selector is connected with the input end of the lookup table. The input selector is configured to: when the clock enable end is at low level, the output end of the input selector outputs low level; when the clock enable terminal is at a high level, the input selector output terminal outputs the level of the input selector input terminal. To achieve the above configuration, the other input terminal of the input selector may be connected to a constant low-level signal. When the clock enable terminal is at a low level, the input selector output terminal may output a constant low level signal at the other input terminal. In the present embodiment, the low level signal represents a logic "0", and the high level signal represents a logic "1".
In this embodiment, the look-up table includesA lookup table input and a lookup table output. The signal from the input of the lookup table to the output of the lookup table will generate a lookup table delay DLUT. The input end of the lookup table is connected with the output end of the input selector, and the output end of the lookup table is connected with the input end of the delay chain. As shown in fig. 1, the lookup table includes two columns, where the left column a represents the input level of the lookup table, and the right column b represents the output level of the lookup table. When the look-up table input is a logic "0" (i.e., low), the look-up table output outputs a logic "1" (i.e., high). Conversely, when the input of the lookup table is logic "1" (i.e., high), the output of the lookup table outputs logic "0" (i.e., low). It can be seen that the look-up table implements the function of an inverter, i.e. changing an input high level to an output low level and an input low level to an output high level. In this embodiment, the look-up table output is connected to the clock output for outputting the clock signal. Preferably, a clock buffer is further connected between the output end of the lookup table and the clock output end, so as to enhance the load capacity of the clock generation unit and reduce the interference and influence of the load on the clock generation unit.
In this embodiment, the delay chain includes a delay chain input terminal and n delay chain output terminals, where n is a positive integer. Each delay chain output has a different delay relative to the delay chain input. The ith delay chain output end of the n delay chain output ends has a delay D relative to the delay chain input endDCiWherein i is a positive integer less than or equal to n. As shown in fig. 1, the delay chain comprises n delay cells, each delay cell producing a delay t. And the output ends of the n delay chains are respectively connected with the output ends of the n delay units. Thus, the delay D of the ith delay chain output relative to the delay chain inputDCiI × t. It can be seen that the higher the order of the delay chain outputs, the longer the delay that is produced. According to this embodiment, the delays at the output ends of the delay chains are sequentially increased by taking t as a unit, and the delay at the output end of the last first delay chain is nxt. It should be understood that the delay at the output of each delay chain may be arbitrarily set as desired. The delay between the outputs of the delay chains can be adjusted, for example, by adjusting the number of delay elements between adjacent delay chain outputsAnd (5) delaying.
In this embodiment, the delay selector includes a delay selection terminal, n delay selector input terminals, and a delay selector output terminal. The delay selector outputs having a delay D with respect to each delay selector inputDS. And the input ends of n delay selectors of the delay selectors respectively correspond to the output ends of the n delay chains one by one and are connected with each other. Therefore, the levels of the n delay chain output terminals are respectively input to the n delay selector input terminals of the delay selector. The signal input from the delay selector terminal may select a level of one of the delay selector input terminals as an output of the delay selector output terminal. For example, when the signal input from the delay selector terminal represents i (i is a positive integer less than or equal to n), the level of the ith delay selector input terminal may be output to the delay selector output terminal. It can be seen that according to the present embodiment, the delay selector is configured to output the level of one of the n delay selector input terminals at the delay selector output terminal according to the signal input at the delay selector input terminal. Since each delay selector input has a different delay relative to the delay chain input, the delay of the delay selector output can be adjusted by adjusting the signal input by the delay selector.
The specific steps of generating the clock signal by the tunable frequency clock generation unit according to the present invention will be described dynamically with reference to fig. 1. In the following description, it is assumed that the output terminal of the delay selector outputs the level of the input terminal of the ith delay selector. In addition, in the following description, a binary number 0 represents a logical "0" (i.e., low level), and a binary number 1 represents a logical "1" (i.e., high level).
1) When the clock enable is 0 (i.e., clock enable is off), the selector outputs a constant value of 0. At this time, the input end a of the lookup table is constant 0, and the output end b of the lookup table is constant 1.
2) When the clock enable terminal becomes 1 (i.e. the clock enable is turned on), the input selector output terminal outputs 1, the lookup table input terminal a is 1, and the lookup table output terminal b is 0.
3) The 0 value at the output b of the lookup table is then delayed by i t (i.e., D) through the delay chainDCiAfter i × t), is subjected to stretchingThe time selector reaches the input selector input. Since the enable terminal is 1 at this time, the input selector output terminal outputs the value 0 of the input selector input terminal.
4) Since the look-up table input a is connected to the input selector output, the look-up table input a becomes 0 and the look-up table output b becomes 1.
5) The value 1 at the output of the lookup table is then delayed through the delay chain by i t (i.e., D)DCiI × t), and then through the delay selector to the input selector input. Since the enable terminal is 1 at this time, the input selector output terminal outputs the value 1 of the input selector input terminal.
6) Since the look-up table input a is connected to the input selector output, the look-up table input a becomes 1 and the look-up table output b becomes 0.
7) And repeating the steps 3 to 6, and outputting a stable clock signal at the output end b of the lookup table.
The clock generation unit according to the present embodiment generates a square wave clock signal in which 1 (high level) and 0 (low level) alternate through the above steps. When it is necessary to stop generating the clock signal, the clock enable terminal may be set to 0 (low level). At this time, the input end of the lookup table is at low level, and the output end of the lookup table is constantly at 1, so that the clock signals with 1 and 0 alternating are not generated any more.
It can be seen from the above steps that, the output end b of the lookup table needs to pass through the delay chain, the delay selector and the input selector from the value 1, and then becomes 0 after being inverted by the lookup table, and the time passed by the process is the delay D of the delay chainDCiDelay selector delay DDSInput selector delay DISAnd a look-up table delay DLUTSum, i.e. DDCi+DDS+DIS+DLUT. Then, a time D is further elapsedDCi+DDS+DIS+DLUTThe output b of the look-up table is then changed back from 0 to the value 1. It can be seen that the period of the clock signal output at the output of the look-up table is T-2 (D)DCi+DDS+DIS+DLUT). Since the frequency is equal to the reciprocal of the period, the frequency f of the clock signal output at the output of the look-up table is 1/(2 (D)DCi+DDS+DIS+DLUT). Due to DDCiIs selectable by delaying the input signal of the selection terminal, and thus can be changed by changing DDCiTo adjust the period or frequency of the clock signal. When the clock generation unit is designed, the delay range of the output end of the delay chain can be adjusted by increasing or decreasing the number of the delay units in the delay chain, so that the adjustment range of the clock period or the frequency of the clock generation unit is increased or decreased.
In this embodiment, the clock signal is generated from the look-up table output, since the clock output is connected to the look-up table output. It will be appreciated that in other embodiments the clock output may be connected to, for example, a look-up table input or a delay chain output, both of which may produce a stable clock output having the same period and frequency as the clock signal output from the look-up table output.
Under the condition that the existing hardware FPGA lacks a reference clock, the clock generation unit can be realized in the FPGA in a programming mode, so that a stable and reliable clock with adjustable frequency is provided for the FPGA.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A frequency tunable clock generation unit within an FPGA chip, comprising:
an input selector comprising a clock enable terminal, an input selector input terminal, and an input selector output terminal;
a lookup table comprising a lookup table input and a lookup table output, the lookup table configured to: when the input end of the lookup table is at a low level, the output end of the lookup table outputs a high level, and when the input end of the lookup table is at a high level, the output end of the lookup table outputs a low level;
the delay chain comprises a delay chain input end and n delay chain output ends, wherein n is a positive integer, and each delay chain output end has different delay relative to the delay chain input end;
a delay selector, including a delay selection terminal, n delay selector input terminals and a delay selector output terminal, where the n delay selector input terminals are respectively connected to the n delay chain output terminals, and the delay selector is configured to output a level of one of the n delay selector input terminals at the delay selector output terminal according to a signal input by the delay selection terminal;
wherein the input selector input is connected to the delay selector output, the input selector output is connected to the lookup table input, the lookup table output is connected to the delay chain input, and the input selector is configured to: and when the clock enable terminal is at a high level, the input selector output terminal outputs the level of the input selector input terminal.
2. The clock generation unit of claim 1, wherein an ith delay chain output of the n delay chain outputs has a delay D relative to the delay chain inputDCiWherein i is a positive integer less than or equal to n.
3. The clock generation unit of claim 2, wherein the look-up table output is further coupled to a clock output.
4. The clock generation unit of claim 3, wherein a clock buffer is connected between the look-up table output and the clock output.
5. The clock generation unit of claim 2, wherein the input selector output has an input selector delay D relative to the input selector inputISThe output end of the lookup table is opposite to the output end of the lookup tableThe input end of the lookup table is provided with a lookup table delay DLUTSaid delay selector output having a delay D with respect to said delay selector inputDSWhen the output end of the delay selector outputs the level of the input end of the ith delay selector, the period of the clock signal output by the clock output end is T-2 (D)DCi+DDS+DIS+DLUT)。
6. The clock generation unit of claim 5, wherein the clock signal has a frequency of f-1/(2 (D)DCi+DDS+DIS+DLUT))。
7. The clock generation unit of claim 6, wherein the delay chain comprises n delay units connected in series, each delay unit producing a delay t, the n delay chain outputs are connected to the outputs of the n delay units, respectively, and the i-th delay chain output is delayed with respect to the delay D of the delay chain inputDCi＝i×t。
8. An FPGA chip implementing the clock generation unit of any one of claims 1 to 7.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208994A (en) * | 2013-03-11 | 2013-07-17 | 东南大学 | Two-stage time digital convert (TDC) circuit |
| CN104579320A (en) * | 2014-12-26 | 2015-04-29 | 深圳市国微电子有限公司 | Clock delay method, clock delay device, delay-locked loop and digital clock management unit |
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- 2020-09-25 CN CN202011021876.6A patent/CN112165314A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208994A (en) * | 2013-03-11 | 2013-07-17 | 东南大学 | Two-stage time digital convert (TDC) circuit |
| CN104579320A (en) * | 2014-12-26 | 2015-04-29 | 深圳市国微电子有限公司 | Clock delay method, clock delay device, delay-locked loop and digital clock management unit |
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