CN113315493B - Clock calibration circuit and programmable logic chip - Google Patents
Clock calibration circuit and programmable logic chip Download PDFInfo
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- CN113315493B CN113315493B CN202110413808.2A CN202110413808A CN113315493B CN 113315493 B CN113315493 B CN 113315493B CN 202110413808 A CN202110413808 A CN 202110413808A CN 113315493 B CN113315493 B CN 113315493B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
Abstract
The application provides a clock calibration circuit and a programmable logic chip, relates to the technical field of integrated circuits, and aims to solve the problem of signal delay among a plurality of circuit units. The circuit comprises: the first delay circuit comprises a first delay unit and a first control circuit, and the first delay unit inputs a first output clock to the phase detector under the control of the first control circuit. The second delay circuit comprises a second delay unit and a second control circuit, and the second delay unit inputs a second output clock to the phase detector under the control of the second control circuit. The phase discriminator calculates the phase difference between the first output clock and the second output clock to obtain a comparison result, when the comparison result is larger than or equal to the phase threshold value, the comparison result is fed back to the first delay circuit and/or the second delay circuit, the first control circuit inputs a new first output clock to the phase discriminator according to the comparison result and/or the second control circuit inputs a new second output clock to the phase discriminator according to the comparison result until the new comparison result is smaller than the phase threshold value.
Description
Technical Field
The present disclosure relates to integrated circuit technology, and more particularly, to a clock calibration circuit and a programmable logic chip.
Background
The programmable logic chip includes a plurality of circuit units that can operate when a clock signal corresponding thereto arrives.
For a plurality of circuit units operating synchronously, the clock signals should be simultaneously reached. However, there is a delay between the circuit units that should be operated synchronously due to process, temperature, voltage, transmission paths of clock signals, etc.
Disclosure of Invention
The embodiment of the application provides a clock calibration circuit and a programmable logic chip to improve the problems.
In a first aspect, a clock calibration circuit is provided, the clock calibration circuit comprising: the phase detector comprises a first delay circuit, a second delay circuit and a phase detector, wherein the first delay circuit comprises at least one first delay unit and a first control circuit corresponding to the at least one first delay unit, and the at least one first delay unit inputs a first output clock to the phase detector under the control of the first control circuit. And the second delay circuit comprises at least one second delay unit and a second control circuit corresponding to the at least one second delay unit, and the at least one second delay unit inputs a second output clock to the phase detector under the control of the second control circuit. The phase discriminator calculates the phase difference between the first output clock and the second output clock to obtain a comparison result, when the comparison result is larger than or equal to a phase threshold value, the comparison result is fed back to the first delay circuit and/or the second delay circuit, the first control circuit controls at least one first delay unit to adjust the first output clock according to the comparison result so as to input a new first output clock into the phase discriminator, and/or the second control circuit controls at least one second delay unit to adjust the second output clock according to the comparison result so as to input a new second output clock into the phase discriminator until the phase difference between the new first output clock and the new second output clock is smaller than the phase threshold value.
In a second aspect, a programmable logic chip is provided, including a plurality of circuit units and the clock calibration circuit in the first aspect, where the circuit units include a clock output terminal; every two circuit units correspond to one clock calibration circuit, the input end of a first delay circuit of the clock calibration circuit is electrically connected with the clock output end of the corresponding circuit unit, and the input end of a second delay circuit is electrically connected with the clock output end of the corresponding circuit unit.
In the clock calibration circuit and the programmable logic chip provided by the embodiment of the application, the first delay circuit and the second delay circuit of the clock calibration circuit can be respectively and electrically connected with the clock output ends of the clock circuits in the two circuit units, are used for receiving clock signals of the clock circuits electrically connected with the clock circuits, adjusting the received clock signals, respectively sending the first output clock and the second output clock to the phase discriminator after adjusting the received clock signals, and after comparing the comparison result by the phase discriminator, if the comparison result is still greater than or equal to the phase threshold value, feeding back the comparison result to the first delay circuit and/or the second delay circuit, so that the delay time of the clock signals can be continuously adjusted by the first delay circuit and/or the second delay circuit until the phase difference between the new first output clock and the new second output clock is smaller than the phase threshold value, thereby improving the problem of signal delay among a plurality of circuit units.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit connection diagram of a clock calibration circuit according to an embodiment of the present disclosure;
FIG. 2a is a circuit connection diagram of a clock calibration circuit according to an embodiment of the present disclosure;
FIG. 2b is a diagram illustrating a circuit connection relationship of a clock calibration circuit according to an embodiment of the present disclosure;
FIG. 3 is a circuit connection diagram of a programmable logic chip according to an embodiment of the present disclosure;
fig. 4 is a circuit connection relationship diagram of a first delay unit and a third delay unit provided in an embodiment of the present application;
fig. 5 is a circuit connection relationship diagram of a second delay unit and a fourth delay unit provided in an embodiment of the present application;
fig. 6 is a circuit connection diagram of a clock calibration circuit according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. It should be noted that, without conflict, features in embodiments of the present application may be combined with each other.
As shown in fig. 1, the embodiment of the present application provides a clock calibration circuit 100, where the clock calibration circuit 100 includes a first delay circuit 10, a second delay circuit 20, and a phase detector 30.
As shown in fig. 2a and 2b, the first delay circuit 10 includes at least one first delay unit 11 and a first control circuit 12 corresponding to the at least one first delay unit 11, and the at least one first delay unit 11 inputs a first output clock to the phase detector 30 under the control of the first control circuit 12.
The second delay circuit 20, the second delay circuit 20 includes at least one second delay unit 21 and a second control circuit 22 corresponding to the at least one second delay unit 21, and the at least one second delay unit 21 inputs a second output clock to the phase detector 30 under the control of the second control circuit 22.
As shown in fig. 1, the phase detector 30 calculates the phase difference between the first output clock and the second output clock to obtain a comparison result, and when the comparison result is greater than or equal to the phase threshold value, the comparison result is fed back to the first delay circuit 10 and/or the second delay circuit 20, the first control circuit 12 controls at least one first delay unit 11 to adjust the first output clock according to the comparison result so as to input a new first output clock to the phase detector, and/or the second control circuit controls at least one second delay unit 21 to adjust the second output clock according to the comparison result so as to input a new second output clock to the phase detector 30 until the phase difference between the new first output clock and the new second output clock is less than the phase threshold value.
As shown in fig. 3, the clock calibration circuit may be applied to a programmable logic chip including a plurality of circuit units 200, each of the plurality of circuit units 200 including a clock circuit 201, and two clock circuits 201 of each of the two circuit units 200 may be calibrated using the clock calibration circuit 100. The clock circuit 201 includes a clock output terminal, and the first delay circuit 10 may be electrically connected to the clock output terminal of the first clock circuit 201 to receive a first input clock of the first clock circuit 10, and the second delay circuit 20 may be electrically connected to the clock output terminal of the second clock circuit 201 to receive a second input clock of the second clock circuit 201.
In some embodiments, in the case that the first delay circuit 10 includes a plurality of first delay units 11, as shown in fig. 2a, the first control circuit 12 may include a plurality of first control units, which are in one-to-one correspondence with and electrically connected to the first delay units 11, and are used to input control signals to the first delay units 11 corresponding thereto.
Alternatively, in the case that the first delay circuit 10 includes a plurality of first delay units 11, as shown in fig. 2b, the first control circuit 12 may include a plurality of output pins corresponding to and electrically connected to the first delay units 11, and the first control circuit 12 is configured to input a control signal to the corresponding first delay units 11 through the output pins. The control signals input to the different first delay units 11 by the first control circuit 12 through the different output pins may be the same or different.
In some embodiments, after the first delay circuit 10 receives the first input clock output by the first clock circuit 201, the at least one first delay unit 11 may input the first output clock to the phase detector 30 under the control of the first control circuit 12. Wherein the at least one first delay unit 11 may delay or not delay the received clock signal under the control of the first control circuit 12.
The number of the first delay units 11 is 3, the first delay unit 11 delays under the control of the first control circuit 12, the second first delay unit 11 does not delay under the control of the first control circuit 12, and the third first delay unit 11 does not delay under the control of the first control circuit 12.
In some embodiments, the maximum delay time of at least one first delay unit 11 is related to a specific constituent circuit of the first delay unit 11, which is not limited herein. Alternatively, the maximum delay time of each first delay unit 11 may be 25 picoseconds.
In the case where the number of the first delay units 11 is plural, the maximum delay time lengths of the plural first delay units 11 may be the same or different.
In some embodiments, in the case that the second delay circuit 20 includes a plurality of second delay units 21, as shown in fig. 2a, the second control circuit 22 may include a plurality of second control units, which are in one-to-one correspondence with and electrically connected to the second delay units 21, and are used for inputting control signals to the second delay units 21 corresponding thereto.
Alternatively, in the case where the second delay circuit 20 includes a plurality of second delay units 21, as shown in fig. 2b, the second control circuit 22 may include a plurality of output pins corresponding to and electrically connected to the second delay units 21, and the second control circuit 22 is configured to input a control signal to the second delay units 21 corresponding thereto through the output pins. The control signals input to the different second delay units 21 by the second control circuit 22 through the different output pins may be the same or different.
In some embodiments, after the second delay circuit 20 receives the second input clock output by the second clock circuit 201, the at least one second delay unit 21 may input the second output clock to the phase detector 30 under the control of the second control circuit 22. Wherein the at least one second delay unit 21 may delay or not delay the received clock signal under the control of the second control circuit 22.
For example, the number of the second delay units 21 is 3, the first second delay unit 21 delays under the control of the second control circuit 22, the second delay unit 21 delays under the control of the second control circuit 22, and the third second delay unit 21 does not delay under the control of the second control circuit 22.
In some embodiments, the maximum delay time of at least one second delay unit 21 is related to the specific constituent circuits of the second delay unit 21, and is not limited herein. Alternatively, the maximum delay time of each second delay unit 21 may be 25 picoseconds.
In the case where the number of the first delay units 11 is plural, the maximum delay time lengths of the plural first delay units 11 may be the same or different.
In some embodiments, the clock circuits 201 of each two circuit units 200 are respectively named as a first clock circuit 201 and a second clock circuit 201 for convenience of distinction, however, it should be understood by those skilled in the art that the clock circuit 201 of any one circuit unit 200 may be used as the first clock circuit 201 or the second clock circuit 201 of the clock circuits 201 of the first other circuit units 200.
In some embodiments, the number of the first delay units 11 may be the same as or different from the number of the second delay units. The maximum delay time length of the first delay unit 11 may be the same as or different from the maximum delay time length of the second delay unit 21.
In some embodiments, in the case where the number of the first delay units 11 is plural, the connection relationship of the plural first delay units 11 is not limited. Alternatively, a plurality of first delay units 11 may be connected in series.
In the case where the number of the second delay units 21 is plural, the connection relationship of the plural second delay units 21 is not limited. Alternatively, a plurality of second delay units 21 may be connected in series.
In some embodiments, the specific value of the phase threshold is not limited, alternatively, in the case where the maximum delay time lengths of the first delay unit 11 and the second delay unit 12 are both 25 picoseconds, the phase threshold may be 25 picoseconds, that is, when the comparison result is greater than or equal to 25 picoseconds, the first delay circuit 10 and/or the second delay circuit 20 are required to adjust the first output clock and/or the second output clock again on the basis of the first output clock and/or the second output clock, and input the first output clock and/or the second output clock to the phase discriminator 30 until the comparison result is less than 25 picoseconds.
For example, in the case that the comparison result is 26 picoseconds, the phase detector 30 may only feed back the comparison result to the first delay circuit 10 or the second delay circuit 20, and only one first delay unit 11 or one second delay unit 21 is required to make the updated comparison result less than 25 picoseconds.
In the case that the comparison result is 50 picoseconds, the phase detector 30 may feed back only the comparison result to the first delay circuit 10 and/or the second delay circuit 20, specifically, the number of the first delay units 11 and the second delay units 12, the connection relationship between the first delay units 11 and the first delay units 11, and the connection relationship between the second delay units 12 and the second delay units 12.
In other embodiments, the comparison result of the first output clock and the second output clock may be smaller than the phase threshold, in which case the phase detector 30 may not need to feed back the comparison result to the first delay circuit 10 and the second delay circuit 20.
In some embodiments, the clock calibration circuit 100 may further include a state machine 60, where an input terminal of the state machine 60 is electrically connected to an output terminal of the phase detector 30, and output terminals of the state machine 60 are respectively electrically connected to the first delay circuit 10 and the second delay circuit 20, and the state machine 60 may collect the comparison result at intervals, and feedback the comparison result to the first delay circuit 10 and/or the second delay circuit 20 when the comparison result is greater than or equal to the phase threshold value.
The embodiment of the present application provides a clock calibration circuit 100, a first delay circuit 10 and a second delay circuit of the clock calibration circuit 100 may be electrically connected to clock output ends of clock circuits 201 in two circuit units 200 respectively, and configured to receive clock signals of the clock circuits 201 electrically connected to the clock circuits, adjust the received clock signals, send a first output clock and a second output clock to a phase discriminator 30 respectively after the adjustment, and after the comparison result is obtained by the phase discriminator 30, if the comparison result is still greater than or equal to a phase threshold, feedback the comparison result to the first delay circuit 10 and/or the second delay circuit 20, so that the delay time of the clock signals is continuously adjusted by the first delay circuit 10 and/or the second delay circuit 20 until a phase difference between a new first output clock and a new second output clock is less than the phase threshold, thereby improving a problem of signal delay between a plurality of circuit units.
As shown in fig. 4, another embodiment of the present application provides a clock calibration circuit 100, and detailed circuit structures of the first delay unit 11 and the second delay unit 12 are described on the basis of the foregoing embodiments.
The at least one first delay circuit 10 includes a plurality of first delay units 11 connected in series, the first delay units 11 including a selector 111 and a first buffer 112.
The first input terminal of the selector 111 of the first delay unit is electrically connected to the first clock signal input terminal, the second input terminal is electrically connected to the first clock signal input terminal through the first buffer 112, and the control terminal is electrically connected to the first control circuit. The input terminal of the selector of each other first delay unit is electrically connected to the output terminal of the selector 111 of the previous first delay unit, and the control terminal is electrically connected to the first control circuit 12. The output of the last first delay cell is electrically connected to the input of the phase detector 30.
Taking the first delay unit as an example, the first input end of the first delay unit is electrically connected with the first clock signal input end, so that the first clock signal can be directly received; the second input terminal of the first delay unit is electrically connected to the first clock signal input terminal through the first buffer 112, and can receive the clock signal delayed by the first clock signal.
On the basis, the selector 111 of the first delay unit may selectively output the first clock signal received at the first input terminal or output the clock signal delayed from the first clock signal received at the second input terminal under the control of the first control circuit 12.
Similarly, the first input end of the other first delay units may directly receive the clock signal output by the previous first delay unit, and the second input end may receive the clock signal delayed by the first buffer 112 from the clock signal output by the previous first delay unit. The selector 111 of the other first delay units may selectively output the clock signal output by the previous first delay unit received at the first input terminal or the clock signal delayed by the first buffer 112 from the clock signal output by the previous first delay unit received at the second input terminal under the control of the first control circuit 12.
In some embodiments, the comparison result may include a first output clock and a first adjustment signal. The output terminal of the phase detector 30 is electrically connected to the first input terminal and the second input terminal of the selector 111 of the first delay unit, and the first control circuit 12, respectively, and the phase detector 30 is configured to input the first output clock to the selector 111 of the first delay unit and the first adjustment signal to the first control circuit 12 when the comparison result is greater than or equal to the phase threshold.
Thus, if the comparison result is greater than or equal to the phase threshold, and the phase detector 30 feeds back the comparison result to the first delay circuit 10, the first delay unit may receive the first output clock, and the plurality of first delay units 11 connected in series may delay the first output clock again under the control of the first control circuit 12.
As shown in fig. 5, the at least one second delay circuit 20 includes a plurality of second delay units 21 connected in series, the second delay units including a selector 211 and a second buffer 212.
The first input terminal of the selector 211 of the first second delay unit is electrically connected to the second clock signal input terminal, the second input terminal is electrically connected to the second clock signal input terminal through the first buffer 212, and the control terminal is electrically connected to the second control circuit 22. The input terminal of the selector 211 of each other second delay unit is electrically connected to the output terminal of the selector 211 of the last second delay unit, and the control terminal is electrically connected to the second control circuit 22. The output of the last second delay cell is electrically connected to the input of the phase detector 30.
Taking the first and second delay units as examples, the first input end of the first and second delay units is electrically connected with the second clock signal input end, so that the second clock signal can be directly received; the second input terminal of the first second delay unit is electrically connected to the second clock signal input terminal through the second buffer 212, and can receive the delayed clock signal of the second clock signal.
On the basis, the selector 211 of the first second delay unit may selectively output the second clock signal received at the first input terminal or output the delayed clock signal of the second clock signal received at the second input terminal under the control of the second control circuit 22.
Similarly, the first input end of the other second delay units may directly receive the clock signal output by the previous second delay unit, and the second input end may receive the clock signal delayed by the buffer 212 from the clock signal output by the previous second delay unit. The selector 111 of the other second delay units may selectively output the clock signal output by the previous second delay unit received at the first input terminal or the clock signal delayed by the second buffer 212 from the clock signal output by the previous second delay unit received at the second input terminal under the control of the second control circuit 22.
In some embodiments, the comparison result may include a second output clock and a second adjustment signal. The output terminal of the phase detector 30 is electrically connected to the first input terminal and the second input terminal of the selector 211 of the first second delay unit, and the second control circuit 22, respectively, and the phase detector 30 is configured to input the second output clock to the selector 211 of the first second delay unit and the first adjustment signal to the first control circuit 12 when the comparison result is greater than or equal to the phase threshold.
Thus, if the comparison result is greater than or equal to the phase threshold, and the phase detector 30 feeds back the comparison result to the second delay circuit 20, the first second delay unit may receive the first output clock, and the plurality of second delay units 21 connected in series may delay the second output clock again under the control of the second control circuit 22.
As shown in fig. 6, the embodiment of the present application further provides a clock calibration circuit 100, where, on the basis of any of the foregoing embodiments, the clock calibration circuit 100 further includes a third delay circuit 40 and a fourth delay circuit 50.
The third delay circuit 40 includes at least one third delay unit 41 and a third control circuit 42 corresponding to the at least one third delay unit 41; the input end of the third delay circuit 40 is electrically connected to the first clock signal input end, the output end is electrically connected to the first input end and the second input end of the first delay circuit 10, and the third delay circuit 40 is configured to receive the first input clock input by the first clock signal input end and calibrate the first input clock according to the transmission path of the first input clock.
The fourth delay circuit 50 includes at least one fourth delay unit 51 and a fourth control circuit 52 corresponding to the at least one fourth delay unit 51. The input end of the fourth delay circuit 50 is electrically connected to the second clock signal input end, the output end is electrically connected to the first input end and the second input end of the first second delay circuit 20, and the fourth delay circuit 50 is configured to receive the second input clock input by the second clock signal input end and calibrate the second input clock according to the transmission path of the second clock signal.
In the case where the paths traversed by the clocks of the two circuit units 200 are determined and the two path lengths are different, one of the two clock signals may be delayed more due to the different path lengths. In this case, the length of time that can be delayed by the third delay circuit 40 and/or the fourth delay circuit 50 may be determined according to the path lengths of the respective two clock signals, and then the delay with the first input clock and/or the second input clock is performed by the third delay circuit 40 and/or the fourth delay circuit 50.
In some embodiments, in the case that the third delay circuit 40 includes a plurality of third delay units 41, referring to fig. 2a, the third control circuit 42 may include a plurality of third control units, which are in one-to-one correspondence with and electrically connected to the third delay units 41, and are used to input control signals to the third delay units 41 corresponding thereto.
Alternatively, as shown in fig. 4, the third control circuit 42 may include a plurality of output pins, where the plurality of output pins are corresponding to and electrically connected to the third delay units 41, and the third control circuit 42 is configured to input a control signal to the corresponding third delay units 41 through the output pins. The control signals input to the different third delay units 41 by the third control circuit 42 through the different output pins may be the same or different.
In some embodiments, after the third delay circuit 40 receives the first input clock, the at least one third delay unit 41 may delay or not delay the received clock signal under the control of the third control circuit 42.
For example, the number of the third delay units 41 is 2, the first third delay unit 41 delays under the control of the third control circuit 42, and the second third delay unit 41 does not delay under the control of the third control circuit 42.
In some embodiments, the maximum delay time of at least one third delay element 41 is related to the specific constituent circuits of the third delay element 41, and is not limited herein. Alternatively, the maximum delay time of each third delay unit 41 may be 100 picoseconds.
In the case where the number of the third delay units 41 is plural, the maximum delay time lengths of the plural third delay units 41 may be the same or different.
In some embodiments, in the case that the fourth delay circuit 50 includes a plurality of fourth delay units 51, referring to fig. 2a, the fourth control circuit 52 may include a plurality of fourth control units, which are in one-to-one correspondence with the fourth delay units 51 and are electrically connected, and the fourth control units are used to input control signals to the fourth delay units 51 corresponding thereto.
Alternatively, in the case where the fourth delay circuit 50 includes a plurality of fourth delay units 51, as shown in fig. 5, the fourth control circuit 52 may include a plurality of output pins corresponding to and electrically connected to the fourth delay units 51, and the fourth control circuit 52 may be configured to input a control signal to the fourth delay unit 51 corresponding thereto through the output pins. The control signals input to the different fourth delay units 51 by the fourth control circuit 52 through the different output pins may be the same or different.
In some embodiments, after the fourth delay circuit 50 receives the second input clock, the at least one fourth delay unit 51 may delay or not delay the received clock signal under the control of the fourth control circuit 52.
For example, the number of the fourth delay units 51 is 2, the first fourth delay unit 51 delays under the control of the fourth control circuit 52, and the second fourth delay unit 51 delays under the control of the fourth control circuit 52.
In some embodiments, the maximum delay time of the at least one fourth delay unit 51 is related to a specific constituent circuit of the fourth delay unit 51, which is not limited herein. Alternatively, the maximum delay time length of each fourth delay unit 51 may be 100 picoseconds.
In the case where the number of the fourth delay units 51 is plural, the maximum delay time lengths of the plural fourth delay units 51 may be the same or different.
In some embodiments, the number of third delay units 41 may be the same as or different from the number of second delay units. The maximum delay time length of the third delay unit 41 may be the same as or different from the maximum delay time length of the fourth delay unit 51.
In some embodiments, in the case where the number of the third delay units 41 is plural, the connection relationship of the plural third delay units 41 is not limited. Alternatively, a plurality of third delay units 41 may be connected in series.
When the number of fourth delay units 51 is plural, the connection relationship between the plural fourth delay units 51 is not limited. Alternatively, a plurality of fourth delay units 51 may be connected in series.
In some embodiments, as shown in fig. 4, at least one third delay circuit 40 includes a plurality of third delay cells 41 in series, the third delay cells 41 including a selector 411 and a third buffer 412. The first input terminal of the selector 411 of the first third delay unit is electrically connected to the first clock signal input terminal, the second input terminal is electrically connected to the first clock signal input terminal through the third buffer 412, and the control terminal is electrically connected to the third control circuit 42. The input terminal of the selector 411 of each of the other third delay units is electrically connected to the output terminal of the selector 411 of the last third delay unit, and the control terminal is electrically connected to the third control circuit 42. The output of the last third delay cell is electrically connected to the first delay cell of the first delay circuit 10.
As shown in fig. 5, the at least one fourth delay circuit 50 includes a plurality of fourth delay units 51 connected in series, and the fourth delay units 51 include a selector 511 and a fourth buffer 512. The first input terminal of the selector 511 of the first fourth delay unit is electrically connected to the second clock signal input terminal, the second input terminal is electrically connected to the second clock signal input terminal through the fourth buffer 512, and the control terminal is electrically connected to the fourth control circuit 52. The input terminal of the selector 511 of each other fourth delay unit is electrically connected to the output terminal of the selector 511 of the last fourth delay unit, and the control terminal is electrically connected to the fourth control circuit 52. The output of the last fourth delay cell is electrically connected to the first second delay cell of the second delay circuit 20.
Taking the first third delay unit as an example, the first input end of the first third delay unit is electrically connected with the first clock signal input end, so that the first clock signal can be directly received; the second input terminal of the first third delay unit is electrically connected to the first clock signal input terminal through the third buffer 412, and can receive the clock signal delayed by the first clock signal.
On the basis of this, the selector 411 of the first third delay unit may selectively output the first clock signal received at the first input terminal or output the clock signal delayed from the first clock signal received at the second input terminal under the control of the third control circuit 42.
Similarly, the first input terminal of the other third delay units may directly receive the clock signal output by the previous third delay unit, and the second input terminal may receive the clock signal delayed by the third buffer 412 from the clock signal output by the previous third delay unit. The selector 411 of the other third delay units may select to output the clock signal output by the previous third delay unit received at the first input terminal or the clock signal delayed by the third buffer 412 from the clock signal output by the previous third delay unit received at the second input terminal under the control of the third control circuit 42.
In this embodiment, the maximum delay time of each third delay unit 41 in the third delay circuit 40 may be greater than the maximum delay time of each first delay unit 11 in the first delay circuit 10, so as to adjust clock delay caused by different clock path lengths, and further, since the maximum delay time of the first delay unit 11 is less than the maximum delay time of the third delay unit 41, the clock signal may be further finely adjusted by using the first delay unit 11. The maximum delay time of each fourth delay unit 51 in the fourth delay circuit 50 may be longer than the maximum delay time of each second person delay unit 21 in the second delay circuit 20, so as to adjust the clock delay caused by different clock path lengths, and further, since the maximum delay time of the second delay unit 21 is smaller than the maximum delay time of the fourth delay unit 51, the clock signal may be further finely adjusted by using the second delay unit 21.
As shown in fig. 3, the embodiment of the present application further provides a programmable logic chip, which includes a plurality of circuit units 200 and a plurality of clock calibration circuits 100 according to any of the foregoing embodiments, where the circuit units 200 include clock output terminals. Each two circuit units 200 corresponds to one clock calibration circuit 100, and the input end of the first delay circuit 10 of the clock calibration circuit 100 is electrically connected to the clock output end of the corresponding one circuit unit 200, and the input end of the second delay circuit 20 is electrically connected to the clock output end of the corresponding other circuit unit 200.
The programmable logic chip may be a Field programmable gate array (Field-Programmable Gate Array, abbreviated as FPGA) chip or a complex programmable logic device (Complex Programmable Logic Device, abbreviated as CPLD) or the like.
The explanation and the beneficial effects of the programmable logic chip provided in the embodiment of the present application are the same as those of the previous embodiment, and are not repeated here.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, one of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not drive the essence of the corresponding technical solutions to depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (8)
1. A clock calibration circuit, comprising:
the first delay circuit comprises at least one first delay unit and a first control circuit corresponding to the at least one first delay unit, and the at least one first delay unit inputs a first output clock to the phase detector under the control of the first control circuit;
the first delay circuit comprises a plurality of first delay units connected in series, the first delay units comprise selectors and first buffers, the first input end of each selector of each first delay unit is electrically connected with a first clock signal input end, the second input end of each selector of each first delay unit is electrically connected with the first clock signal input end through each first buffer, the control end of each selector of each other first delay unit is electrically connected with the output end of each selector of the last first delay unit, the control end of each selector of each first delay unit is electrically connected with the first control circuit, and the output end of each last first delay unit is electrically connected with the input end of the phase discriminator;
the second delay circuit comprises at least one second delay unit and a second control circuit corresponding to the at least one second delay unit, and the at least one second delay unit inputs a second output clock to the phase discriminator under the control of the second control circuit;
the phase discriminator is used for calculating the phase difference between the first output clock and the second output clock to obtain a comparison result, when the comparison result is larger than or equal to a phase threshold value, the comparison result is fed back to the first delay circuit and/or the second delay circuit, the first control circuit controls the at least one first delay unit to adjust the first output clock according to the comparison result so as to input a new first output clock into the phase discriminator, and/or the second control circuit controls the at least one second delay unit to adjust the second output clock according to the comparison result so as to input a new second output clock into the phase discriminator until the phase difference between the new first output clock and the new second output clock is smaller than the phase threshold value, and the comparison result comprises the first output clock and a first adjusting signal;
the phase detector is used for inputting the first output clock to the selector of the first delay unit and inputting the first adjusting signal to the first control circuit when the comparison result is larger than or equal to the phase threshold value.
2. The clock calibration circuit of claim 1, further comprising a third delay circuit comprising at least one third delay cell and a third control circuit corresponding to the at least one third delay cell;
the input end of the third delay circuit is electrically connected with the first clock signal input end, the output end of the third delay circuit is electrically connected with the first input end and the second input end of the first delay circuit, and the third delay circuit is used for receiving the first input clock input by the first clock signal input end and calibrating the first input clock according to the transmission path of the first input clock.
3. The clock calibration circuit of claim 2, wherein the at least one third delay circuit comprises a plurality of third delay cells in series, the third delay cells comprising a selector and a third buffer;
a first input end of a selector of the first third delay unit is electrically connected with the first clock signal input end, a second input end of the selector of the first third delay unit is electrically connected with the first clock signal input end through the third buffer, and a control end of the selector of the first third delay unit is electrically connected with the third control circuit;
the input end of the selector of each other third delay units is electrically connected with the output end of the selector of the last third delay unit, and the control end is electrically connected with the third control circuit;
the output end of the last third delay unit is electrically connected with the input end of the first delay unit of the first delay circuit.
4. A clock calibration circuit according to any one of claims 1 to 3, wherein the at least one second delay circuit comprises a plurality of second delay cells in series, the second delay cells comprising a selector and a second buffer;
the first input end of the selector of the first second delay unit is electrically connected with the second clock signal input end, the second input end is electrically connected with the second clock signal input end through the second buffer, and the control end is electrically connected with the second control circuit;
the input end of the selector of each other second delay units is electrically connected with the output end of the selector of the last second delay unit, and the control end is electrically connected with the second control circuit;
the output end of the last second delay unit is electrically connected with the input end of the phase discriminator.
5. The clock calibration circuit of claim 4, wherein the comparison result comprises the second output clock and a second adjustment signal;
the output end of the phase discriminator is electrically connected with the first input end and the second input end of the selector of the first second delay unit and the second control circuit respectively, and the phase discriminator is used for inputting the second output clock to the selector of the first second delay unit and inputting the second adjusting signal to the second control circuit when the comparison result is larger than or equal to the phase threshold value.
6. The clock calibration circuit of claim 5, further comprising a fourth delay circuit comprising at least one fourth delay cell and a fourth control circuit corresponding to the at least one fourth delay cell;
the input end of the fourth delay circuit is electrically connected with the second clock signal input end, the output end of the fourth delay circuit is electrically connected with the first input end and the second input end of the first second delay circuit, and the fourth delay circuit is used for receiving the second input clock input by the second clock signal input end and calibrating the second input clock according to the transmission path of the second clock signal.
7. The clock calibration circuit of claim 6, wherein the at least one fourth delay circuit comprises a plurality of fourth delay cells in series, the fourth delay cells comprising a selector and a fourth buffer;
a first input end of a selector of the first fourth delay unit is electrically connected with the second clock signal input end, a second input end of the selector of the first fourth delay unit is electrically connected with the second clock signal input end through the fourth buffer, and a control end of the selector of the first fourth delay unit is electrically connected with the fourth control circuit;
the input end of the selector of each other fourth delay unit is electrically connected with the output end of the selector of the last fourth delay unit, and the control end is electrically connected with the fourth control circuit;
the output end of the last fourth delay unit is electrically connected with the input end of the first second delay unit of the second delay circuit.
8. A programmable logic chip comprising a plurality of circuit units and a plurality of clock calibration circuits according to any one of claims 1-7, the circuit units comprising clock outputs;
each two circuit units correspond to one clock calibration circuit, the input end of the first delay circuit of the clock calibration circuit is electrically connected with the clock output end of the corresponding circuit unit, and the input end of the second delay circuit is electrically connected with the clock output end of the corresponding other circuit unit.
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