CN108039885A - A kind of high speed dividing method and there is the high-speed frequency divider of duty cycle adjustment - Google Patents
A kind of high speed dividing method and there is the high-speed frequency divider of duty cycle adjustment Download PDFInfo
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- CN108039885A CN108039885A CN201810140080.9A CN201810140080A CN108039885A CN 108039885 A CN108039885 A CN 108039885A CN 201810140080 A CN201810140080 A CN 201810140080A CN 108039885 A CN108039885 A CN 108039885A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
Abstract
The invention discloses a kind of high speed dividing method and there is the high-speed frequency divider of duty cycle adjustment.Frequency divider includes subtraction circuit, negative circuit, add circuit and adjusts circuit.Subtraction circuit receives N frequency dividing ratio signals and input clock signal and provides subtraction signal；Negative circuit receives the subtraction signal and provides anti-reflection signal；Add circuit receives height (N 1) position of the anti-reflection signal and frequency dividing ratio signal, it provides carry signal.In the case of even frequency division, the high-speed frequency divider can obtain duty cycle be 50% carry signal as fractional frequency signal, avoid frequency jitter；In the case of frequency division by odd integers, adjust circuit and carry signal is compensated or adjusted, can equally obtain the fractional frequency signal that duty cycle is 50%.
Description
Technical field
It is more specific to be still not exclusively to high speed dividing method and have account for the present invention relates to a kind of dividing method
The empty frequency divider than regulatory function.
Background technology
In contemporary electronic systems, the ratio shared by digital electronic system is increasing.In digital logic circuit design,
Frequency divider is a kind of basic circuit, commonly used to be divided to some given frequency, obtains required frequency.Application at present is most
It is widely the frequency synthesis technique based on phaselocked loop, it can synthesize very high frequency, while phase noise is also smaller, because
This is using extremely wide.At a high speed, the frequency divider design of 50% duty cycle is always the difficult point in Design of PLL.It is public at present
The divider circuit known is complicated, and can bring the shake between cycle and cycle.How to improve, so that frequency divider is electric
Road is simple, and possesses that the ability of 50% duty cycle input clock signal is all exported when odd and even number divides is art technology
Personnel's technical issues that need to address.
The content of the invention
To solve the above problems, the present invention provides a kind of high speed dividing method, including provide N frequency dividing ratio signal with
Input clock signal, wherein N are the integer more than 1；In the rising edge or trailing edge of each input clock signal, the frequency dividing
The acquisition subtraction signal that subtracts 1 successively than signal；The subtraction signal is anti-phase, obtain anti-reflection signal；Take the height of N frequency dividing ratio signals
(N-1) position, obtains dividing high half signal；The anti-reflection signal is added with high half signal of frequency dividing, obtains carry signal；With
And carry signal is provided as fractional frequency signal.
There is the high-speed frequency divider of duty cycle adjustment present invention also offers a kind of, including：Subtraction circuit, has the
One input terminal, the second input terminal and output terminal, the first input end and the second input terminal receive frequency dividing ratio signal and defeated respectively
Enter clock signal, the subtraction circuit is based on the input clock signal and carries out subtraction to frequency dividing ratio signal, and defeated at its
Outlet provides subtraction signal, and the frequency dividing ratio signal is N position digital signals, and wherein N is the integer more than 1；Negative circuit, has
Input terminal and output terminal, its input terminal are coupled to the output terminal of the subtraction circuit to receive the subtraction signal, its output terminal
Anti-reflection signal is provided；And add circuit, there is first input end, the second input terminal and output terminal, the coupling of its first input end
The extremely output terminal of the negative circuit is to receive the anti-reflection signal, its second input terminal, which receives, divides high half signal, described point
Frequently high half signal is height (N-1) position of frequency dividing ratio signal, its output terminal provides carry signal, and the add circuit is to the anti-reflection
Signal and high half signal of frequency dividing carry out add operation；And circuit is adjusted, there is control terminal, first input end, second defeated
Enter end and output terminal, its control terminal receives the input clock signal, its first input end receives the frequency dividing ratio signal most
Low level, its second input terminal are coupled to the output terminal of the add circuit to receive the carry signal, its output terminal, which provides, to be divided
Frequency signal；The adjusting circuit includes：First d type flip flop, has first input end, the second input terminal and output terminal, first is defeated
Entering to hold the output terminal for being coupled to add circuit, the second input terminal receives input clock signal to receive carry signal；First is anti-phase
Device, has input terminal and output terminal, its input terminal receives input clock signal；Second d type flip flop, has first input end, the
Two input terminals and output terminal, first input end are coupled to the output terminal of add circuit to receive carry signal or the first d type flip flop
Output terminal, the second input terminal are coupled to the output terminal of the first phase inverter；First OR gate, has first input end, the second input terminal
And output terminal, first input end are coupled to the output terminal of the first d type flip flop, the second input terminal is coupled to the defeated of the second d type flip flop
Outlet；First NAND gate, has first input end, the second input terminal and output terminal, and first input end is coupled to the first OR gate
Output terminal, the second input terminal receive frequency dividing ratio signal lowest order；Second phase inverter, has input terminal and output terminal, input termination
Contracture frequency ratio signal lowest order；Second NAND gate, has first input end, the second input terminal and output terminal, first input end coupling
The output terminal of the second phase inverter is connected to, the second input terminal is coupled to the output terminal of add circuit；And the 3rd NAND gate, have the
One input terminal, the second input terminal and output terminal, first input end are coupled to the output terminal of the first NAND gate, the coupling of the second input terminal
To the output terminal of the second NAND gate, its output terminal provides the fractional frequency signal.
The high speed dividing method and frequency divider rapidly and accurately can carry out input clock signal according to frequency dividing ratio signal
Frequency dividing, as a result of digital control, be directly based upon clock signal and divided, avoid frequency jitter.In even frequency division feelings
Under condition, which can obtain the fractional frequency signal that duty cycle is 50%, avoid frequency jitter.In frequency division by odd integers situation
Under, carry signal is compensated or adjusted, can equally obtain the fractional frequency signal that duty cycle is 50%.
Brief description of the drawings
Fig. 1 shows the circuit diagram of high-speed frequency divider 10 according to an embodiment of the invention；
Fig. 2 shows to adjust the operation oscillogram 20 of circuit；
Fig. 3 shows to adjust the operation oscillogram 30 of circuit；
Fig. 4 shows adjusting circuit 40 according to an embodiment of the invention；
Fig. 5 shows adjusting circuit 50 according to an embodiment of the invention；
Fig. 6 shows adjusting circuit 60 according to an embodiment of the invention；
Fig. 7 shows adjusting circuit 70 according to an embodiment of the invention；
Fig. 8 shows the flow chart of high speed dividing method 80 according to an embodiment of the invention.
Embodiment
The specific embodiment being described below represents the exemplary embodiment of the present invention, and substantially merely illustrative explanation
It is and unrestricted.In the description, refer to that " one embodiment " or " embodiment " means to combine the described spy of the embodiment
Determining feature, structure or characteristic is included at least one embodiment of the present invention.Term " in one embodiment " is illustrating
Each position occurs not all referring to identical embodiment in book, nor mutually exclusive other embodiment or variable implementation
Example.All features disclosed in this specification, or disclosed all methods or during the step of, except mutually exclusive feature
And/or beyond step, it can combine in any way.
The embodiment that the present invention will be described in detail below with reference to the accompanying drawings.The reference numeral identical through all attached drawings
Represent identical component or feature.
Fig. 1 shows the circuit diagram of high-speed frequency divider 10 according to an embodiment of the invention, and frequency divider 10 includes subtracting
Method circuit 101, negative circuit 102, add circuit 103 and adjusting circuit 104.Subtraction circuit 101, has first input end, the
Two input terminals and output terminal, its first input end and the second input terminal receive frequency dividing ratio signal DIV respectively<N:0>And input clock
Signal CKIN, frequency dividing ratio signal DIV<N:0>For N position digital signals, wherein N is the integer more than 1.Subtraction circuit 101 is based on defeated
Enter clock signal CKIN to frequency dividing ratio signal DIV<N:0>Count with subtraction and provide subtraction signal in its output terminal
DIV_O<N:0>.In one embodiment, in the rising edge of each input clock signal CKIN, subtraction circuit 101 is by frequency dividing ratio
Signal DIV<N:0>Subtract 1, such as in first rising edge of input clock signal CKIN by frequency dividing ratio signal DIV<N:0>Subtracted by 111
For 110, in the next rising edges of input clock signal CKIN by frequency dividing ratio signal DIV<N:0>101 are kept to by 110 ... ..., will
Frequency dividing ratio signal DIV<N:0>111 are kept to by 000, specifically may be referred to form 1.In other examples, subtraction circuit 101
Can also input clock signal CKIN each trailing edge by frequency dividing ratio signal DIV<N:0>Subtract 1 successively.
Negative circuit 102, has input terminal and an output terminal, its input terminal is coupled to the output terminal of subtraction circuit 101 to connect
Receive subtraction signal DIV_O<N:0>, subtraction signal DIV_O of the negative circuit 102 to input<N:0>Carry out anti-phase, its output terminal carries
For anti-reflection signal DIV_N<N:0>.In one embodiment, if subtraction signal DIV_O<N:0>For 101, then anti-reflection signal DIV_N
<N:0>For 010, with specific reference to form 1.Negative circuit 102 can be realized with multiple phase inverters.
Add circuit 103, there is control terminal, first input end, the second input terminal and output terminal, first input end to be coupled to
The output terminal of negative circuit 102 with receive negative circuit 102 output anti-reflection signal DIV_N<N:0>, the second input terminal, which receives, to be divided
Frequently high half signal DIV<N:1>, divide high half signal DIV<N:1>For frequency dividing ratio signal DIV<N:0>Height (N-1) position.At one
In embodiment, if frequency dividing ratio signal DIV<N:0>For 111 (corresponding ten's digits 7), then high (N-1) position for 11 (corresponding ten into
System numeral is 3)；If frequency dividing ratio signal DIV<N:0>For 110 (corresponding ten's digits 6), then high (N-1) position for 11 (corresponding ten into
System is digital 3), referring specifically to table 1.In digital signal, (N-1) position is approximately divided by 2 before taking, therefore DIV<N:1>Referred to as frequency dividing is high by half
Signal.Those of ordinary skill in the art can also be understood with following manner divides high half signal DIV<N:1>：Frequency dividing ratio is believed
Number DIV<N:0>Extreme lower position 0, then divided by 2.If such as frequency dividing ratio signal DIV<N:0>It is 110 for 111, after lowest order zero setting
(corresponding ten's digit 6), divided by 011 (011 i.e. 11, corresponding ten's digit 3) is obtained after 2, referring specifically to table 1.
The anti-reflection signal DIV_N that add circuit 103 exports negative circuit 102<N:0>With the high half signal DIV of frequency dividing<N:1
>Additional calculation is carried out, and carry signal CO is provided in output terminal.In one embodiment, if the high half signal DIV of frequency dividing<
N:1>With the anti-reflection signal DIV_N<N:0>The sum of need carry, then carry signal CO is 1, such as 110+010=1000, then into
Position signal CO is 1.If the high half signal DIV of frequency dividing<N:1>With the anti-reflection signal DIV_N<N:0>The sum of without carry, then
The carry signal is 0, such as 100+010=110, then carry signal CO is 0.In another embodiment it is also possible to will
Whether carry is corresponding is represented to need carry with 0, and 1 represents without carry.In one embodiment, add circuit also has control
End, to receive input clock signal CKIN, the input clock signal CKIN based on control terminal is to anti-reflection signal DIV_N<N:0>
With the high half signal DIV of frequency dividing<N:1>Carry out additional calculation.In one embodiment, in input clock signal CKIN rising edges or
Trailing edge is by anti-reflection signal DIV_N<N:0>With the high half signal DIV of frequency dividing<N:1>Carry out add operation/calculating.
Circuit 104 is adjusted, there is control terminal, first input end, the second input terminal and output terminal, its control terminal receives input
Clock signal CKIN, its first input end receive frequency dividing low level signal DIV<0>(i.e. frequency dividing ratio signal DIV<N:0>Lowest order),
Its second input terminal is coupled to the output terminal of add circuit 103 to receive carry signal CO, its output terminal provides duty cycle essence
Upper is 50% output signal CKOUT.In one embodiment, if the lowest order of the frequency dividing ratio signal is first state (example
Such as 0, even frequency division), the direct output carry signal CO of circuit 104 is adjusted as fractional frequency signal CKOUT, i.e. fractional frequency signal CKOUT
Substantially equal to described carry signal CO；If the frequency dividing ratio signal DIV<N:0>Lowest order for the second state (such as 1, very
Number frequency dividing), the adjusting circuit 104 is adjusted such that the fractional frequency signal to the pulse width of the carry signal CO
Duty cycle is substantially equal to 50%.In other words, if without circuit 104 is adjusted, it is fractional frequency signal directly to provide carry signal CO, also may be used
Realize digital control high speed frequency dividing, obtain stable required frequency；Add and adjust circuit 104, can also realize duty cycle adjustment,
No matter frequency division by odd integers or even frequency division, can obtain duty cycle be 50% fractional frequency signal.
Table 1
As shown in table 1 and Fig. 2, it is assumed that frequency dividing ratio signal DIV<N:0>For 100, then high half signal DIV is divided<N:1>For
010 (0 is mended before 10), frequency dividing low level signal DIV<0>For 0.When input clock signal CKIN pulses (such as rising edge) arrive
(period 1 T1), subtraction circuit 101 is to frequency dividing ratio signal DIV<N:0>Carry out a subtraction, the subtraction letter of its output terminal
Number DIV_O<N:0>For 011, by negative circuit 102, anti-reflection signal DIV_N<N:0>For 100, this anti-reflection signal DIV_N<
N:0>(100) input terminal of add circuit 103, and the high half signal DIV of frequency dividing are transferred into<N:1>Signal (010) is defeated
Enter the lower progress of clock signal CKIN controls and add computing, i.e. 100+010=110, since without carry, carry signal CO is 0 entirely.
The next cycles (second round T2) of input clock signal CKIN, subtraction circuit 101 is to frequency dividing ratio signal DIV<N:0>One is carried out again
The subtraction signal DIV_O of secondary subtraction, i.e. its output terminal<N:0>It is changed into 010 from 011, by negative circuit 102, anti-reflection letter
Number DIV_N<N:0>For 101, this anti-reflection signal DIV_N<N:0>(101) input terminal of add circuit 103 is transferred into,
With the high half signal DIV of frequency dividing<N:1>Signal (010) carries out adding computing, i.e. 101+010 entirely under input clock signal CKIN controls
=111, due to continuing to remain 0 in second round T2 without carry, i.e. carry signal CO.It is next in input clock signal CKIN
In the cycle (period 3 T3), subtraction circuit 101 is to frequency dividing ratio signal DIV<N:0>A subtraction, i.e. its output terminal are carried out again
Subtraction signal DIV_O<N:0>It is changed into 001 from 010, by negative circuit 102, anti-reflection signal DIV_N<N:0>For 110, this
Anti-reflection signal DIV_N<N:0>(110) input terminal of add circuit 103, and the high half signal DIV of frequency dividing are transferred into<N:1>
Signal (010) is carried out under input clock signal CKIN controls entirely plus computing, i.e. 110+010=1000, carry signal CO are 1,
Other work-based logics and sequential refer to table 1 and Fig. 2.As shown in Fig. 2, in period 1 T1 and second round T2, carry signal CO
For 0, period 3 T3 and period 4 T4, carry signal CO are 1, i.e., carry signal form a cycle (CT1, CT2 or
CT3) be four times of input clock signal cycle (T1, T2 ... T11 or T12) and duty cycle is 50% clock signal, that is, is realized
Four frequency dividing (frequency dividing ratio signal DIV<N:0>For 100,4) corresponding ten's digit is.Frequency dividing ratio signal DIV<N:0>Most
Low level is 0 (representing even frequency division), adjusts the direct output carry signal CO of circuit 104 as fractional frequency signal CKOUT, i.e. frequency dividing letter
Number CKOUT is substantially equal to the carry signal CO.Before period 1 T1, due to not to carry signal CO and fractional frequency signal
CKOUT carries out state analysis, therefore its state is represented by dashed line in Fig. 2.
As shown in Table 2 and Figure 3, it is assumed that frequency dividing ratio signal DIV<N:0>For 101, then high half signal DIV is divided<N:1>For
010, frequency dividing low level signal DIV<0>For 1.(the period 1 when input clock signal CKIN pulses (such as rising edge) arrive
T1), subtraction circuit 101 is to frequency dividing ratio signal DIV<N:0>Carry out a subtraction, the subtraction signal DIV_O of its output terminal<
N:0>For 100, by negative circuit 102, anti-reflection signal DIV_N<N:0>For 011, this anti-reflection signal DIV_N<N:0>(011)
It is transferred into an input terminal of add circuit 103, and the high half signal DIV of frequency dividing<N:1>Signal (010) is in input clock signal
CKIN controls are lower to be carried out adding computing entirely, i.e. 011+010=101, since without carry, carry signal CO is 0.Believe in input clock
Number next cycles (second round T2) of CKIN, subtraction circuit 201 is to frequency dividing ratio signal DIV<N:0>A subtraction is carried out again,
That is the subtraction signal DIV_O of its output terminal<N:0>For 011, by negative circuit 102, anti-reflection signal DIV_N<N:0>For 100,
This anti-reflection signal DIV_N<N:0>(100) input terminal of add circuit 103, and the high half signal DIV of frequency dividing are transferred into<
N:1>Signal (010) carries out entirely plus computing under input clock signal CKIN controls, i.e. 100+010=110, due to need not be into
Position, i.e., carry signal CO continues to remain 0 in second round T2.In input clock signal CKIN next (period 3 in cycle
T3), subtraction circuit 101 is to frequency dividing ratio signal DIV<N:0>A subtraction, the i.e. subtraction signal of its output terminal are carried out again
DIV_O<N:0>For 010, by negative circuit 102, anti-reflection signal DIV_N<N:0>For 101, this anti-reflection signal DIV_N<N:0
>(101) input terminal of add circuit 103, and the high half signal DIV of frequency dividing are transferred into<N:1>Signal (010) is in input
Clock signal CKIN controls are lower to be carried out adding computing entirely, i.e. 101+010=111, i.e. carry signal CO continue to keep in period 3 T3
For 0.In the next cycles (period 4 T4) of input clock signal CKIN, subtraction circuit 101 is to frequency dividing ratio signal DIV<N:0>Again
Carry out the subtraction signal DIV_O of a subtraction, i.e. its output terminal<N:0>For 001, by negative circuit 102, anti-reflection signal
DIV_N<N:0>For 110, this anti-reflection signal DIV_N<N:0>(110) input terminal of add circuit 103 is transferred into, and
Divide high half signal DIV<N:1>Signal (010) carries out adding computing, i.e. 110+010=entirely under input clock signal CKIN controls
1000, carry signal CO are 1, other work-based logics and sequential refer to table 2 and Fig. 3.
As shown in Fig. 2, in period 1 T1, second round T2 and period 3 T3, carry signal CO is 0, the period 4
T4 and period 5 T5, carry signal CO are 1, i.e., it is input clock that carry signal, which forms a cycle (CT1, CT2 or CT3),
Five times of signal period (T1, T2 ... T14 or T15) and the clock signal that duty cycle is 40%, that is, realize five frequency dividing (frequency dividing ratios
Signal DIV<N:0>For 101,5) corresponding ten's digit is.
Table 2
Frequency dividing ratio signal DIV<N:0>Lowest order be 1 (representing frequency division by odd integers), adjust circuit 104 to the carry signal
The pulse width of CO is adjusted such that the duty cycle of the fractional frequency signal is substantially equal to 50%.A reality according to the present invention
Example is applied, as shown in figure 3, sampling the carry signal adjusted signal CO ' of CO in input clock signal CKIN trailing edges, carry is believed
Number CO and Regulate signal CO ' takes OR (or logic) to obtain the output frequency division clock i.e. CKOUT that duty cycle is 50%.At another
In embodiment, can also with logic or other logics.
Before period 1 T1, due to not carrying out state analysis to carry signal CO and fractional frequency signal CKOUT, therefore in Fig. 3
Its state is represented by dashed line.
Subtraction circuit 101, negative circuit 102, add circuit 103 are common circuits, are no longer illustrated herein.
Fig. 4 shows adjusting circuit 40 according to an embodiment of the invention, and adjusting circuit 40 includes：
Compensation circuit 41, has first input end, the second input terminal and output terminal, its first input end receives the input
Clock signal CKIN, its second input terminal receive the carry signal CO, and the compensation circuit 41 is based on the clock signal
CKIN compensates the pulse width of the carry signal CO and provides the thermal compensation signal CP that duty cycle is 50% in output terminal；
And
Selection circuit 42, has selection end, first input end, the second input terminal and output terminal, it is selected described in the reception of end
Divide low level signal DIV<0>(lowest order of frequency dividing ratio signal), its first input end receive the carry signal CO, it second
Input terminal receives the thermal compensation signal CP, selects one to provide the fractional frequency signal CKOUT in its output terminal.Work as even frequency division
When, it is fractional frequency signal CKOUT directly to provide carry signal CO, and when frequency division by odd integers compensates the duty cycle of carry signal CO to 50%
It is re-used as fractional frequency signal output.
Fig. 5 shows adjusting circuit 50 according to an embodiment of the invention, and adjusting circuit 50 includes：
First phase inverter I1, has input terminal and output terminal, and input terminal is coupled to frequency dividing low level signal DIV<0>, divide low
Position signal DIV<0>Output signal DIV_N is obtained by the first phase inverter I1<0>.
First and door A1, there is first input end, the second input terminal and output terminal, first input end to be coupled to add circuit
For 103 output terminal to receive the carry signal CO of add circuit 103, the second input terminal is coupled to the output terminal of phase inverter I1 to connect
Receive the output signal DIV_N of phase inverter I1<0>, the input signal of first input end and the second input terminal passes through with computing first
Output signal AO1 is produced with the output terminal of door A1.
Second and door A2, has first input end, the second input terminal and output terminal, first input end input frequency dividing low level letter
Number DIV<0>, the second input terminal is coupled to the output terminal of add circuit 103 to receive the carry signal CO of add circuit 103, and
The input signal of one input terminal and the second input terminal is passed through produces output signal AO2 with computing in the output terminal of second and door A2.
Second phase inverter I2, has input terminal and output terminal, and input terminal receives input clock signal CKIN, input clock letter
Number CKIN obtains output signal CKIN_N by the second phase inverter A2.
D type flip flop D1, there is first input end, the second input terminal and output terminal, first input end to be coupled to second and door
For the output terminal of A2 to receive the output signal AO2 of second and door A2, the second input terminal is coupled to the output terminal of the second phase inverter I2
To receive the output signal CKIN_N of phase inverter I2, the input signal of first input end and the second input terminal passes through d type flip flop D1,
Output signal DO1 is produced in its output terminal.
First OR gate O1, there is first input end, the second input terminal and output terminal, first input end to be coupled to first and door
Output terminal to receive the output signal AO1 of first and door, the second input terminal is coupled to the output terminal of d type flip flop D1 to receive D
The first input end of output the signal DO1, the first OR gate O1 of trigger D1 and the input signal process of the second input terminal or computing
Output signal OUT1 is produced in its output terminal.
Second OR gate O2, has first input end, the second input terminal and output terminal, and first input end is coupled to the first OR gate
For the output terminal of O1 to receive the output signal OUT1 of the first OR gate O1, the second input terminal is coupled to the output terminal of add circuit 103
To receive the input signal of the first input end of the carry signal CO, the second OR gate O2 of add circuit 103 and the second input terminal warp
Cross or computing produces output signal CKOUT in its output terminal.
Adjust circuit 60 logical expression be：CKOUT=CO ↑ DIV_N<0>+CO↓·DIV<0>+ CO ↑ (" CO ↑ " generation
Carry signal CO when table input clock signal CKIN rising edges arrive, " CO ↓ " represents input clock signal CKIN trailing edges and arrives
Carry signal CO when coming).
This adjusts circuit and adds data selection function, can be to odd number or even frequency division than signal DIV<N:0>Into
Row selection, so as to decide whether that carry signal CO is adjusted, to realize final either frequency division by odd integers than input signal also
It is even frequency division than input signal, the output clock signal of 50% duty cycle is all obtained by frequency dividing circuit.Divide low level signal
DIV<0>The lowest order of frequency dividing ratio signal (input) due to being binary digit, only two kinds of values：0 or 1, both values are just
Representing all odd number even frequency divisions may.As frequency dividing low level signal DIV<0>When=0, it is meant that the frequency dividing ratio signal of input is
Even frequency division is than signal, and when a rising edge clock arrives, the first phase inverter I1 outputs are 1, first and door A1 outputs are CO
↑, second with door A2 output be 0, d type flip flop D1 output be 0, the first OR gate O1 output for CO ↑, the second OR gate O2 output for CO ↑
That is CKOUT=CO ↑, by logical expression also recall that CKOUT=CO ↑, that is, export clock signal CKOUT for input clock letter
Carry signal CO when number CKIN rising edges arrive；Work as DIV<0>When=1, it is meant that the frequency divider frequency dividing ratio signal of input is strange
Number frequency dividing ratio signal, when a rising edge clock arrives, the first phase inverter I1 outputs are 0, first and door A1 outputs are 0, the
Two with door output for CO ↑, when the trailing edge of this clock arrives, d type flip flop D1 produce non-zero outputs CO ↓, the first OR gate O1 is defeated
Go out for CO ↓, the second OR gate O2 output for CO ↑+CO ↓, i.e. CKOUT=CO ↑+CO ↓, CKOUT is equally drawn by logical expression
=CO ↑+CO ↓, that is, export the carry signal that clock signal CKOUT is add circuit when input clock signal CKIN rising edges arrive
When CO and input clock CKIN trailing edges arrive the carry signal CO phases of add circuit or as a result, this output clock signal is
By the signal of duty cycle adjustment (compensation), it has 50% duty cycle.
Fig. 6 shows adjusting circuit diagram 60 according to an embodiment of the invention.Adjusting circuit 60 includes：
First d type flip flop D1, there is first input end, the second input terminal and output terminal, first input end to be coupled to addition
The output terminal of circuit 103, to receive 103 carry signal CO of add circuit, the second input terminal receives input clock signal CKIN, the
The input signal of one input terminal and the second input terminal passes through d type flip flop D1, and output signal DO1 is produced in its output terminal；
First phase inverter I1, has input terminal and output terminal, and input terminal receives input clock signal CKIN, input clock letter
Number CKIN obtains output signal CKIN_N by the first phase inverter I1；
Second d type flip flop D2, there is first input end, the second input terminal and output terminal, first input end to be coupled to addition
The output terminal of circuit 103, to receive 103 carry signal CO of add circuit, the second input terminal is coupled to the defeated of the first phase inverter I1
Outlet is to receive the output signal CKIN_N of the first phase inverter I1, and the input signal of first input end and the second input terminal is by the
2-D trigger D2, output signal DO2 is produced in its output terminal；
First OR gate O1, has first input end, the second input terminal and output terminal, and first input end is coupled to the first D and touches
The output terminal of device D1 is sent out to receive the output signal DO1 of the first d type flip flop, the second input terminal is coupled to the second d type flip flop D2's
Output terminal to receive the output signal DO2 of the second d type flip flop D2, the input signal of first input end and the second input terminal pass through or
Computing produces output signal OUT1 in the output terminal of the first OR gate O1；
First NAND gate N1, has first input end, the second input terminal and an output terminal, first input end be coupled to first or
For the output terminal of door O1 to receive the output signal OUT1 of the first OR gate O1, the second input terminal is coupled to frequency dividing low level signal DIV<0
>, the input signal of first input end and the second input terminal produces output letter by NAND operation in the first NAND gate N1 output terminals
Number NOUT1；
Second phase inverter I2, has input terminal and output terminal, and input terminal is coupled to frequency dividing low level signal DIV<0>, divide low
Position signal DIV<0>Output signal DIV_N is produced by the second phase inverter I2<0>；
Second NAND gate N2, has first input end, the second input terminal and output terminal, it is anti-that first input end is coupled to second
The output terminal of phase device I2 is to receive the output signal DIV_N of the second phase inverter I2<0>, the second input terminal is coupled to add circuit
103 output terminal to receive the carry signal CO of add circuit 103, pass through by the input signal of first input end and the second input terminal
NAND operation produces output signal NOUT2 in the output terminal of the second NAND gate N2；
3rd NAND gate N3, has first input end, the second input terminal and an output terminal, first input end be coupled to first with
For the output terminal of NOT gate N1 to receive the output signal NOUT1 of the first NAND gate N1, the second input terminal is coupled to the second NAND gate N2
Output terminal to receive the output signal NOUT2 of the second NAND gate N2, the input signal warp of first input end and the second input terminal
Cross NAND operation and produce output signal CKOUT in the output terminal of the 3rd NAND gate N3.
Its logical expression is：CKOUT=CO ↑ DIV_N<0>+(CO↓+CO↑)·DIV<0>.This duty cycle adjustment
(compensation) circuit equally adds data selection function, and odd number or even frequency division can be made choice than signal, so that certainly
The fixed adjusting (compensation) that circuit whether is carried out by compensation circuit, to realize final either odd divider frequency dividing ratio input letter
Number or even number divider frequency dividing ratio input signal, the output clock signal of 50% duty cycle can be obtained by frequency dividing circuit.
Work as DIV<0>When=0, it is meant that the frequency dividing ratio signal of input for even frequency division than signal, when an input clock CKIN rising edge
No matter what signal the first input end of N1 inputs during arrival, NOUT1 outputs are all 1, while the output letter of the second phase inverter I2
Number DIV_N<0>=1, N2 output are CO ↑ negate, N3 outputs for CO ↑, by logical expression also recall that CKOUT=CO ↑, i.e.,
It is carry signal when input clock signal CKIN rising edges arrive to export clock signal CKOUT；Work as DIV<0>When=1, meaning
The frequency dividing ratio signal for input is frequency division by odd integers than signal, when an input clock CKIN rising edge arrives, the second phase inverter
The output signal DIV_N of I2<0>=0, no matter the second input signal CO of N2 ↑ why be worth, the output NOUT2 of N2 is 1, together
When, the first d type flip flop D1 outputs CO ↑, when this input clock signal CKIN trailing edges arrive, the second d type flip flop D2 outputs CO
↓, the first OR gate output OUT1=CO ↑+CO ↓, NOUT1 outputs are negated for (CO ↑+CO ↓), NOUT3 outputs for CO ↑+CO ↓, pass through
Logical expression be known that CKOUT=CO ↑+CO ↓, that is, export clock signal CKOUT be input clock signal CKIN rising edges
Carry signal CO when carry signal CO during arrival arrives with input clock signal CKIN trailing edges carry out or computing as a result,
This output clock signal is equally by the signal of duty cycle adjustment (compensation), it has 50% duty cycle.
Fig. 7 shows adjusting circuit diagram 70 according to an embodiment of the invention.Compared with adjusting circuit 60, circuit is adjusted
70 main distinction is：Second d type flip flop D2, has first input end, the second input terminal and output terminal, first input end coupling
It is connected to the first d type flip flop D1 output terminals (receive the first d type flip flop D1 outputs signal DO1), rather than the output of add circuit 103
End is (receive 103 carry signal CO of add circuit).
Fig. 8 shows the flow chart of high speed dividing method 80 according to an embodiment of the invention.Including：
Step 81：One N frequency dividing ratio signal DIV is provided<N:0>With input clock signal CKIN；
Step 82：In each rising edge or trailing edge of input clock signal CKIN, the frequency dividing ratio signal subtracts 1 successively
Obtain
Obtain subtraction signal DIV_O<N:0>；
Step 83：By the subtraction signal DIV_O<N:0>It is anti-phase, obtain anti-reflection signal DIV_N<N:0>；
Step 84：Height (N-1) position of N frequency dividing ratio signals is taken, obtains dividing high half signal DIV<N:1>；
Step 85：By the anti-reflection signal DIV_N<N:0>With the high half signal DIV of frequency dividing<N:1>Be added, obtain into
Position letter
Number CO.
CO is obtained fractional frequency signal, as frequency dividing ratio signal DIV<N:0>For 100 when, the frequency of carry signal CO is defeated
Enter the 1/4 of clock signal；As frequency dividing ratio signal DIV<N:0>For 110 when, the frequency of carry signal CO is input clock signal
1/6.The corresponding ten's digit of fractional frequency signal is divider ratios.
One embodiment according to the present invention, dividing method 80 further include, if the high half signal DIV of frequency dividing<N:1>With institute
State anti-reflection signal DIV_N<N:0>The sum of need carry, then the carry signal be 1；If the high half signal DIV of frequency dividing<N:1>With
The anti-reflection signal DIV_N<N:0>The sum of without carry, then the carry signal is 0.
In even frequency division (2 frequency dividings, 4 frequency dividings ...), the duty cycle of carry signal CO is 50%；And in frequency division by odd integers
(3 frequency dividings, 5 frequency dividings ...), the duty cycle of carry signal CO cannot be 50%.To overcome this problem, one according to the present invention
Embodiment, dividing method 80 further include step 86：If the frequency dividing ratio signal lowest order is first state, there is provided the carry letter
Number it is used as fractional frequency signal；If the frequency dividing ratio signal lowest order is the second state, adjust the pulse width of the carry signal with
So that the duty cycle of the carry signal is substantially equal to 50%.
One embodiment according to the present invention, dividing method 80 further include, and the pulse to the carry signal CO is wide
It is wide that the pulse including adding or subtracting input clock signal CKIN for the pulse width of the carry signal CO is adjusted in degree
Degree.
One embodiment according to the present invention, dividing method 80 further include, and the duty cycle of the input clock signal is 50%,
The carry signal adjusted signal CO ' of CO are sampled in input clock signal trailing edge, carry signal CO and Regulate signal CO ' are taken
Or obtain the fractional frequency signal that duty cycle is 50%.
One embodiment according to the present invention, the pulse based on the input clock signal CKIN to the carry signal CO are wide
Degree compensates and is substantially 50% thermal compensation signal CP in output terminal offer duty cycle；Based on the frequency dividing low level signal DIV<
0>The carry signal CO and thermal compensation signal CP is selected, selects one as the fractional frequency signal CKOUT
One embodiment according to the present invention, frequency dividing ratio signal DIV<N:0>For the divider ratios of the high-speed frequency divider, example
As 100 correspondence, 4 frequency dividing, 110 corresponds to 6 frequency dividings.
One embodiment according to the present invention, is 111 after subtracting 1 if the frequency dividing ratio signal is 000.
Although the present invention has been combined its specific illustrative embodiment and is described, it is therefore apparent that, it is a variety of it is alternative,
Modification and variation will be readily apparent to one having ordinary skill.Thus, the exemplary embodiment party of the invention illustrated herein
Formula is schematical and and non-limiting.It can modify without departing from the spirit and scope of the present invention.In every case
It is the content without departing from technical solution of the present invention, what the technical spirit according to the present invention made above example any simply repaiies
Change, equivalent variations and modification, in the range of still falling within technical solution of the present invention.
In this disclosure used measure word "one", " one kind " etc. be not excluded for plural number." first " in text, "
Two " etc. are merely represented in the sequencing occurred in the description of embodiment, in order to distinguish like." first ", " second " exist
Appearance in claims is only for the purposes of the fast understanding to claim rather than in order to be limited.Right will
Any reference numeral in book is asked to should be construed as the limitation to scope.
Claims (10)
1. a kind of high speed dividing method, including
A N frequency dividing ratio signal and input clock signal are provided, wherein N is the integer more than 1；
In the rising edge or trailing edge of each input clock signal, acquisition subtraction signal that the frequency dividing ratio signal subtracts 1 successively；
The subtraction signal is anti-phase, obtain anti-reflection signal；
Height (N-1) position of N frequency dividing ratio signals is taken, obtains dividing high half signal；
The anti-reflection signal is added with high half signal of frequency dividing, obtains carry signal；And
Carry signal is provided as fractional frequency signal.
2. high speed dividing method according to claim 1, it is characterised in that if high half signal of frequency dividing and the anti-reflection
The sum of signal needs carry, then the carry signal is 1；If frequency dividing the sum of high half signal and the anti-reflection signal need not be into
Position, then the carry signal is 0.
3. high speed dividing method according to claim 1, it is characterised in that each input clock signal rising edge or
Person's trailing edge, the anti-reflection signal is added with high half signal of frequency dividing, obtains carry signal.
4. high speed dividing method according to claim 1, it is characterised in that the offer carry signal is as fractional frequency signal
Further include：If the lowest order of the frequency dividing ratio signal is first state, there is provided the carry signal is as fractional frequency signal；
If the lowest order of the frequency dividing ratio signal is the second state, the pulse width of the carry signal is adjusted to provide
Duty cycle is substantially equal to 50% fractional frequency signal.
5. high speed dividing method according to claim 4, it is characterised in that the pulse to the carry signal is wide
Degree is adjusted including adding or subtracting input clock signal pulse width for the pulse width of the carry signal.
6. high speed dividing method according to claim 4, it is characterised in that the duty cycle of the input clock signal is
50%, the adjusted signal of carry signal is sampled in input clock signal trailing edge, carry signal and Regulate signal are taken or obtained
To the fractional frequency signal that duty cycle is 50%.
7. high speed dividing method according to claim 4, it is characterised in that based on the input clock signal to it is described into
The pulse width of position signal compensates and is substantially 50% thermal compensation signal in output terminal offer duty cycle；Based on the frequency dividing
Lowest order than signal makes choice the carry signal and the thermal compensation signal, selects one as the fractional frequency signal.
8. high speed method according to claim 1, it is characterised in that the corresponding ten's digit of the frequency dividing ratio signal is
The divider ratios of the high-speed frequency divider.
9. high speed method according to claim 1, it is characterised in that if the frequency dividing ratio signal is 000, be after subtracting 1
111。
10. there is the high-speed frequency divider of duty cycle adjustment a kind of, including：
Subtraction circuit, has first input end, the second input terminal and output terminal, the first input end and the second input terminal difference
Frequency dividing ratio signal and input clock signal are received, the subtraction circuit is based on the input clock signal and frequency dividing ratio signal is carried out
Subtraction, and subtraction signal is provided in its output terminal, the frequency dividing ratio signal is N position digital signals, and wherein N is more than 1
Integer；
Negative circuit, has input terminal and output terminal, and the output terminal that its input terminal is coupled to the subtraction circuit is described to receive
Subtraction signal, its output terminal provide anti-reflection signal；And
Add circuit, has first input end, the second input terminal and output terminal, its first input end is coupled to the negative circuit
Output terminal to receive the anti-reflection signal, its second input terminal, which receives, divides high half signal, high half signal of frequency dividing for point
Height (N-1) position of frequency ratio signal, its output terminal provide carry signal, and the add circuit is to the anti-reflection signal and the frequency dividing
High half signal carries out add operation；And
Circuit is adjusted, there is control terminal, first input end, the second input terminal and output terminal, when its control terminal receives the input
Clock signal, its first input end receive the lowest order of the frequency dividing ratio signal, its second input terminal is coupled to the add circuit
Output terminal to receive the carry signal, its output terminal provide fractional frequency signal；The adjusting circuit includes：
First d type flip flop, there is first input end, the second input terminal and output terminal, first input end to be coupled to add circuit
For output terminal to receive carry signal, the second input terminal receives input clock signal；
First phase inverter, has input terminal and output terminal, its input terminal receives input clock signal；
Second d type flip flop, there is first input end, the second input terminal and output terminal, first input end to be coupled to add circuit
Output terminal is coupled to the output terminal of the first phase inverter to receive carry signal or the first d type flip flop output terminal, the second input terminal；
First OR gate, has first input end, the second input terminal and output terminal, and first input end is coupled to the first d type flip flop
Output terminal, the second input terminal are coupled to the output terminal of the second d type flip flop；
First NAND gate, has first input end, the second input terminal and output terminal, and first input end is coupled to the defeated of the first OR gate
Outlet, the second input terminal receive frequency dividing ratio signal lowest order；
Second phase inverter, has input terminal and output terminal, and input terminal receives frequency dividing ratio signal lowest order；
Second NAND gate, has first input end, the second input terminal and output terminal, and first input end is coupled to the second phase inverter
Output terminal, the second input terminal are coupled to the output terminal of add circuit；And
3rd NAND gate, has first input end, the second input terminal and output terminal, and first input end is coupled to the first NAND gate
Output terminal, the second input terminal are coupled to the output terminal of the second NAND gate, its output terminal provides the fractional frequency signal.
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| CN117081582A (en) * | 2023-05-12 | 2023-11-17 | 南京筠芯科技有限公司 | Frequency division method for realizing 50% duty ratio and frequency divider |
| CN117081582B (en) * | 2023-05-12 | 2024-04-23 | 南京筠芯科技有限公司 | Frequency division method for realizing 50% duty ratio and frequency divider |
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