JPH09162732A - Fraction-n frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress sprious by setting the decimal sections of variable frequency ratio according to the integral ratio of two counters and adding a triangular waveform signal, which is generated based on the counting terms of respective counters, to the output signal of phase comparator. SOLUTION: Setting values M and A (M>A) are respectively set to 1st and 2nd counters 6 and 7. During the A cycle of input signal, an 'H' signal is sent to a variable frequency divider 5 and during the (M-A) cycle, an 'L' signal is sent to the variable frequency divider respectively by a switching signal generating circuit 8. Since the variable frequency divider 5 respectively switches the frequency dividing ratio to (N+1) and N corresponding to the 'H' and 'L' signals, (N+A/M) is provided as an average frequency dividing ratio. In this case, a triangular wave signal (7), which is provided by passing an output signal (3) of switching signal generating circuit 8 through a level shift circuit 9 and integrating it at an integrator 9, is suitably negatively weighted and added later to an output (5) of phase comparator 7. Thus, the cycle change in the output of phase comparator 7 is canceled without using any D/A converter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer, and more particularly to a fractional N frequency synthesizer capable of obtaining a frequency resolution below a reference frequency.

[0002]

2. Description of the Related Art The structure of a conventional fractional-N frequency synthesizer is shown in FIG. In this figure, 1 is a phase comparator, 3 is a loop filter, 4 is a voltage controlled oscillator (VCO), 5 is a variable frequency divider, and 20 is an accumulator. The accumulator comprises an n-bit adder 21 and an n-bit latch 22.

The accumulator 20 accumulates the data K input to the adder 21 every time a reference signal is input. The adder 21 sends an overflow signal to the variable frequency divider 5 when the content becomes 2 ⁿ or more due to the accumulation operation. When the variable frequency divider 5 receives this overflow signal, it changes the frequency division ratio from the integer value N to N + 1.

At this time, the frequency division ratio of the variable frequency divider 5 is N + 1 out of K times of the reference signal input of 2 ⁿ times and N out of (2 ⁿ −K) times. Therefore, the division ratio N averaged over 2 ⁿ cycles
_AVE is represented by the sum of the integer part N and the fractional part K / 2 ⁿ shown in “ _Equation 1”.

[0005]

[Equation 1]

Therefore, _assuming that the reference frequency is f _REF , the oscillation frequency f _VCO of the VCO when phase-locked is "Equation 2".
As shown in FIG. 5, f _VCO is changed by a frequency step of 1/2 ⁿ of the reference frequency f _REF by changing the data K one by one.

[0007]

(Equation 2)

Therefore, the reference frequency can be set to 2 ⁿ times higher than the frequency step. Generally, in a phase locked loop, the higher the reference frequency, the better the phase noise characteristic and the faster the frequency switching speed. However, in the fractional-N frequency synthesizer, spurious is generated due to the periodic switching of the frequency division ratio.

If the bandwidth of the loop filter is reduced to suppress this spurious, the frequency switching speed becomes slow. A specific example of a circuit that reduces such spurious is described in, for example, the document “U. Rohde, Digital PLL Frequency.
Synthesizers, Prentice-Hall, 1983. "and the like.

FIG. 7 shows an example of the configuration of a conventional fractional-N frequency synthesizer to which a spurious reduction circuit is added. In this figure, 18 is a DA converter (DAC) and 2 is an adder. A timing chart showing the operation of this conventional example is shown in FIG. In FIGS. 7 and 8, is the output of the VCO 4, is the output of the variable frequency divider 5, is the reference signal, is the logical operation of the phase comparator 1, is the circled 10 (hereinafter referred to as (10) in the text). Represents the output of the DAC 18.

In FIG. 8, the frequency division ratio N of the variable frequency divider 5 is set to 2, and when the overflow signal of the adder 21 is received, the frequency division ratio is changed to 3. The number of bits n of the accumulator 20 is 3, and an overflow occurs when 2 ³ = 8. In addition, the data K input to the adder 21 is set to 3
And

First, it is assumed that the output signal of the variable frequency divider 5 and the reference signal are in phase with each other. The contents of the adder 21 are accumulated as 3 and 6 for each input of the reference signal. At this time, the frequency division ratio of the variable frequency divider 5 is 2, and the signal is VC
It rises at the second and fourth output signals of O4. The content of the adder 21 becomes 9 at the next reference signal input, but overflow occurs, and the accumulation operation is continued with the remaining 1 obtained by subtracting 8 as the initial value.

Further, the frequency division ratio of the variable frequency divider 5 is changed to 3 by the overflow signal. The contents of the adder 21 are
It returns to the initial value in 8 cycles of the reference signal, and in 8 cycles,
Overflow 3 times. It is the 19th signal that the signal rises in the eighth cycle of the reference signal.

Therefore, the average division ratio of the signal is 19/8.
= 2 + (3/8). On the other hand, the reference signal has a constant frequency and a period of 19/8 times that of the signal. The pulse width of the signal indicating the logical operation of the phase comparator 1 changes according to the phase difference between the signal and the reference signal. The width is initially 0, and then (19/8) -2 = 3/8, (38/8)-.
It changes to 4 = 6/8.

The actual output of the phase comparator 1 is a waveform obtained by integrating signals, and has a voltage proportional to the phase difference. The VCO is controlled by this voltage, but since the pulse width of the signal changes periodically, spurious is generated.

Looking at the contents of the adder 21, it can be seen that it changes in proportion to the pulse width of the signal. Therefore, the signal (10) obtained by converting the output signal of the accumulator 20 into an analog voltage by the DAC 18 is inverted, and the adder 2 appropriately weights and adds the signals, thereby canceling the periodic change in the output of the phase comparator 1. , Spurious can be reduced.

[0017]

The conventional fractional-N frequency synthesizer as described above requires a DA converter. However, the DA converter has a large circuit scale and a high production cost, which impairs economic efficiency. was there. Further, the fractional-N frequency synthesizer is characterized in that the reference frequency is set higher than the frequency step, but the DA converter also needs to operate at the raised reference frequency, resulting in a problem that power consumption also increases.

An object of the present invention is to provide a fractional-N frequency synthesizer which can be realized at low cost without using a DA converter, has low power consumption, and has small spurious.

[0019]

According to the invention, the above-mentioned object is solved by the means described in the claims.

That is, according to the first aspect of the invention, the voltage controlled oscillator whose oscillation frequency is set by the voltage inputted to the frequency control terminal and the output of this voltage controlled oscillator are inputted and divided by the logical level of the switching signal. A variable frequency divider that switches the frequency ratio to either an integer N or N + 1;

By comparing the phase difference between the output of the variable frequency divider and the reference signal, a voltage proportional to the phase difference, a pulse having a time width corresponding to the phase difference, or a voltage obtained by integrating the same is output. Phase comparator to

A loop filter for feedback connecting the output of the phase comparator to the frequency control terminal of the voltage controlled oscillator;
When the output of the variable frequency divider is input and the integer M is set and the input pulse is counted by the set value M, a first counter that outputs a signal indicating this,

When the output of the variable frequency divider is input and an integer A smaller than the set value M of the first counter is set and the input pulse is counted by the set value A, a signal notifying this is output and the count is made. A second counter that stops the operation and restarts the counting operation when the first counter counts the set value M.

A switching signal generating circuit for inverting the logic level of the output when the first counter counts the input pulse by the set value M and when the second counter counts the input pulse by the set value A; An output of the switching signal generating circuit or an inverted output thereof is input, and a level shift circuit for converting the DC level thereof,

An output of the level shift circuit is input, and an integrator for outputting the integrated value is provided, and the output of the switching signal generating circuit is used as a frequency division ratio switching signal of the variable frequency divider. A fractional-N frequency synthesizer configured by adding or subtracting the output of the integrator to the output of the phase comparator.

According to a second aspect of the present invention, in the fractional-N frequency synthesizer according to the first aspect, when the first counter counts the input pulse by a set value M, an output signal for notifying the input pulse, and When the second counter counts the input pulse by the set value A, the output signal for notifying it is constructed by inverting the logic level of the output signal.

[0027]

FIG. 1 is a diagram showing an example of an embodiment of a fractional-N frequency synthesizer of the present invention. In this figure, numeral 1 is a phase comparator, 2 is an adder, 3 is a loop filter, 4 is a voltage controlled oscillator (VCO), 5 is a variable frequency divider, 6 is a first counter, 7 is a second counter. counter,
Reference numeral 8 represents a switching signal generating circuit, 9 represents a level shift circuit, and 10 represents an integrator. The symbols (1) to (4) in the figure associate the signal at that location with the waveform shown in FIG.

The set value of the first counter 6 is M, the set value of the second counter 7 is A, and M> A. The second counter 7 stops the counting operation when the input pulse is counted by the set value A. Next, when the first counter 6 counts the input pulse by the set value M, the first counter 6 and the second counter 7 are reset to the initial set values, and the operation is repeated.

The switching signal generating circuit 8 operates when the first counter counts the input pulse by the set value M and when the second counter counts the input pulse by the set value A.
Inverts the logic level of its output. Therefore, the output of the switching signal generating circuit 8 switches between high and low levels in the A cycle and (MA) cycle of the input signal. It is now assumed that the input signal is "high" in the A cycle and "low" in the (MA) cycle.

The variable frequency divider 5 divides the frequency division ratio into N and N + according to the high / low level of the output signal of the switching signal generation circuit 8.
Switch to 1. Now, when the output of the switching signal generation circuit 8 is "high", the division ratio is (N + 1), and when it is "low", the division ratio is N.
Then, the frequency division ratio N _AVE obtained by averaging the frequency division ratios of the variable frequency divider 5 over M cycles is as shown in “ _Equation 3”, and N _AVE is an integer part N and a fraction part A It is represented by the sum of / M.

[0031]

(Equation 3)

Therefore, assuming that the reference frequency is f _REF , the oscillation frequency f _VCO of the VCO when the phases are synchronized is "Equation 4".
By changing the setting value A of the second programmable counter 6 by 1, f _VCO changes at a step frequency of 1 / M of the reference frequency f _REF .

[0033]

(Equation 4)

FIG. 2 is a timing chart showing the operation of the example of the embodiment shown in FIG. 1 and 2, is the output of VCO 4, is the output of variable frequency divider 5,
Is the output of the switching signal generating circuit 8, is the reference signal, is the logical operation of the phase comparator 1, is the output of the level shift circuit 9,
Represents the output of the integrator 10.

In FIG. 2, the frequency division ratio N of the variable frequency divider 5 is set to 2. When the output signal of the switching signal generation circuit 8 is "high", the frequency division ratio is changed to 3. Further, the setting value M of the first counter 6 is 8, and the setting value A of the second counter 7 is 3
And

First, it is assumed that the output signal of the variable frequency divider 5 and the reference signal are in phase with each other, and the output signal of the switching signal generating circuit 8 is "high". Therefore, the variable frequency divider 5
Has a frequency division ratio of 3, and the output rises at the 3rd and 6th output signals of the VCO 4. Next, when the signal rises to the ninth signal, the second counter 7 finishes counting the set value 3 and stops the counter operation, and the output signal of the switching signal generation circuit 8 becomes "low". .

Accordingly, the frequency division ratio of the variable frequency divider 5 is changed to 2. The first counter 6 finishes counting the set value 8 when the signal rises to the 19th signal. Therefore, the average division ratio of the signal is 19/8 = 2
It becomes + (3/8). On the other hand, the reference signal has a constant frequency and a period of 19/8 times that of the signal.

The signal indicating the logical operation of the phase comparator 1 is
The pulse width changes depending on the phase difference between the signal and the reference signal. Its width is initially 0, then 3- (19/8) = 5
/ 8,6- (38/8) = 10/8. The actual output of the phase comparator 1 is a waveform obtained by integrating the signal,
The voltage is proportional to the phase difference. Although the VCO is controlled by this voltage, the pulse width of the signal changes periodically, so if it is applied to the VCO as it is, spurious is generated.

Therefore, the output signal of the switching signal generating circuit 8 is branched and input to the level shift circuit. FIG. 3 shows an example of the level shift circuit. In the figure, reference numeral 31 is a capacitor, 32 is a resistor, and 33 is a coil.
When the time constant of the level shift circuit is selected to be a value that sufficiently follows the change in the input, the average DC level of the output is 0, and the output waveform is the same as the input waveform.

This state is shown in FIG. Since the ratio of the input time of the level shift circuit 9 being high and being low is 9:10, the voltage ratio between the high level and the low level is 10: 9. Therefore, the signal obtained by integrating this signal monotonically increases at the time of the high level of the signal and monotonically decreases at the time of the low level of the same voltage value at the 0th time and the 19th time of the signal. It becomes a certain triangular wave.

This signal changes in proportion to the pulse width of the signal. Therefore, by inverting the signals and adding the weights appropriately by the adder 2, it is possible to cancel the periodic change in the output of the phase comparator 1 and reduce the spurious.

As described above, according to the present invention, DA
A fractional-N frequency synthesizer with small spurious can be realized with a simple additional circuit without using a converter, and a frequency resolution below the reference frequency can be obtained.

4 and 5 show the experimental results of the example of the embodiment of the present invention as described above, which is constructed by using the actual hardware. FIG. 4 is a drawing based on an observation waveform by an oscilloscope, and and in the figure show that the output is the same circuit as in FIG. FIG. 5 is a diagram in which the output of the frequency synthesizer is plotted based on the spectrum observed by the spectrum analyzer.

4 and 5 show the output frequency f of the VCO.
_VCOIs 4.83 GHz, reference frequency f _REFIs 80 MH
z, the frequency division ratio N of the variable frequency divider is 60, and the first counter is set.
If the constant value M is 16 and the setting value A of the second counter is 6,
5M under the standard frequency of 80MHz
You are getting a frequency step of Hz.

In FIG. 4, the output signal of the phase comparator has a waveform in which a reference frequency of 80 MHz and a triangular wave of 5 MHz are superimposed. On the other hand, the output of the integrator is 5 MH
It is a triangular wave of z. These are added by the adder.

FIG. 5A shows the output of the frequency synthesizer before addition, and FIG. 5B shows the output of the frequency synthesizer after addition. Before the addition, the level difference between the desired wave signal of 4.83 GHz and the spurious generated at a position 5 MHz away from 4.83 GHz was 58 dB, but it can be seen that after the addition, it is greatly reduced to 83 dB.

According to the present invention, D
It can be seen that a fractional N frequency synthesizer with small spurious can be realized with a simple additional circuit without using an A converter.

In the example of the level shift circuit described above with reference to FIG. 3, one end of the resistor 32 or the coil 33 in FIG. 3 is grounded so that the average DC level of the output of the level shift circuit 9 becomes zero. However, the present invention is not limited to this, and the average DC level may be used as a certain reference potential. In this case, the integrator 10 may integrate the difference between the input signal and the reference potential.

Further, the branching of the output signal of the switching signal generation circuit 8 is not in-phase distribution, but signals in which they are mutually inverted are input to the variable frequency divider 5 and the level shift circuit 9,
It suffices if the polarities of the two input signals are inverted in the adder 2.

[0050]

As described above, according to the present invention,
It is possible to configure a fractional-N frequency synthesizer with small spurious noise by using a simple additional circuit without using a DA converter, low power consumption, good phase noise characteristics, and fast frequency switching speed. There is an advantage that the synthesizer can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the example of the embodiment of the present invention.

FIG. 3 is a diagram showing an example of a level shift circuit.

FIG. 4 is a diagram showing a waveform observed by an oscilloscope.

FIG. 5 is a diagram showing an observation result by a spectrum analyzer.

FIG. 6 is a diagram showing an example of a conventional fractional-N frequency synthesizer.

FIG. 7 is a diagram showing an example of a fractional-N frequency synthesizer to which a conventional spurious reduction circuit is added.

FIG. 8 is a timing chart showing an operation of a fractional-N frequency synthesizer to which a conventional spurious reduction circuit is added.

[Explanation of symbols]

 1 phase comparator 2 adder 3 loop filter 4 voltage controlled oscillator 5 variable frequency divider 6 first counter 7 second counter 8 switching signal generation circuit 9 level shift circuit 10 integrator 20 accumulator 21 adder 22 latch 31 capacitor 32 resistance 33 coil

Claims (2)

[Claims] 1. A voltage-controlled oscillator whose oscillation frequency is set by a voltage input to a frequency control terminal, and an output of this voltage-controlled oscillator are input, and the division ratio is an integer N or N + 1 depending on the logic level of a switching signal. Of the variable frequency divider that switches to either of the two, and the phase difference between the output of this variable frequency divider and the reference signal, and a voltage proportional to the phase difference, or a pulse with a time width corresponding to the phase difference, or , A phase comparator that outputs a voltage that integrates the output, a loop filter that feeds back the output of the phase comparator to the frequency control terminal of the voltage controlled oscillator, and an output of the variable frequency divider, and an integer M Is set and the input pulse is counted by the set value M, the first counter that outputs a signal notifying this and the output of the variable frequency divider are input and the set value M of the first counter is set. When a small integer A is set and the input pulse is counted by the set value A, a signal indicating this is output and the count operation is stopped, and when the first counter counts the set value M, the count operation is performed. A switch for inverting the logic level of the output when the second counter restarts and when the first counter counts the input pulse by the set value M and when the second counter counts the input pulse by the set value A A signal generation circuit, the output of this switching signal generation circuit or an inverted version of this output is input, and a level shift circuit that converts the DC level thereof and the output of this level shift circuit are input and the integrated value is output. And an output of the switching signal generation circuit as a switching signal of the division ratio of the variable frequency divider, the output of the integrator, the phase A fractional-N frequency synthesizer characterized by adding or subtracting to the output of a comparator. 2. A first counter sets an input pulse to a set value M.
When counting only, the output signal to inform this,
2. The fractional-N frequency synthesizer according to claim 1, wherein when the second counter counts the input pulse by the set value A, the output signal for notifying it is obtained by inverting the logic level of the output signal.