CN117081582A - Frequency division method for realizing 50% duty ratio and frequency divider - Google Patents

Frequency division method for realizing 50% duty ratio and frequency divider Download PDF

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CN117081582A
CN117081582A CN202310531702.1A CN202310531702A CN117081582A CN 117081582 A CN117081582 A CN 117081582A CN 202310531702 A CN202310531702 A CN 202310531702A CN 117081582 A CN117081582 A CN 117081582A
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CN117081582B (en
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黄海平
刘海涛
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Nanjing Junxin Technology Co ltd
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Nanjing Junxin Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

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  • Manipulation Of Pulses (AREA)

Abstract

The invention discloses a frequency dividing method and a frequency divider for realizing 50% duty ratio, which are used for realizing N frequency division; n is expressed as binary form Bit < N:0>; the addition counter circuit performs An incremental count and generates a pulse signal An-A0 in the counting process; the down counter circuit performs down counting and generates pulse signals Sn-S0 and SR in the counting process; the time sequence generating circuit generates time sequence signals P0, P1, P2_even and P2_odd according to An-A0, sn-S0 and SR; the logic control circuit gates the signals of the corresponding channels so that the duty ratio of the output clock signals is 50% at different frequency division ratios. In the technical scheme, in the process of up-counting of the adder and down-counting of the subtracter, the output values of the adder and the subtracter are equal in a certain clock period to logically judge so as to obtain a pulse signal, and a target pulse signal P_2 which is one clock period or two clock periods different from the pulse signal is obtained based on the pulse signal, so that when the wide-range frequency division ratio is realized, the duty ratio of the signal can be ensured to be 50%.

Description

Frequency division method for realizing 50% duty ratio and frequency divider
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to a frequency dividing method and a frequency divider for realizing 50% duty ratio.
Background
A frequency divider is a very widely used digital circuit that is used to divide a given frequency to obtain the desired frequency. The most common method is to use a phase-locked loop synthesis method, which can synthesize very high frequencies, so that the application is very wide, however, the frequency divider circuit obtained by using the method has a complex structure and is difficult to realize a clock signal with 50% duty cycle.
On the other hand, although it is theoretically possible to achieve an arbitrary frequency division ratio by dividing the clock signal by the counter, the duty ratio is generally poor, and particularly, the larger the frequency division ratio is, the worse the duty ratio is, and improvement is desired.
Disclosure of Invention
The invention aims to provide a frequency dividing method and a frequency divider for realizing 50% duty ratio, which can still maintain the duty ratio of a signal to be 50% when different frequencies are output.
In order to achieve the above object, the solution of the present invention is:
a frequency division method for realizing 50% duty ratio is used for realizing N frequency division, and corresponding processing is carried out on a clock signal CK corresponding to the following different conditions:
in case one, when realizing one frequency division, outputting a clock signal CK;
in case two, when the divide-by-two is implemented, the output signal fout=p_0, the signal p_0 is generated from the pulse signal generated when the counter counts to N-1;
in case three, when implementing the divide-by-three, the output signal fout=or (p_0, p_1), where the signal p_1 is generated by: counting to N-1 by a counter, and delaying for half a period to generate a pulse signal P_1;
in case four, when the frequency division is performed an even number of times and N is equal to OR greater than 4, the output signal fout=or (p_0, p_2_even), wherein the signal p_2_even is generated in the following manner: starting at a certain moment, starting to count down by N, starting to count up by 0, and when the count reaches N/2 at the same time, delaying the pulse signal obtained by one period again to obtain P_2_even;
in case five, when the frequency division is performed for an odd number of times and N is equal to OR greater than 5, the output signal fout=or (p_1, p_2_odd) is generated by: starting at a certain moment, starting from N to count down, starting from 1 to count up, and outputting a pulse signal when the counts of the two sides are the same, wherein the pulse signal obtained by delaying the pulse signal by two periods is P_2_odd.
A frequency divider realizing a duty cycle of 50% for realizing frequency division by N; the binary form of N is expressed as Bit < N:0>; the frequency divider comprises an up counter circuit, a down counter circuit, a time sequence generating circuit, a clock signal generating circuit, a signal selecting circuit and a logic control circuit;
the addition counter circuit is reset and then performs incremental counting, generates a pulse signal An-A0 in the counting process, and sends the pulse signal An-A0 to the time sequence generating circuit;
the down counter circuit is reset and then performs down counting, generates pulse signals Sn-S0 and SR in the counting process, and sends the pulse signals Sn-S0 and SR to the time sequence generating circuit;
the time sequence generating circuit is used for generating time sequence signals P0, P1, P2_even and P2_odd according to the pulse signal An-A0 generated by the up counter circuit and the pulse signals Sn-S0 and SR generated by the down counter circuit and is connected to the signal selecting circuit;
the clock signal generation circuit is used for generating a clock signal CK, and the clock signal CK is used for the operation of the up-counter circuit, the down-counter circuit and the time sequence generation circuit respectively;
the logic control circuit sends a control signal to the signal selection circuit, the signal selection circuit gates the signals of the corresponding channels, and the signals with the duty ratio of 50% are output.
The signals are all generated at the rising edge of the clock.
When n=1 to 7, the addition counter circuit includes an adder Q1, a first gate Q2, a first exclusive or gate Q3, a first or gate Q4, a second or gate Q5, and a first not gate Q6, where the input end of the first gate Q2 is connected to N and n+1, and the control end thereof is connected to Bit <0>; the output end of the first gating device Q2 is connected with one input end of a first exclusive OR gate Q3, the other input end of the first exclusive OR gate Q3 is connected with the output end of an adder Q1, the output end of the first exclusive OR gate Q3 is respectively connected with one input end of a first OR gate Q4 and one input end of a second OR gate Q5, the other input end of the first OR gate Q4 is connected with Bit <0>, the input end of a first NOT gate Q6 is connected with Bit <0>, and the output end of the first NOT gate Q6 is connected with the other input end of the second OR gate Q5; the output end of the first or gate Q4 is connected with the RST end of the adder Q1, the output end of the second or gate Q5 is connected with the SET end of the adder Q1, and the output end of the adder Q1 is also used as the output end of the addition counter circuit.
When n=1 to 7, the down counter circuit includes a subtractor Q34 and a three-input exclusive-or gate Q35, where an assigned end of the subtractor Q34 is connected to N, an output end of the subtractor Q34 is connected to an input end of the three-input exclusive-or gate Q35, and an output end of the subtractor Q34 is further used as an output end of the down counter circuit to output S2S1S0; the output terminal of the three-input exclusive-or gate Q35 is connected to the reset terminal of the subtractor Q34, and the output terminal of the three-input exclusive-or gate Q35 also serves as the output terminal of the down counter circuit, outputting SR.
The subtractor Q34 includes a first subtracting circuit Q7, a second subtracting circuit Q8, a third subtracting circuit Q9, a first three-input and gate Q10, a first two-input and gate Q11, a first D flip-flop Q12, and a second not gate Q13, where an input terminal of the first subtracting circuit Q7 is connected to an inverting output terminal thereof and is commonly connected to a first input terminal of the first three-input and gate Q10; the input end of the second subtracting block Q8 is connected with the inverting output end thereof and is commonly connected with the second input end of the first three-input AND gate Q10; the input end of the third subtracting block Q9 is connected with the inverting output end thereof and is commonly connected with the third input end of the first three-input AND gate Q10; the output end of the first three-input AND gate Q10 is connected with one input end of a first two-input AND gate Q11, the output end of the first two-input AND gate Q11 is connected with the input end of a first D trigger Q12, the output end of the first D trigger Q12 is connected with the other input end of the first two-input AND gate Q11 and is commonly connected with the input end of a second NOT gate Q13, and the output end of the second NOT gate Q13 is respectively connected with the SR ends of a first subtracting circuit Q7, a second subtracting circuit Q8 and a third subtracting circuit Q9 and is used as the SR signal output end of a subtracting counter circuit; the clock end of the first subtracting circuit Q7 is connected with the clock signal CK, and the output end of the first subtracting circuit Q7 is connected with the clock end of the second subtracting circuit Q8 and serves as the S0 signal output end of the subtracting counter circuit; the output end of the second subtracting circuit Q8 is connected with the clock end of the third subtracting circuit Q9 and is used as the S1 signal output end of the subtracting counter circuit; the output terminal of the third subtracting block Q9 serves as the S2 signal output terminal of the subtracting block.
The first subtracting circuit Q7, the second subtracting circuit Q8, and the third subtracting circuit Q9 have the same structure, and each includes a first transmission gate Q701, a fourth not gate Q702, a first nand gate Q703, a second transmission gate Q704, a second nand gate Q705, a third nand gate Q706, a fourth nand gate Q707, a third transmission gate Q708, a fifth nand gate Q709, a fourth transmission gate Q710, a sixth nand gate Q711, and a fifth not gate Q712, where one end of the first transmission gate Q701 is a D1 end of the first/second/third subtracting circuit Q7/Q8/Q9, and the other end thereof is connected to one input end of the first nand gate Q703 and one end of the second transmission gate Q704, respectively; the input end of the fourth NOT gate Q702 is used as the D2 end of the first/second/third subtracting circuit Q7/Q8/Q9, the output end of the fourth NOT gate Q702 is connected with one input end of the third NOT gate Q706, and the other input end of the third NOT gate Q706 is used as the SR end of the first/second/third subtracting circuit Q7/Q8/Q9 and is connected with one input end of the second NOT gate Q705; the output end of the third NAND gate Q706 is respectively connected with the other input end of the first NAND gate Q703 and one input end of the sixth NAND gate Q711; the output end of the second nand gate Q705 is connected to one input end of the fourth nand gate Q707 and one input end of the fifth nand gate Q709, the other input end of the fourth nand gate Q707 is connected to the output end of the first nand gate Q703 and one end of the third transmission gate Q708, and the output end of the fourth nand gate Q707 is connected to the other end of the second transmission gate Q704; the other end of the third transmission gate Q708 is connected to the other input end of the fifth nand gate Q709 and one end of the fourth transmission gate Q710, and the output end of the fifth nand gate Q709 is connected to the other input end of the sixth nand gate Q711 and the input end of the fifth not gate Q712, respectively, and the ends are also used as Q ends of the first/second/third subtraction circuits Q7/Q8/Q9; the output end of the sixth nand gate Q711 is connected to the other end of the fourth transmission gate Q710, and the output end of the fifth nand gate Q712 is used as the Qb end of the first/second/third subtracting block Q7/Q8/Q9.
When n=1 to 7, the timing generating circuit includes a second D flip-flop Q14, a third D flip-flop Q15, a third not gate Q16, a second exclusive nor gate Q17, a third exclusive nor gate Q18, a fourth exclusive nor gate Q19, a second three-input and gate Q20, a fourth D flip-flop Q21, a second two-input and gate Q22, a fifth D flip-flop Q23, a sixth D flip-flop Q24, a third two-input and gate Q25, and a seventh D flip-flop Q26, wherein a D terminal of the second D flip-flop Q14 is connected to an SR signal, and a Q terminal of the second D flip-flop Q14 outputs a timing signal P0; the clock end of the second D trigger Q14 is connected with a clock signal CK, the clock signal CK is also connected with the input end of a third NOT gate Q16, the output end of the third NOT gate Q16 is connected with the clock end of a third D trigger Q15, the D end of the third D trigger Q15 is connected with the Q end of the second D trigger Q14, and the Q end of the third D trigger Q15 outputs a time sequence signal P1; the two input ends of the second exclusive-or gate Q17 are respectively connected with signals S2 and A2, the two input ends of the third exclusive-or gate Q18 are respectively connected with signals S1 and A1, the two input ends of the fourth exclusive-or gate Q19 are respectively connected with signals S0 and A0, the output end of the second exclusive-or gate Q17, the output end of the third exclusive-or gate Q18 and the output end of the fourth exclusive-or gate Q19 are respectively connected with the three input ends of the second third input AND gate Q20, the output end of the second third input AND gate Q20 is connected with the D end of the fourth D trigger Q21, the Q end of the fourth D trigger Q21 is respectively connected with one input end of the second two input AND gate Q22 and the D end of the sixth D trigger Q24, the output end of the second two input AND gate Q22 is connected with the clock end of the fifth D trigger Q23, the D end of the fifth D trigger Q23 is connected with the Qb end, and the Q end of the fifth D trigger Q23 outputs a time sequence signal P2_even; the Q end of the sixth D flip-flop Q24 is connected to one input end of the third two-input and gate Q25, the other input end of the third two-input and gate Q25 is connected, the output end of the third two-input and gate Q25 is connected to the clock end of the seventh D flip-flop Q26, the D end of the seventh D flip-flop Q26 is connected to the Qb end, and the Q end of the seventh D flip-flop Q26 outputs the timing signal p2_odd.
When n=1 to 7, the logic control circuit Q33 includes a sixth not gate Q3301, a third three-input and gate Q3302, a seventh not gate Q3303, a fourth three-input and gate Q3304, a fifth three-input and gate Q3305, and a sixth three-input and gate Q3306, where an input end of the sixth not gate Q3301 is connected to Bit <0>, and three input ends of the third three-input and gate Q3302 are respectively connected to Bit <2>, bit <1>, and an output end of the sixth not gate Q3301; the input end of the seventh NOT gate Q3303 is connected with Bit <1>, and the three input ends of the fourth three input AND gate Q3304 are respectively connected with the output ends of the seventh NOT gate Q3303, bit <2>, bit <0>; the three input ends of the fifth three-input and gate Q3305 are respectively connected with Bit <2>, bit <1>, bit <0>, the three input ends of the sixth three-input and gate Q3306 are respectively connected with the output ends of the third three-input and gate Q3302, the fourth three-input and gate Q3304 and the fifth three-input and gate Q3305, and the sixth three-input and gate Q3306 outputs sel_fre <3> as a control signal for the signal selection circuit.
When n=1 to 7, the signal selection circuit includes a fourth two-input and gate Q27, a fifth two-input and gate Q28, a second gate Q29, an eighth D flip-flop Q30, a sixth two-input and gate Q31, and a 4-select 1 selector Q32, where input ends of the fourth two-input and gate Q27 are respectively connected to P0 and p2_even, input ends of the fifth two-input and gate Q28 are respectively connected to P0 and p2_odd, output ends of the fourth two-input and gate Q27 and the fifth two-input and gate Q28 are respectively connected to two input ends of the second gate Q29, and a control end of the second gate Q29 is connected to Bit <0>; the output end of the second gating device Q29 is connected with the clock end of the eighth D trigger Q30, the D end of the eighth D trigger Q30 is connected with the Qb end, the Q end of the eighth D trigger Q30 is connected with the input end IN3 of the 4-to-1 selector Q32, the two input ends of the sixth two-input AND gate Q31 are respectively connected with P0 and P1, the output end of the sixth two-input AND gate Q31 is connected with the input end IN2 of the 4-to-1 selector Q32, the input end IN1 of the 4-to-1 selector Q32 is connected with P0, the input end IN0 of the 4-to-1 selector Q32 is connected with the clock signal CK, and the control end of the 4-to-1 selector Q32 is connected with the output end of the logic control circuit Q33.
After the scheme is adopted, in the process of increasing and counting by the adder and decreasing and counting by the subtracter, the output values of the adder and the subtracter are equal in a certain clock period to logically judge so as to obtain a pulse signal, and a target pulse signal P_2 which is different by one clock period or two clock periods is obtained based on the pulse signal, so that the duty ratio of the signal can be ensured to be 50% when the wide-range frequency division ratio is realized.
Drawings
FIG. 1 is a block diagram of a programmable divider of the present invention;
FIG. 2 is a circuit block diagram of an add counter circuit in an embodiment of the invention;
FIG. 3 is a circuit diagram of a down counter circuit in an embodiment of the invention;
FIG. 4 is a circuit block diagram of a subtractor in an embodiment of the present invention;
FIG. 5 is a circuit diagram of a subtraction circuit in an embodiment of the present invention;
fig. 6 is a circuit configuration diagram of the timing generation circuit;
FIG. 7 is a circuit diagram of a logic control circuit in an embodiment of the present invention;
FIG. 8 is a circuit diagram of a signal selection circuit in an embodiment of the invention;
FIG. 9 is a plot of output frequency values and duty cycle as a function of divide ratio;
wherein, (a) is an effect schematic diagram of the existing frequency divider; (b) is an effect diagram of the present case;
FIG. 10 is a timing diagram when N is even;
FIG. 11 is a timing diagram when N is odd;
fig. 12 is a schematic diagram of a design of a 10bit frequency divider based on the frequency division method of the present invention.
Detailed Description
The technical scheme and beneficial effects of the present invention will be described in detail below with reference to the accompanying drawings.
The invention provides a frequency division method for realizing 50% duty ratio, which is used for realizing N frequency division and can be matched with the diagram shown in fig. 11, and comprises the following contents:
the clock signal CK is correspondingly processed according to the frequency division ratio N corresponding to the following different conditions:
in the first case, n=1 (one division)
At this time, the output signal fout=ck, directly outputs the clock signal CK;
in the second case, n=2 (two-frequency division)
Setting an output signal fout=p_0, which is generated from a pulse signal generated when the counter counts (decrements) from N to N-1;
in the third case, n=3 (frequency division by three)
Let out signal fout=or (p_0, p_1), wherein generation of signal p_0 refers to the second case; the signal p_1 is generated in the following manner: counting to N-1 by a counter, and delaying for half a period to generate a pulse signal P_1;
in the fourth case, N is an even number and N is not less than 4 (even number of frequency divisions)
Let out signal fout=or (p_0, p_2_even), wherein generation of signal p_0 can refer to the second case; the signal p_2_even is generated in the following manner: simultaneously performing up-down counting, starting at a certain moment, starting from N to count down, starting from 0 to count up, and delaying a pulse signal obtained by a period to obtain P_2_even when the count reaches N/2 at the same time;
in the fifth case, N is an odd number and N is not less than 5 (frequency division is performed an odd number of times)
Let out signal fout=or (p_1, p_2_odd), wherein generation of signal p_1 can refer to the third case; the signal p_2_odd is generated in the following manner: and simultaneously performing up-down counting, starting at a certain moment, starting from N to count down, starting from 1 to count up, and outputting a pulse signal when the counts of the two sides are the same, wherein the pulse signal obtained by delaying two periods of the pulse signal is P_2_odd.
Referring to fig. 10, when the frequency divider divides the frequency, if the set division ratio N is even (greater than 2), when the counter counts to N-1, a p_0 signal is generated, when the counter counts to (N-2)/2, another pulse signal p_2 is generated, the two pulses are or-gate-logic-processed to obtain a p_n/2 signal, and the p_n/2 signal is further divided into two frequency halves to obtain a frequency output signal with 50% duty ratio. Similarly, in fig. 11, when the set frequency division ratio is odd (greater than 3), the counter counts to N-1 and delays for half a period to generate the p_1 signal, when the counter counts to (N-3)/2, a new pulse signal p_2 signal is generated, the p_1 and p_2 signals are or-gate-logic to obtain the p_n/2 signal, and the p_n/2 signal is frequency-divided to obtain the frequency output signal with 50% duty ratio.
It can be seen that the key is how to generate the p_2 signal. The up counter and the down counter can be simultaneously counted, when N is even, the down counter starts to be decremented from N, the up counter starts to be incremented from 0, when the down counter is decremented to N/2, the up counter is also incremented to N/2, at the moment, a logic judgment circuit is used for generating a pulse signal, and the signal is further delayed for one period, namely the P_2 signal at the moment (N/2) -1 in fig. 10. Similarly, when N is odd, the down counter is still decremented from N, and the up counter is incremented from 1. When the up and down counter outputs are equal, a pulse signal is generated that is delayed by two main clock cycles to obtain the p_2 signal of fig. 11. For example, in table 1, when N is 5, the output of the down counter and the output of the up counter are equal over three periods, and one pulse signal p2_pre_odd is generated at this time, but from the timing chart of fig. 11, the p_2 signal is generated when the down counter output (N-3)/2= (5-3)/2=1, and the p_2 signal can be obtained by delaying the signal p2_pre_odd by two periods. Similarly, when N is 4, the output of the down counter and the output of the up counter are equal over three periods, and one pulse signal p2_pre_even is generated at this time, but from the timing chart of fig. 10, the p_2 signal is generated when the down counter outputs (N-2)/2=1, and the p_2 signal can be obtained by delaying the signal p2_pre_even by 1 period.
Table 1 example of the up and down counters generating the p_2 signal
The invention also provides a frequency divider for realizing the duty ratio of 50%, which comprises an up counter circuit, a down counter circuit, a time sequence generating circuit, a clock signal generating circuit, a signal selecting circuit and a logic control circuit, wherein the frequency divider is shown in figure 1;
the frequency division ratio N is expressed as a binary form Bit < N:0> as input signals of the up-counter circuit and the down-counter circuit;
the addition counter circuit performs incremental counting according to An input signal after reset, continuously generates a pulse signal An-A0 in the counting process, and sends the pulse signal An-A0 to the time sequence generating circuit;
the down counter circuit performs down counting according to an input signal after reset, continuously generates pulse signals Sn-S0 and SR in the counting process, and sends the pulse signals Sn-S0 and SR to the time sequence generating circuit;
the time sequence generating circuit is used for generating time sequence signals P0, P1, P2_even and P2_odd according to the pulse signal An-A0 generated by the up counter circuit and the pulse signals Sn-S0 and SR generated by the down counter circuit and is connected to the signal selecting circuit;
the clock signal generation circuit is used for generating a clock signal CK, and the clock signal CK can be obtained by an external clock signal through a plurality of clock buffers; the clock signal CK generated by the clock signal generation circuit is respectively used as the clock signals of the up-counter circuit, the down-counter circuit and the time sequence generation circuit;
the logic control circuit sends control signals to the signal selection circuit according to logic control rules (refer to fig. 11), the signal selection circuit gates signals of corresponding channels to achieve the purpose of frequency division, and signals with 50% duty ratio are output; the signals are all generated at the rising clock edge.
The following is Bit<2:0>For example, the invention provides a specific circuit form for realizing a programmable frequency divider with 50% duty ratio, which is suitable for a frequency division ratio of 1-7 (2 2+1 -1).
As shown in fig. 2, the up-counter circuit performs up-counting and resets when reaching the count value, and outputs a signal A2A1A0 during the counting process; the addition counter circuit comprises an adder Q1, a second logic circuit Q2, an exclusive OR gate Q3, an OR gate Q4, an OR gate Q5 and an NOT gate Q6, wherein the input end of the Q2 is respectively connected with N and N+1, the control end of the Q2 is connected with Bit <0>, the count value of the addition counter circuit is determined according to the parity of the frequency division ratio N, and when N is even, the channel of the N+1 is gated (namely, the channel is increased from 0); when N is odd, the way of N is gated (i.e., incremented from 1); the output end of Q2 is connected with one input end of Q3, the other input end of Q3 is connected with the output end of Q1, the output end of Q3 is respectively connected with one input end of Q4 and one input end of Q5, the other input end of Q4 is connected with Bit <0>, the input end of Q6 is connected with Bit <0>, and the output end of Q6 is connected with the other input end of Q5; the output end of Q4 is connected with the RST end of Q1, the output end of Q5 is connected with the SET end of Q1, the output end of Q1 is also used as the output end of the up-counter circuit, and A2A1A0 is output.
As shown in fig. 3, the down counter circuit performs down counting and resets when reaching a count value, and outputs signals S2S1S0 and SR during counting; the down counter circuit comprises a subtracter Q34 and a three-input exclusive-OR gate Q35, wherein the assigned end of the Q34 is connected with N and used for performing down counting; the output end of the Q34 is connected with the input end of the Q35, and the output end of the Q34 is also used as the output end of the down counter circuit to output S2S1S0; the output terminal of Q35 is connected to the reset terminal of Q34, and the output terminal of Q35 also serves as the output terminal of the down counter circuit, outputting SR.
Fig. 4 shows a specific circuit configuration of the subtractor Q34; since the embodiment is 3 bits, 3 subtracting circuits Q7, Q8, Q9 are provided, corresponding to Bit <0>, bit <1>, bit <2>, respectively, that is, for Bit < n:0>, the number of subtracting circuits provided is n+1; the subtracter further comprises a three-input AND gate Q10, a two-input AND gate Q11, a D trigger Q12 and a NOT gate Q13, wherein the input end of the Q7 is connected with the inverted output end of the Q7 and is commonly connected to the first input end of the Q10; the input end of Q8 is connected with the inverting output end thereof and is commonly connected with the second input end of Q10; the input end of Q9 is connected with the inverting output end thereof and is commonly connected with the third input end of Q10; the output end of Q10 is connected with one input end of Q11, the output end of Q11 is connected with the input end of Q12, the output end of Q12 is connected with the other input end of Q11 and is commonly connected with the input end of Q13, and the output ends of Q13 are respectively connected with the SR ends of Q7, Q8 and Q9 and serve as reset ends of a subtracter Q34; the clock end of the Q7 is connected with the clock signal CK, and the output end of the Q7 is connected with the clock end of the Q8 and serves as an S0 signal output end of the subtracter; the output end of the Q8 is connected with the clock end of the Q9 and is used as an S1 signal output end of the subtracter; the output end of the Q9 is used as an S2 signal output end of the subtracter; the structures of Q7, Q8 and Q9 are the same, and the specific structures can be matched with those shown in FIG. 5, and the structure comprises a transmission gate Q701, a NOT gate Q702, a NOT gate Q703, a transmission gate Q704, a NOT gate Q705, a NOT gate Q706, a NOT gate Q707, a Q708, NOT gates Q709, Q710, a NOT gate Q711 and a NOT gate Q712, wherein one end of the Q701 is used as a D1 end of the Q7/Q8/Q9, and the other end of the Q701 is respectively connected with one input end of the Q703 and one end of the Q704; the input end of the Q702 is taken as the D2 end of the Q7/Q8/Q9, the output end of the Q702 is connected with one input end of the Q706, the other input end of the Q706 is taken as the SR end of the Q7/Q8/Q9 and is connected with one input end of the Q705, and the other input end of the Q705 is connected with the input end of the Q702; the output end of Q706 is respectively connected with the other input end of Q703 and one input end of Q711; the output end of Q705 is connected with one input end of Q707 and one input end of Q709 respectively, the other input end of Q707 is connected with the output end of Q703 and one end of Q708 respectively, and the output end of Q707 is connected with the other end of Q704; the other end of Q708 is connected with the other input end of Q709 and one end of Q710 respectively, the output end of Q709 is connected with the other input end of Q711 and the input end of Q712 respectively, and the end is also used as the Q end of Q7/Q8/Q9; the output end of Q711 is connected with the other end of Q710, and the output end of Q712 is taken as the Qb end of Q7/Q8/Q9.
As shown in fig. 6, the timing generation circuit includes a D flip-flop Q14, a D flip-flop Q15, a not gate Q16, an exclusive or gate Q17, an exclusive or gate Q18, an exclusive or gate Q19, a three-input and gate Q20, a D flip-flop Q21, a two-input and gate Q22, a D flip-flop Q23, a D flip-flop Q24, a two-input and gate Q25, and a D flip-flop Q26, wherein a D terminal of Q14 is connected to an SR signal, and a Q terminal of Q14 outputs a timing signal P0; the clock end of the Q14 is connected with a clock signal CK, the clock signal CK is also connected with the input end of the Q16, the output end of the Q16 is connected with the clock end of the Q15, the D end of the Q15 is connected with the Q end of the Q14, and the Q end of the Q15 outputs a time sequence signal P1; the two input ends of Q17 are respectively connected with signals S2 and A2, the two input ends of Q18 are respectively connected with signals S1 and A1, the two input ends of Q19 are respectively connected with signals S0 and A0, the output end of Q17, the output end of Q18 and the output end of Q19 are respectively connected with three input ends of Q20, the output end of Q20 is connected with the D end of Q21, the Q end of Q21 is respectively connected with one input end of Q22 and the D end of Q24, the other input end of Q22 is connected, the output end of Q22 is connected with the clock end of Q23, the D end of Q23 is connected with the Qb end, and the Q end of Q23 outputs a time sequence signal P2_even; the Q end of the Q24 is connected with one input end of the Q25, the other input end of the Q25 is connected, the output end of the Q25 is connected with the clock end of the Q26, the D end of the Q26 is connected with the Qb end, and the Q end of the Q26 outputs a time sequence signal P2_odd.
As shown in fig. 7, the logic control circuit Q33 includes an not gate Q3301, a three-input and gate Q3302, an not gate Q3303, a three-input and gate Q3304, a three-input and gate Q3305, and a three-input and gate Q3306, wherein an input terminal of Q3301 is connected to Bit <0>, and three input terminals of Q3302 are respectively connected to Bit <2>, bit <1>, and an output terminal of Q3301 (i.e., bit <0 >); the input terminal of Q3303 is connected with Bit <1>, and the three input terminals of Q3304 are respectively connected with Bit <2>, bit <0> and the output terminal of Q3303 (namely, bit <1 >); three input ends of Q3305 are respectively connected with Bit <2>, bit <1>, bit <0>, and three input ends of Q3306 are respectively connected with output ends of Q3302, Q3304 and Q3305, and Q3304, Q3305 and Q3306 respectively output sel_fre <0>, sel_fre <1>, sel_fre <2>, sel_fre <3> as control signals sel_fre <3:0> for the signal selection circuit.
As shown IN fig. 8, the signal selection circuit includes a two-input and gate Q27, a two-input and gate Q28, a gate Q29, a D flip-flop Q30, a two-input and gate Q31, and a 4-select 1 selector Q32, wherein an input terminal of Q27 is connected to P0 and p2_even, an input terminal of Q28 is connected to P0 and p2_odd, an output terminal of Q27 and Q28 is connected to two input terminals of Q29, a control terminal of Q29 is connected to Bit <0>, an output terminal of Q29 is connected to a clock terminal of Q30, a D terminal of Q30 is connected to a Qb terminal, a Q terminal of Q30 is connected to an input terminal IN3 of Q32, two input terminals of Q31 are connected to P0 and P1, an output terminal of Q31 is connected to an input terminal IN2 of Q32, an input terminal IN1 of Q32 is connected to P0, an input terminal IN0 of Q32 is connected to an output terminal of a logic control circuit Q33, and a corresponding channel is output under control of a control signal, and a duty ratio of the output signal is clk50%.
The effect of the present invention in comparison with the prior frequency divider is shown with reference to fig. 9.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereto, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the present invention.

Claims (10)

1. A frequency dividing method for realizing 50% duty ratio, which is used for realizing N frequency division; the method is characterized in that: the clock signal CK is processed accordingly for the following different cases:
in case one, when realizing one frequency division, outputting a clock signal CK;
in case two, when the divide-by-two is implemented, the output signal fout=p_0, the signal p_0 is generated from the pulse signal generated when the counter counts to N-1;
in case three, when implementing the divide-by-three, the output signal fout=or (p_0, p_1), where the signal p_1 is generated by: counting to N-1 by a counter, and delaying for half a period to generate a pulse signal P_1;
in case four, when the frequency division is performed an even number of times and N is equal to OR greater than 4, the output signal fout=or (p_0, p_2_even), wherein the signal p_2_even is generated in the following manner: starting at a certain moment, starting to count down by N, starting to count up by 0, and outputting a pulse signal when the count reaches N/2 at the same time, wherein the pulse signal obtained by delaying one period of the pulse signal is P_2_even;
in case five, when the frequency division is performed for an odd number of times and N is equal to OR greater than 5, the output signal fout=or (p_1, p_2_odd) is generated by: starting at a certain moment, starting from N to count down, starting from 1 to count up, and outputting a pulse signal when the counts of the two sides are the same, wherein the pulse signal obtained by delaying the pulse signal by two periods is P_2_odd.
2. A frequency divider realizing a duty cycle of 50% for realizing frequency division by N; the method is characterized in that: the binary form of N is expressed as Bit < N:0>; the frequency divider comprises an up counter circuit, a down counter circuit, a time sequence generating circuit, a clock signal generating circuit, a signal selecting circuit and a logic control circuit;
the addition counter circuit is reset and then performs incremental counting, generates a pulse signal An-A0 in the counting process, and sends the pulse signal An-A0 to the time sequence generating circuit;
the down counter circuit is reset and then performs down counting, generates pulse signals Sn-S0 and SR in the counting process, and sends the pulse signals Sn-S0 and SR to the time sequence generating circuit;
the time sequence generating circuit is used for generating time sequence signals P0, P1, P2_even and P2_odd according to the pulse signal An-A0 generated by the up counter circuit and the pulse signals Sn-S0 and SR generated by the down counter circuit and is connected to the signal selecting circuit;
the clock signal generating circuit is used for generating clock signals which are respectively used as clock signals of the up counter circuit, the down counter circuit and the time sequence generating circuit;
the logic control circuit sends control signals to the signal selection circuit, and the signal selection circuit gates signals of corresponding channels, so that the duty ratio of the clock signals is 50% at different frequency division ratios.
3. The frequency divider implementing a duty cycle of 50% as recited in claim 2, wherein: the signals are all generated at the rising clock edge.
4. The frequency divider implementing a duty cycle of 50% as recited in claim 2, wherein: when n=1 to 7, the addition counter circuit includes an adder (Q1), a first gating device (Q2), a first exclusive or gate (Q3), a first or gate (Q4), a second or gate (Q5) and a first not gate (Q6), wherein the input end of the first gating device (Q2) is connected to N and n+1 respectively, and the control end thereof is connected to Bit <0>; the output end of the first gating device (Q2) is connected with one input end of a first exclusive OR gate (Q3), the other input end of the first exclusive OR gate (Q3) is connected with the output end of an adder (Q1), the output end of the first exclusive OR gate (Q3) is respectively connected with one input end of a first OR gate (Q4) and one input end of a second OR gate (Q5), the other input end of the first OR gate (Q4) is connected with Bit <0>, the input end of the first NOT gate (Q6) is connected with Bit <0>, and the output end of the first NOT gate (Q6) is connected with the other input end of the second OR gate (Q5); the output end of the first OR gate (Q4) is connected with the RST end of the adder (Q1), the output end of the second OR gate (Q5) is connected with the SET end of the adder (Q1), and the output end of the adder (Q1) is also used as the output end of the addition counter circuit.
5. The frequency divider implementing a duty cycle of 50% as recited in claim 2, wherein: when n=1 to 7, the down counter circuit includes a subtractor (Q34) and a three-input exclusive-or gate (Q35), where an assigned end of the subtractor (Q34) is connected to N, an output end of the subtractor (Q34) is connected to an input end of the three-input exclusive-or gate (Q35), and an output end of the subtractor (Q34) is further used as an output end of the down counter circuit to output S2S1S0; the output end of the three-input exclusive-OR gate (Q35) is connected to the reset end of the subtracter (Q34), and the output end of the three-input exclusive-OR gate (Q35) is also used as the output end of the down counter circuit to output SR.
6. The frequency divider implementing a duty cycle of 50% as recited in claim 5, wherein: the subtracter (Q34) comprises a first subtracting circuit (Q7), a second subtracting circuit (Q8), a third subtracting circuit (Q9), a first three-input AND gate (Q10), a first two-input AND gate (Q11), a first D trigger (Q12) and a second NOT gate (Q13), wherein the input end of the first subtracting circuit (Q7) is connected with the inverting output end of the first subtracting circuit and is commonly connected to the first input end of the first three-input AND gate (Q10); the input end of the second subtracting circuit (Q8) is connected with the inverting output end of the second subtracting circuit and is commonly connected to the second input end of the first three-input AND gate (Q10); the input end of the third subtracting circuit (Q9) is connected with the inverting output end of the third subtracting circuit and is commonly connected to the third input end of the first three-input AND gate (Q10); the output end of the first three-input AND gate (Q10) is connected with one input end of a first two-input AND gate (Q11), the output end of the first two-input AND gate Q11 is connected with the input end of a first D trigger (Q12), the output end of the first D trigger (Q12) is connected with the other input end of the first two-input AND gate (Q11) and is commonly connected with the input end of a second NOT gate (Q13), and the output end of the second NOT gate (Q13) is respectively connected with the SR ends of a first subtracting circuit (Q7), a second subtracting circuit (Q8) and a third subtracting circuit (Q9) and is used as the SR signal output end of a subtracting counter circuit; the clock end of the first subtracting circuit (Q7) is connected with the clock signal CK, and the output end of the first subtracting circuit (Q7) is connected with the clock end of the second subtracting circuit (Q8) and is used as the S0 signal output end of the subtracting counter circuit; the output end of the second subtracting circuit (Q8) is connected with the clock end of the third subtracting circuit (Q9) and is used as the S1 signal output end of the subtracting counter circuit; the output of the third subtracting circuit (Q9) serves as the S2 signal output of the subtracting circuit.
7. The frequency divider implementing a duty cycle of 50% as recited in claim 6, wherein: the first subtracting circuit (Q7), the second subtracting circuit (Q8) and the third subtracting circuit (Q9) have the same structure, and each include a first transmission gate (Q701), a fourth not gate (Q702), a first nand gate (Q703), a second transmission gate (Q704), a second nand gate (Q705), a third nand gate (Q706), a fourth nand gate (Q707), a third transmission gate (Q708), a fifth nand gate (Q709), a fourth transmission gate (Q710), a sixth nand gate (Q711) and a fifth not gate (Q712), wherein one end of the first transmission gate (Q701) is used as a D1 end of the first/second/third subtracting circuit (Q7/Q8/Q9), and the other end of the first transmission gate is connected to one input end of the first nand gate (Q703) and one end of the second transmission gate (Q704), respectively; the input end of the fourth NAND gate (Q702) is used as the D2 end of the first/second/third subtracting circuit (Q7/Q8/Q9), the output end of the fourth NAND gate is connected with one input end of the third NAND gate (Q706), and the other input end of the third NAND gate (Q706) is used as the SR end of the first/second/third subtracting circuit (Q7/Q8/Q9) and is connected with one input end of the second NAND gate (Q705); the output end of the third NAND gate (Q706) is respectively connected with the other input end of the first NAND gate (Q703) and one input end of the sixth NAND gate (Q711); the output end of the second NAND gate (Q705) is respectively connected with one input end of the fourth NAND gate (Q707) and one input end of the fifth NAND gate (Q709), the other input end of the fourth NAND gate (Q707) is respectively connected with the output end of the first NAND gate (Q703) and one end of the third transmission gate (Q708), and the output end of the fourth NAND gate (Q707) is connected with the other end of the second transmission gate (Q704); the other end of the third transmission gate (Q708) is respectively connected with the other input end of the fifth NAND gate (Q709) and one end of the fourth transmission gate (Q710), the output end of the fifth NAND gate (Q709) is respectively connected with the other input end of the sixth NAND gate (Q711) and the input end of the fifth NAND gate (Q712), and the ends are also used as the Q ends of the first/second/third subtraction circuit (Q7/Q8/Q9); the output end of the sixth NAND gate (Q711) is connected with the other end of the fourth transmission gate (Q710), and the output end of the fifth NAND gate (Q712) is used as the Qb end of the first/second/third subtracting block (Q7/Q8/Q9).
8. The frequency divider implementing a duty cycle of 50% as recited in claim 2, wherein: when n=1 to 7, the timing sequence generating circuit includes a second D flip-flop (Q14), a third D flip-flop (Q15), a third not gate (Q16), a second exclusive-nor gate (Q17), a third exclusive-nor gate (Q18), a fourth exclusive-nor gate (Q19), a second third input and gate (Q20), a fourth D flip-flop (Q21), a second two input and gate (Q22), a fifth D flip-flop (Q23), a sixth D flip-flop (Q24), a third two input and gate (Q25) and a seventh D flip-flop (Q26), wherein a D end of the second D flip-flop (Q14) is connected to an SR signal, and a Q end of the second D flip-flop (Q14) outputs a timing sequence signal P0; the clock end of the second D trigger (Q14) is connected with a clock signal CK, the clock signal CK is also connected with the input end of a third NOT gate (Q16), the output end of the third NOT gate (Q16) is connected with the clock end of a third D trigger (Q15), the D end of the third D trigger (Q15) is connected with the Q end of the second D trigger (Q14), and the Q end of the third D trigger (Q15) outputs a time sequence signal P1; two input ends of the second exclusive-or gate (Q17) are respectively connected with signals S2 and A2, two input ends of the third exclusive-or gate (Q18) are respectively connected with signals S1 and A1, two input ends of the fourth exclusive-or gate (Q19) are respectively connected with signals S0 and A0, the output end of the second exclusive-or gate (Q17), the output end of the third exclusive-or gate (Q18) and the output end of the fourth exclusive-or gate (Q19) are respectively connected with three input ends of the second three-input exclusive-or gate (Q20), the output end of the second three-input exclusive-or gate (Q20) is connected with the D end of the fourth D flip-flop (Q21), the Q end of the fourth D flip-flop (Q21) is respectively connected with one input end of the second exclusive-or gate (Q22) and the D end of the sixth D flip-flop (Q24), the other input end of the second exclusive-or gate (Q22) is connected, the output end of the second exclusive-or gate (Q22) is connected with the three input ends of the second three-input exclusive-or gate (Q20), and the output end of the fifth D flip-flop (Q23) is connected with the fifth clock signal (Q_2); the Q end of the sixth D trigger (Q24) is connected with one input end of a third two-input AND gate (Q25), the other input end of the third two-input AND gate (Q25) is connected, the output end of the third two-input AND gate (Q25) is connected with the clock end of the seventh D trigger (Q26), the D end of the seventh D trigger (Q26) is connected with the Qb end, and the Q end of the seventh D trigger (Q26) outputs a time sequence signal P2_odd.
9. The frequency divider implementing a duty cycle of 50% as recited in claim 2, wherein: when n=1 to 7, the logic control circuit (Q33) includes a sixth not gate (Q3301), a third three-input and gate (Q3302), a seventh not gate (Q3303), a fourth three-input and gate (Q3304), a fifth three-input and gate (Q3305) and a sixth three-input and gate (Q3306), wherein an input end of the sixth not gate (Q3301) is connected to Bit <0>, and three input ends of the third three-input and gate (Q3302) are respectively connected to Bit <2>, bit <1>, and an output end of the sixth not gate (Q3301); the input end of the seventh NOT gate (Q3303) is connected with Bit <1>, and the three input ends of the fourth three-input AND gate (Q3304) are respectively connected with Bit <2>, bit <0> and the output end of the seventh NOT gate (Q3303); three input ends of the fifth three-input AND gate (Q3305) are respectively connected with Bit <2>, bit <1>, bit <0>, three input ends of the sixth three-input AND gate (Q3306) are respectively connected with output ends of the third three-input AND gate (Q3302), the fourth three-input AND gate (Q3304) and the fifth three-input AND gate (Q3305), and the sixth three-input AND gate (Q3306) outputs sel_fre <3> as a control signal for the signal selection circuit.
10. The frequency divider implementing a duty cycle of 50% as recited in claim 2, wherein: when n=1 to 7, the signal selection circuit includes a fourth two-input and gate (Q27), a fifth two-input and gate (Q28), a second gate (Q29), an eighth D flip-flop (Q30), a sixth two-input and gate (Q31), and a 4-select 1 selector (Q32), wherein the input end of the fourth two-input and gate (Q27) is respectively connected to P0 and p2_even, the input end of the fifth two-input and gate (Q28) is respectively connected to P0 and p2_odd, the output ends of the fourth two-input and gate (Q27) and the fifth two-input and gate (Q28) are respectively connected to two input ends of the second gate (Q29), and the control end of the second gate (Q29) is connected to Bit <0>; the output end of the second gating device (Q29) is connected with the clock end of the eighth D trigger (Q30), the D end of the eighth D trigger (Q30) is connected with the Qb end, the Q end of the eighth D trigger (Q30) is connected with the input end IN3 of the 4-to-1 selector (Q32), the two input ends of the sixth two-input AND gate (Q31) are respectively connected with P0 and P1, the output end of the sixth two-input AND gate (Q31) is connected with the input end IN2 of the 4-to-1 selector (Q32), the input end IN1 of the 4-to-1 selector (Q32) is connected with P0, the input end IN0 of the 4-to-1 selector (Q32) is connected with the clock signal CK, and the control end of the 4-to-1 selector (Q32) is connected with the output end of the logic control circuit (Q33).
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