JP2011151672A - Frequency division device and control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To frequency-divide an input pulse train changing a period, and to suppress the jitter of the frequency-divided pulse train as much as possible. <P>SOLUTION: A frequency division device 1 takes a positive integer having mutually different first variable and second variable, and can frequency-divide input pulses at a division ratio representing a ratio of a second variable ratio to the first variable. The division device 1 includes a counter circuit (12) counting a reference clock having a constant frequency for a period of input pulses, and arithmetic output circuits (13 and 14) conducting arithmetic operations dividing a first count value obtained by the counter circuit into values indicated by the first variable while starting the count of the reference clock and outputting one pulse every time a second count value by the count reaches any divided value of the first count value. The division device 1 further includes a frequency dividing circuit (15) outputting pulses obtained by obtained by frequency-dividing an output pulse train of an arithmetic output circuit by a value indicated by the second variable. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a frequency divider that divides an input pulse train. Furthermore, the present invention relates to a control circuit equipped with the frequency dividing device.

  A general frequency dividing device configured by hardware uses, for example, an n-ary counter when dividing an input pulse by n (for example, Patent Documents 1 and 2).

JP 2005-64995 A JP 2006-230017 A

According to the frequency dividing device disclosed in Patent Documents 1 and 2, when the period of the input pulse train is constant, the jitter of the pulse train after frequency division can be suppressed.
However, for example, when the rotation speed is controlled with an irregular cycle like a servo motor, the cycle of the input pulse train to be divided also varies irregularly.

  Therefore, in the frequency dividing devices disclosed in Patent Documents 1 and 2, if the period of the input pulse train changes irregularly, it is difficult for the synchronous counter to output pulses in accordance with the period.

  Therefore, there is a demand for a frequency dividing device that can divide the input pulse train whose period changes and suppress the jitter of the divided pulse train as much as possible. Furthermore, it is desired to control a controlled object with high accuracy using a control circuit equipped with such a frequency dividing device.

An object of the present invention is to provide a frequency dividing device that can divide an input pulse train whose period changes and suppress jitter of the divided pulse train as much as possible.
Furthermore, the present invention is to accurately control a control target using a control circuit equipped with such a frequency dividing device.

  In the frequency dividing device according to the present invention, the first variable and the second variable take different positive integers, and the input pulse can be divided by a frequency dividing ratio represented by the ratio of the second variable to the first variable. A counter circuit for counting a reference clock having a constant frequency over the period of the input pulse, and an operation for dividing a first count value obtained by the counter circuit into a value indicated by the first variable An arithmetic output circuit that starts counting the reference clock and outputs one pulse each time a second count value based on the count reaches a value obtained by dividing the first count value; and the arithmetic output circuit And a frequency dividing circuit for outputting a pulse obtained by dividing the output pulse train by a value indicated by the second variable.

  In the control circuit of the present invention, the first variable and the second variable take different positive integers, and the frequency division that can divide the input pulse by the division ratio represented by the ratio of the second variable to the first variable is possible. A control circuit using an output of the frequency divider, wherein the frequency divider includes a counter circuit that counts a reference clock having a constant frequency over the period of the input pulse, and the counter circuit. An operation is performed to divide the obtained first count value into a value indicated by the first variable, and the counting of the reference clock is started, and the second count value by the count becomes a value obtained by dividing the first count value. An arithmetic output circuit that outputs one pulse each time it reaches, and a frequency dividing circuit that outputs a pulse obtained by dividing the output pulse train of the arithmetic output circuit by a value indicated by the second variable.

ADVANTAGE OF THE INVENTION According to this invention, the frequency dividing apparatus which can divide the input pulse train from which a period changes, and can suppress the jitter of the divided pulse train as much as possible can be provided.
Furthermore, according to the present invention, a control object can be controlled with high accuracy using a control circuit equipped with such a frequency dividing device.

FIG. 1 is a block diagram illustrating a configuration example of a frequency divider according to the first embodiment of the present invention. 2A to 2E are timing charts for explaining the outline of the operation of the frequency divider according to the first embodiment of the present invention. FIG. 3 is a flowchart showing an operation example of the arithmetic circuit according to the first embodiment of the present invention. 4A to 4D are timing charts showing an operation example of the frequency divider 1 according to the first embodiment of the present invention. FIGS. 5A to 5D are timing charts showing an operation example of the frequency divider according to the first embodiment of the present invention. FIG. 6 is a block diagram illustrating a configuration example of the frequency dividing device A configured by general software. FIG. 7 is a diagram for explaining the calculation result of the separation calculation unit A8 illustrated in FIG. FIG. 8 is a block diagram illustrating a configuration example of a control system of the servo motor according to the second embodiment. FIG. 9 is a block diagram illustrating a configuration example of a frequency dividing device according to a modified example of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram illustrating a configuration example of a frequency divider according to the first embodiment of the present invention.
A frequency dividing device 1 illustrated in FIG. 1 includes a reference clock generation circuit 11, a pulse period measurement circuit 12, an arithmetic circuit 13, a pulse output circuit 14, a frequency dividing circuit 15, a first instruction circuit 16, and a second instruction circuit 17. Have

Here, the correspondence between the components of the present embodiment and the components of the present invention will be described.
The counter circuit and the measurement circuit according to the present invention correspond to the pulse period measurement circuit 12.
The arithmetic output circuit according to the present invention corresponds to the arithmetic circuit 13 and the pulse output circuit 14.
The clock generation circuit according to the present invention corresponds to the reference clock generation circuit 11.
The first variable according to the present invention corresponds to the variable n. The second variable according to the present invention corresponds to the variable m.
The first count value according to the present invention corresponds to the count value CNT. The second count value according to the present invention corresponds to the count value DCNT. The third count value according to the present invention corresponds to the count value of the frequency dividing circuit 15.

The frequency dividing device 1 has a function of dividing the input pulse train CLK by a frequency dividing ratio R = m / n.
Note that the variable m and the variable n are different positive integers. Dividing the pulse train at a division ratio R = m / n is also simply referred to as “m / n division”. Dividing the pulse train by the variables m and n is also simply referred to as “m division, n division”.

  In the present embodiment, the frequency dividing device 1 is configured by hardware using a subtractor, a divider, a counter, a flip-flop, and the like, and the function of each component is, for example, HDL (Hardware Description Language; hardware description) Language).

First, an outline of the operation of the frequency dividing device 1 will be described with reference to FIGS.
2A to 2E are timing charts for explaining the outline of the operation of the frequency divider according to the first embodiment of the present invention. 2A to 2E show an input pulse (sequence) CLK of one period T, a reference clock BCLK, a count value DCNT (down count), a pulse sequence CLK (1 / n), and a pulse sequence CLK (m / n). Are shown respectively.
Note that the input pulse CLK illustrated in FIG. 2A has a duty ratio of 50%. A pulse train CLK (1 / n) illustrated in FIG. 2D is obtained by dividing the input pulse CLK by n. The pulse train CLK (m / n) illustrated in FIG. 2E is obtained by further dividing the pulse train CLK (1 / n) divided by n by m.
Actually, the pulse train CLK (1 / n) and the pulse train CLK (m / n) are obtained by time division. However, for the sake of clarity, the respective pulse trains are illustrated in the same time series in each figure. ing.

  Hereinafter, the case where the frequency dividing device 1 divides the pulse CLK for one cycle by the frequency dividing ratio R = m / n = 16/3 will be described as an example. As an example, it is assumed that the frequency F1 of the input pulse train CLK is F1 = 1 MHz, and 100 pulses CLK are input to the frequency divider 1 per 100 μs.

Basically, when the pulse CLK is divided by m / n, the pulse CLK may be divided by n and further divided by m.
However, for example, when the frequency division ratio R is a decimal number such as R = 16 / 3≈5.33..., Compared with the case where the frequency division ratio R is R = 3/2 = 1.5. Jitter is likely to occur in the pulse train after frequency division.
Therefore, the frequency dividing device 1 divides the input pulse CLK by 16/3 as follows.

(1) Dividing the input pulse CLK by n First, the frequency divider 1 divides the input pulse CLK shown in FIG. 2A by n = 3, and the pulse train CLK (1 shown in FIG. / N) will be described.

The frequency dividing device 1 counts the number of reference clocks BCLK having a frequency F2 higher than the frequency F1 of the input pulse train CLK over one period T of the input pulse train CLK.
It is assumed that the reference clock BCLK shown in FIG. 2B is generated by the frequency divider 1 and that the frequency F2 is, for example, F2 = 80 MHz. Since it is assumed that 100 pulse trains CLK are input to the frequency divider 1 per 100 μs, 80 (= k) reference clocks BCLK are generated per period T according to the following equation (1). Will exist. In this case, the count value CNT when the reference clock BCLK is counted is CNT = 80.

(Equation 1)
CNT = (1 / 1MHz) / (1 / 80MHz)
= (100 μs / 100 (pieces)) / (1/80 MHz)
= 80 (pieces) (1)

Next, the frequency dividing device 1 divides the input pulse CLK by 3 using the reference clock BCLK. At that time, the frequency dividing device 1 divides the count value CNT = 80 by the frequency dividing ratio R = n = 3. This means that k = 80 reference clocks BCLK are divided into three.
When the count value CNT = 80 is divided by the frequency division ratio R = n = 3, the division result is 80/3 = 26.6. This division is performed by using, for example, a counter, but this cannot obtain the decimal part “0.6...” But can obtain only the integer part “26”.
Therefore, if k = 80 reference clocks BCLK are simply divided into n = 3, they are divided into 26 × 3, leaving two reference clocks BCLK. Due to the remainder, jitter occurs in the divided pulse.

Therefore, the frequency dividing device 1 divides k = 80 reference clocks BCLK into three, k1 = 26, k2 = 27, and k3 = 27, so as to eliminate the remainder.
Specifically, the frequency dividing device 1 divides the count value CNT = 80 by the frequency dividing ratio R = n = 3 to obtain a division result 26.6. Then, the frequency dividing device 1 subtracts the value “26” of the integer part of the division result from the count value CNT = 80 to obtain 80−26 = 54. This subtraction result indicates the number of remaining reference clocks BCLK.

  Next, the frequency dividing device 1 divides the previous subtraction result by the remaining number 2 to be divided to obtain 54/2 = 27. That is, 54 reference clocks BCLK are divided into 27 reference clocks BCLK.

By the way, when the frequency dividing device 1 obtains the count value CNT = 80, as shown in FIG. 2C, the frequency dividing device 1 counts down that value as an initial value for starting counting.
First, when the count value DCNT indicating the down-count value reaches 80−26 = 54 (= D ₁ ), the frequency divider 1 generates a pulse having a cycle T1 as illustrated in FIG. Is output. The count value DCNT = 54 means that k1 = 26 reference clocks BCLK have been counted.
Next, when the count value DCNT reaches DCNT = 54−27 = 27 (= D ₂ ), the frequency divider 1 outputs a pulse having a period T2 as illustrated in FIG. . This count value DCNT = 27 means that k2 = 27 reference clocks BCLK have been counted.
Finally, when the count value DCNT reaches DCNT = 27−27 = 0 (= D ₃ ), the frequency divider 1 has a period T3 (= T2) as illustrated in FIG. Output a pulse. The count value DCNT = 0 means that k3 = 27 reference clocks BCLK have been counted.

In this way, when the count value DCNT reaches D ₁ = 54, D ₂ = 27, and D ₃ = 0, the frequency divider 1 outputs a pulse, whereby n shown in FIG. = A pulse train CLK (1 / n) divided by 3 can be generated.
The period T1 illustrated in FIG. 2D is obtained as T / CNT × K1 = 100 μs / 80 × 26 = 325 ns using the period T of the input pulse, the count value CNT, and the number K1 of the reference clocks BCLK. By the same calculation, the periods T2 and T3 are found to be 337.5 ns using the period T of the input pulse, the count value CNT, and the numbers K2 and K3 of the reference clock BCLK, respectively.

(2) m-division of the pulse train CLK (1 / n) After the generation of the pulse train CLK (1 / n), the frequency divider 1 divides the pulse train CLK (1 / n) by m = 16, so that FIG. A pulse train CLK (m / n) divided by a frequency division ratio R = m / n is generated as shown in FIG.

Incidentally, since the frequency dividing device 1 has divided the k = 80 reference clocks BCLK into the number k1 = 26, k2 = 27, and k3 = 27, the duty ratio of the generated pulse train CLK (1 / n) is 50. %Not necessarily.
In the pulse train CLK (1 / n) illustrated in FIG. 2D, a pulse having a period T1 has a duty ratio of 50%, but a pulse having periods T2 and T3 does not have a duty ratio of 50%.
This is because a pulse having a period T1 is generated using K1 = 26 reference clocks BCLK, and therefore, it can be divided equally into 13 reference clocks BCLK and 13 reference clocks BCLK. This is because it can. For this reason, the on (H level) / off (L level) period is equal to each other.

  However, since the pulses having the periods T2 and T3 are generated using K2 = k3 = 27 reference clocks BCLK, they cannot be equally divided, and the on / off periods are different from each other.

As described above, the frequency dividing device 1 divides the input pulse train CLK by n = 3 while adjusting the duty ratio. However, since it is only necessary to suppress the generation of jitter as much as possible, the periods T1, T2, and T3 are respectively set. The duty ratio of the pulse train CLK (1 / n) is not necessarily 50%.
For example, in order to further reduce the duty ratio of the pulse train CLK (1 / n) having the periods T2 and T3, 12 reference clocks BCLK in the ON period and 15 reference clocks in the OFF period are set for those pulses. It is also possible to assign the clock BCLK. For example, k = 80 reference clocks BCLK can be divided into three, such as k1 = 25, k2 = 26, k3 = 29.

  However, if the duty ratio of the input pulse train CLK is 50%, k = 80 reference clocks BCLK are equally divided into three as possible, such as k1 = 27, k2 = 27, k3 = 26, and the period T1 , T2, and T3, it is desirable to set the duty ratio of the pulse train CLK (1 / n) to 50% as much as possible.

  The case where the frequency division ratio R is R = 16/3 has been described as an example. For example, when the frequency division ratio R is R = 3/2, the frequency dividing device 1 sets the input pulse train CLK to n = 2. The frequency may be divided and further divided by m = 3. When the input pulse train CLK is divided by n = 2, the division result is 2 when the count value CNT = 80 is divided by n = 2. As described above, when no remainder is generated, the frequency dividing device 1 simply divides the input pulse train CLK by n = 2 and further divides it by m = 3.

  Hereinafter, each component of the frequency divider 1 will be described with reference to FIGS. 1 and 2.

  The reference clock generation circuit 11 is configured by, for example, a crystal oscillator or a PLL circuit (phase synchronization circuit). The reference clock generation circuit 11 generates a reference clock BCLK having a constant frequency F2, and outputs this to the pulse period measurement circuit 12.

  As described above, the frequency F2 is constant and is sufficiently higher than the frequency F1 of the input pulse (sequence) CLK (F2 >> F1). This is because when the frequency F2 is smaller than the frequency F1, the input pulse CLK cannot be divided by n = 3. Note that as the frequency F2 is higher than the frequency F1, the occurrence of jitter is suppressed and the accuracy of frequency division is improved.

  In the present embodiment, the frequency F1 of the input pulse (sequence) CLK changes irregularly, but slowly changes within a range where frequency F2 >> frequency F1.

The pulse period measuring circuit 12 is constituted by, for example, a counter or a flip-flop. The pulse period measuring circuit 12 measures one period T of the input pulse train CLK having the frequency F1. At the time of measurement, the pulse period measurement circuit 12 measures a period from the rising edge (edge) of the pulse CLK to the next rising edge (edge) as shown in FIG.
Along with the measurement, the pulse period measurement circuit 12 counts how many reference clocks BCLK are in one period T, and outputs the count value CNT to the arithmetic circuit 13.
The operation of the pulse period measurement circuit 12 is also simply referred to as “clock period measurement”. When measuring one period T of the input pulse train CLK, it is also possible to measure a period from the fall to the next fall.

  The arithmetic circuit 13 is constituted by, for example, a counter or a flip-flop. When the variable n is input from the first instruction circuit 16 and the count value CNT is input from the pulse period measurement circuit 12, the arithmetic circuit 13 operates as follows to divide the input pulse train CLK by n. The operation of the arithmetic circuit 13 is also simply referred to as “CNT / n calculation”.

FIG. 3 is a flowchart showing an operation example of the arithmetic circuit according to the first embodiment of the present invention.
As shown in FIG. 3, the arithmetic circuit 13 divides the count value CNT by the variable n, division results obtain _{D 1} (ST1). Under the above assumption, the division result D ₁ is D ₁ = CNT / n = 26.6. Furthermore, the arithmetic circuit 13, the value "26" of the integer part of the division result D ₁ also obtain.

Then, if there is a remainder in division result _{D 1} (ST2: YES), the arithmetic circuit 13, the subtraction result _{S i-1} of the previous (i-1), this (i) acquired division integer result _{D i} The value of the part is subtracted to obtain the subtraction result S _i (ST3).
Here, the variable i is i = 1, 2,..., N−2. Under the above assumption, the maximum value of the variable i is i = 1. The symbol “int [D _i ]” indicates the value of the integer part of the division result D _i . However, the subtraction result S ₀ as an initial value is assumed to be S ₀ = count value CNT = 80.
For example, when i = 1, since the subtraction result S ₀ = count value CNT, the subtraction result S ₁ is S ₁ = CNT−int [D ₁ ] = 80−26 = 54. Subtraction result _{S 1} is, CNT (= k) = 80 pieces of the reference clock BCLK, which indicates the number of remaining reference clock BCLK.

Then, the arithmetic circuit 13 divides the previously obtained subtraction result S _i by a value (n−i) obtained by subtracting the variable i from the variable n (ST4).
For example, when the variable i = 1, the division result D ₂ is D ₂ = S ₁ / (n−i) = 54 / (3-1) = 27.

When the variable i has not reached n = 1 (ST5: NO), the arithmetic circuit 13 adds “1” to the variable i (ST6), and performs the calculation of step ST4 following the calculation of step ST3.
In this case, the arithmetic circuit 13 obtains the subtraction result S ₂ = S ₁ −int [D ₂ ] = 54−int [27 ”= 27, and then the division result D ₂ = S ₂ / (3-2) = 27. / 1 = 27 is obtained.

After performing the operation of step ST1, the division results D _{1 to} D _n can be obtained by performing the operations of steps ST 3 and 4 recursively.
As shown in FIG. 2 (B), the integer portion of the division result _{D 1} corresponds to the number k1, division results _{D 2} corresponds to the number k2, the division result _{D 3} is equivalent to the number k3. That is, it is possible to obtain the number of reference clocks BCLK when k reference clocks BCLK are divided by the division ratio R = n.

For example, when the frequency division ratio R = m / n = 16/7, the variable n = 7, and the count value CNT = 80, seven division results D _{1 to} D ₇ can be obtained. In this case, the division results D _{1 to} D ₇ are D ₁ = 11, D ₂ = 11, D ₃ = 11, D ₄ = 11, D ₅ = 12, D ₆ = 12, and D ₇ = 12, respectively. .

On the other hand, when the variable i reaches n = 1 (ST5: YES), since all the division results are obtained, the arithmetic circuit 13 collects these division results D _{1 to} D _n to the pulse output circuit 14. Output (ST7). At this time, the arithmetic circuit 13 also outputs the count value CNT obtained by the pulse period measuring circuit 12 to the pulse output circuit 14.

The pulse output circuit 14 illustrated in FIG. 1 is configured by, for example, a down counter. When the division results D _{1 to} D _n are input from the arithmetic circuit 13, the pulse output circuit 14 counts down the reference clock BCLK using the count value CNT as the initial count value as shown in FIG. To start. Since the pulse output circuit 14 counts down the reference clock BCLK, the counting speed is, for example, the frequency F2 of the reference clock generation circuit 11.
The operation of the pulse output circuit 14 is also simply referred to as “n-divided pulse output”.

Specifically, when the count value CNT = 80, the pulse output circuit 14 starts counting down the reference clock BCLK with the count value CNT = 80 as the initial count. Thereafter, when the count value DCNT indicating the value of the down count reaches DCNT = CNT−D ₁ = 80−26 = 54, the pulse output circuit 14 has a cycle T1 illustrated in FIG. A number of pulses are generated and output to the frequency dividing circuit 15.

The pulse output circuit 14 further continues down-counting, and when the count value DCNT reaches DCNT = D ₁ −D ₂ = 54−27 = 27, the pulse having the cycle T 2 shown in FIG. Is output to the frequency divider circuit 15. Subsequently, when the count value DCNT reaches DCNT = D ₂ −D ₃ = 27−27 = 0, the pulse output circuit 14 generates a pulse having a period T3 illustrated in FIG. This is output to the frequency dividing circuit 15.

By using the pulse output circuit 14, a pulse train CLK (1 / n) obtained by dividing the input pulse train CLK by n = 3 can be generated (generated).
When the pulse output circuit 14 performs up-counting and the count value DCNT reaches D ₁ = 26, D ₁ + D ₂ = 53, and D ₁ + D ₂ + D ₃ = 80, the periods T1, T2, and T3 are set. You may output the pulse which each has.

The frequency dividing circuit 15 is constituted by a counter, for example. When the pulse train CLK (1 / n) frequency-divided by n = 3 is input from the pulse output circuit 14, the frequency divider circuit 15 divides this by m = 16. Therefore, the frequency dividing circuit 15 counts the pulse train CLK (1 / n), and outputs a pulse when the count value reaches m = 16. After the pulse is output, the frequency dividing circuit 15 resets the count value to zero.
The frequency dividing circuit 15 generates a pulse train (m / n) divided by a frequency dividing ratio R = m / n, as shown in FIG. The operation of the frequency dividing circuit 15 is also simply referred to as “m frequency division”.

The first instruction circuit 16 gives the variable n to the arithmetic circuit 13 every cycle T of the input pulse train CLK.
The second instruction circuit 17 gives the variable m to the arithmetic circuit 13 every cycle T of the input pulse train CLK.

The operation of the frequency dividing device 1 having the above components will be described with reference to FIGS.
4A to 4D are timing charts showing an operation example of the frequency divider 1 according to the first embodiment of the present invention. FIG. 4A shows the input pulse train CLK. FIG. 4B shows pulse period measurement, CNT / n calculation, n-divided pulse output, and m-divided, respectively. 4C and 4D respectively show the pulse train CLK (1 / n) and the pulse train CLK (m / n).

  When the pulse train CLK illustrated in FIG. 4A is input, the frequency dividing device 1 performs pulse period measurement, CNT / n calculation, and n-divided pulse output illustrated in FIG. 4B in a time-sharing manner. Thus, a pulse train CLK (m / n) divided by n / m as shown in FIG.

Specifically, when the pulse train CLK is input, the pulse period measurement circuit 12 measures the period T from the rising edge (edge) of the pulse CLK at time t1 to the rising edge of the pulse CLK at time t3.
Incidentally, the reference clock generation circuit 11 generates the reference clock BCLK from time t1 or earlier. The pulse period measuring circuit 12 counts the number of reference clocks BCLK in one period T along with the measurement of the period T, and outputs the count value CNT to the arithmetic circuit 13.
Actually, since a time lag occurs, the pulse period measurement starts at time t2 slightly delayed from time t1, and ends at time t4 slightly delayed from the rise of the pulse CLK at time t3. On the other hand, as shown in FIG. 4B, at time t4, the pulse period measurement is completed and a new pulse period measurement is started.

Next, when the variable n is input from the first instruction circuit 16 and the count value CNT is input from the pulse period measurement circuit 12 at time t4, the arithmetic circuit 13 performs the calculations shown in steps ST1 to ST6 ( The division results D _{1 to} D _n are calculated and output to the pulse output circuit 14 (see FIG. 3). Thus, the number of clocks obtained by dividing the k reference clocks BCLK by the frequency division ratio R = n can be obtained.
Even in the CNT / n calculation, a time lag occurs, and the calculation ends at time t6 slightly delayed from the rise of the pulse CLK at time t5. On the other hand, as shown in FIG. 4B, at time t6, the CNT / n calculation is completed and a new CNT / n calculation is started.

Next, when the division results D _{1 to} D _n are input from the arithmetic circuit 13, the pulse output circuit 14 starts down-counting with the count value CNT as the initial value of the count, and the count value DCNT becomes DCNT = CNT−. When D ₁ , D ₁ -D ₂ , D ₂ -D ₃ are reached, pulses having periods T 1, T 2, T 33 are generated (see FIG. 2D), and these are output to the frequency dividing circuit 15. .
Since a time lag also occurs in the n-divided pulse output, this operation ends at time t8 slightly delayed from the rise of the pulse CLK at time t7. On the other hand, as shown in FIG. 4B, at time t8, the n-divided pulse output is completed and a new n-divided pulse output is started.

Next, as shown in FIG. 4B, when the pulse train CLK (1 / n) divided by n is input from the pulse output circuit 14, the frequency divider 15 divides this by m = 16. Then, a pulse train CLK (m / n) divided by m / n as shown in FIG.
A time lag also occurs in this m division, and the m division ends at time t10 slightly delayed from the rise of the pulse train CLK at time t9. On the other hand, as shown in FIG. 4B, at time t10, m division ends and a new m division starts.
Thereafter, clock cycle measurement, CNT / n calculation, n-divided pulse output, and m-division are performed in a time-sharing manner.

Here, the operation of the frequency dividing device 1 when the period (frequency) of the input pulse train CLK changes irregularly will be described.
FIGS. 5A to 5D are timing charts showing an operation example of the frequency divider according to the first embodiment of the present invention. 5A to 5D show the input pulse train CLK, the reference clock BCLK, the pulse train CLK (1 / n), and the pulse train CLK (m / n), respectively.
Actually, each clock is calculated in a time division manner, but for clarity of explanation, each clock is shown in the same time series in each figure.

As shown in FIG. 5A, the case where the cycle of the input pulse train CLK changes as Ta, Tb (= Ta / 2), Tc (= Ta) is taken as an example.
As an example, the frequency division ratio R is R = m / n = 16/3, the frequency F2 of the reference clock BCLK is constant F2 = 80 MHz, and the frequency F1 of the input pulse train CLK is Fa = 1 / Ta = 1 MHz. , Fb = 1 / Tb = 2 / Ta = 2 × Fa = 2 MHz, and Fc (= Fa) are assumed to change. In order to clarify the explanation, a case where the period (frequency) of the input pulse train CLK changes sharply will be exemplified. However, in practice, it is desirable that the period (frequency) of the input pulse train CLK changes slowly.

As shown in FIG. 5B, the pulse period measuring circuit 12 counts 80 reference clocks BCLK in the periods Ta and Tc, and counts 40 reference clocks BCLK in the period Tb. That is, the count values CNT1 and CNT3 in the periods Ta and Tc are CNT1 = CNT3 = 80. Since the frequency F2 of the reference clock BCLK is constant, the count value CNT2 in the cycle Tb is half of the count value CNT1 = 80, that is, CNT2 = 40.
Then, the arithmetic circuit 13 divides the count value CNT1 = CNT3 = 80 in the periods Ta and Tb by the division ratio R = n = 3, and the count value CNT2 = 40 in the period Tb is divided into the division ratio R = n = Divide by 3.

  Then, as shown in FIG. 5C, the pulse output circuit 14 generates a pulse train CLK (1 / n) divided by n. The periods Ta and Tc and the period Tb differ in the period of the pulse train CLK (1 / n), but the input pulse train CLK is divided by 3 in any period. Thereafter, the frequency dividing circuit 15 divides the pulse train CLK (1 / n) by m to generate the pulse train CLK (m / n) shown in FIG.

  Hereinafter, the frequency dividing device 1 according to the present embodiment is compared with a general frequency dividing device configured by hardware and a general frequency dividing device configured by software. The advantage of 1 will be described.

  A general frequency dividing device oscillates a reference clock having a constant frequency. For example, this is for operating a counter. As in this embodiment, a frequency higher than the frequency of the input pulse train is used. It ’s not a clock. In a general frequency dividing device, when the cycle of an input pulse train changes irregularly, a synchronization signal or the like that matches the cycle cannot be supplied to the counter, and it is difficult to divide the input pulse train.

  On the other hand, in the present embodiment, even when the cycle of the input pulse train CLK changes irregularly, for example, as shown in FIG. 5B, the arithmetic circuit 13 has different cycles Ta and Tb. Further, the count values CNT1 and CNT2 are each divided at a frequency division ratio R = n = 3. Each time the pulse output circuit 14 reaches the value when the count values CNT1 and CNT2 are divided by the frequency division ratio R = n = 3, three pulses are output. Therefore, even if the frequency dividing device 1 is configured by hardware, jitter hardly occurs in the pulse train (m / n) divided by m / n.

  FIG. 6 is a block diagram illustrating a configuration example of the frequency dividing device A configured by general software. For example, when dividing a 1 MHz input pulse train CLK with a frequency division ratio R = m / n = 16/3 using software, the process shown in FIG. 6 is performed.

  First, the input pulse train CLK is counted by the counter A1, and the input pulse train CLK is converted into a digital value Dig. This digital value Dig is sampled by the sample hold circuit A2, for example, every sampling time ΔT = 100 μs equal to the period of software control. However, processing in the counter A1 and the sample hold circuit A2 is performed using hardware.

The adder A4 is sampled n times by the sample and hold circuit A2, and the digital value Dig _n , which is delayed by the sampling time ΔT for one sampling by the delay unit A3, is the n−1th digital value Dig _{n− When 1} is added, the frequency division calculation unit A5 divides the n-th addition result AD _n = Dig _n + Dig _n−1 by the frequency division ratio R = m / n.

For example, assuming that the sampling time ΔT is 100 μs and 100 pulses are input to the frequency division calculation unit A5 at 100 μs, the frequency division calculation unit A5 divides the 100 pulse train CLK by the frequency division ratio R. Then, the calculation result RA _n = 100 / R = 100 / (16/3) = 18.75 is obtained. The calculation result RA _n represents the number of input pulses CLK per sampling time [Delta] T. It is assumed that the calculation result of the frequency division calculation unit A5 is the same every sampling time ΔT.

When the separation calculation unit A8 obtains the integer part and the decimal part of the calculation result RA _n input through the addition unit A6, the separation calculation unit A8 outputs the decimal part DEC _n based on the _nth calculation result RA _n to the delay unit A7. The control signal CTL is output to the pulse generator A9. When the pulse generation unit A9 receives the control signal CTL and outputs a pulse, the clock CLK obtained by dividing the input pulse train CLK by the division ratio R = m / n is generated.
On the other hand, when the delay unit A7 delays the decimal part DEC _n input from the separation calculation unit A8 by the sampling time ΔT, the addition unit A6 adds the decimal part DEC _n and the (n + 1) th operation result RA _{n + 1.} The operation result RA _{n + 1} + DEC _n is output to the separation operation unit A8.

FIG. 7 is a diagram for explaining the calculation result of the separation calculation unit A8 illustrated in FIG.
As illustrated in FIG. 7, a remainder of “0.75” is generated in the _nth calculation result RA _n = 18.75. When the integer part of the calculation result RA _n is “18” and the decimal part DEC _n is “0.75”, the decimal part is used for the (n + 1) th calculation by the frequency division calculation unit A5 after the sampling time ΔT. Carried over.
That is, the calculation result of the (n + 1) th time is RA _{n + 1} = 18.75 + 0.75 = 19.05. Since the remainder of “0.05” also occurs in this calculation result, the decimal part “0.05” is carried over to the (n + 2) th calculation.
Similarly, the n + 2 calculation result is RA _{n + 2} = 18.75 + 0.5 = 19.25, and the n + 3 calculation result is RA _{n + 3} = 18.75 + 0.25 = 19.0.

The pulse generation unit A9 outputs a pulse every time it receives the control signal CTL from the separation calculation unit A8. As with a general frequency divider configured by hardware, the pulse generation unit A9 includes 18 separation calculation units A8 or The control signal CTL can be output to the pulse generator A9 only for every 19 pulses.
Therefore, as indicated by the hatched portion in FIG. 7, one pulse is left in the calculation of the frequency division calculation unit A5 at the (n + 1) th time, the (n + 2) th time, and the (n + 3) th time. However, the remainder of the pulse does not occur in the next (n + 4) th computation, as in the (n + 1) th computation. Assuming that the process of obtaining the decimal part of each calculation result is one cycle, if the frequency divider A repeats this process for four cycles, the remaining pulses can be paid out.

  This extra pulse causes jitter. The jitter between the edges of the pulses in the general frequency dividing device A is expressed by equation (2).

(Equation 2)
(1 / 18-1 / 19) / (1 / 18.75) × 100 = ± 5.5% (2)

On the other hand, the jitter in the frequency divider 1 according to this embodiment is obtained as follows. As shown in FIG. 2B, when the count value of the pulse period measurement circuit 12 is CNT = 80, when this is divided by the variable n = 3, k = 80 reference clocks BCLK are k1 = 26, It is divided into three, k2 = 27 and k3 = 27.
Therefore, the maximum value MAX and the minimum value MIN of the period of the pulse train CLK (m / n) output from the frequency divider circuit 15 shown in FIG. 2E are expressed by the following equations (3.1) and (3.2). Represented. However, the symbol “int” is a symbol representing the integer part of (m / n) as described above.

(Equation 3)
MAX = CNT × (1 / F2) × int (m / n) + T2 + T3
= 80 x (1/80 MHz) x 5 + 337.5 ns + 337.5 ns
= 5.675 μs (3.1)

MIN = CNT × (1 / F2) × int (m / n) + T1 + T2 (= T3)
= 80 x (1/80 MHz) x 5 + 325 ns + 337.5 ns
= 5.6625 μs (3.2)

  When the expressions (3.1) and (3.2) are used, the jitter generated in the pulse train CLK (m / n) is expressed by the expression (4).

(MAX-MIN) / {(CNT / n) × m × (100 μs / 80)}
= (5.6725 μs−5.6625 μs) / {(80/3) × 16 × (100 μs / 80)}
= ± 0.2% (4)

  According to the equations (2) and (4), the jitter generated in the frequency dividing device 1 according to the present embodiment is approximately 1/27 of the jitter generated in the general frequency dividing device A that performs software processing. Very small. This is due to the following two reasons.

The first reason is that in this embodiment, the input pulse train CLK is not sampled. The second reason is that in this embodiment, as shown in FIG. 5A, even if the period of the input pulse train CLK changes irregularly, no extra pulses are generated.
As described above, according to the frequency dividing device 1 according to the present embodiment, the period of the input pulse train CLK changes irregularly, and even when the frequency is divided by m / n, the occurrence of jitter is extremely small and extremely accurate. A high m / n frequency divided pulse train can be generated.

[Second Embodiment]
In the frequency dividing device 1 according to the first embodiment, even when the period of the input pulse train CLK changes irregularly, the occurrence of jitter is extremely small. For example, control of the servo motor that changes the rotation speed at an irregular period. It is suitable for.
Therefore, in the second embodiment, a servo control circuit that mounts the frequency divider 1 and controls the servo motor will be described with reference to FIG.

FIG. 8 is a block diagram illustrating a configuration example of a servo control circuit according to the second embodiment.
A servo control circuit 2 illustrated in FIG. 8 includes a control circuit 21 having a frequency divider 1, a drive circuit 22, and a detection circuit 23.
The servo control circuit 2 corresponds to the control circuit of the present invention.

  The servo control circuit 2 controls, for example, a pulse width modulation type servo motor 24. The servo control circuit 2 performs feedback control to detect the position, speed, angle, etc. of the controlled object, and reduce the rotation speed (rotation) of the servo motor 24 so as to reduce the deviation (offset) from the target value. Speed).

  The control circuit 21 generates a control signal CTL for controlling the drive circuit 22 using the pulse train CLK input from the detection circuit 23, and outputs this to the drive circuit 22. The control signal CTL includes a pulse train frequency-divided by the frequency divider 1 by m / n.

When the control circuit 21 generates the control signal CTL, the frequency dividing device 1 divides the input pulse train CLK by the frequency division ratio R = m / n and uses this as a part of the control signal CTL.
In the present embodiment, as an example, the pulse width modulation type servo motor 24 is employed. Therefore, if the frequency divider 1 divides the input pulse train CLK by the frequency dividing ratio R = m / n, The rotational speed can be changed to m / n times.

  The drive circuit 22 generates a drive signal DRV for driving the servo motor 24 by using the control signal CTL input from the control circuit 21, and outputs this to the servo motor 24.

  The servo motor 24 is, for example, an AC (alternating current) motor that can rotate the rotating shaft 241 clockwise or counterclockwise. The servo motor 24 may be a linear motor, for example. The servo motor 24 rotates the rotary shaft 241 at a rotation speed corresponding to the drive signal DRV input from the drive circuit 22.

The detection circuit 23 has a function of a rotary encoder and is connected to the servo motor 24. The detection circuit 23 detects the rotational displacement of the rotary shaft 241, converts it into a digital pulse train CLK, and then outputs this pulse train CLK to the frequency divider 1 of the control circuit 21.
When the servomotor 24 has the A phase and the B phase, the detection circuit 23 outputs the A phase pulse train and the B phase pulse train to the frequency divider 1 of the control circuit 21.

Since the servo motor 24 has a large starting torque and a short time to reach a stable rotational speed compared to that of other motors, the servo motor 24 can operate stably at a wide rotational speed (rotational speed).
Therefore, if the frequency dividing device 1 is used, even if the pulse train CLK whose cycle changes irregularly is divided by m / n, the occurrence of jitter is extremely small, and the rotational speed of the servo motor 24 is controlled with high accuracy and accuracy. be able to.

  The servo control circuit 2 having such advantages can be used, for example, in a servo motor control part of an NC (Numerical Control) device or a CT (Computed Tomography) device.

[Modification of Frequency Divider 1]
In the servo control circuit 2 equipped with the frequency dividing device 1, when the servo motor 24 has the A phase and the B phase, the frequency dividing device 1 can be configured as shown in FIG.

FIG. 9 is a block diagram illustrating a configuration example of a frequency dividing device according to a modified example of the present invention.
A frequency dividing device 1a illustrated in FIG. 9 includes a reference clock generation circuit 11, a pulse period measurement circuit 12, an arithmetic circuit 13, a pulse output circuit 14, a frequency dividing circuit 15, a first instruction circuit 16, and a second instruction circuit 17. In addition, a first pulse form changing circuit 18 and a second pulse form changing circuit 19 are added.

  It is assumed that the phase A pulse train illustrated in FIG. 9 input from the detection circuit 23 is advanced in phase by 90 degrees with respect to the phase B pulse train. In this case, if one of the pulse trains is divided by a frequency division ratio R = m / n, and the phase of one of the pulse trains divided by m / n is shifted by 90 degrees after that frequency division, the other pulse train is generated. be able to.

Therefore, when the A-phase and B-phase pulse trains are input, the first pulse form changing circuit 18 outputs the A-phase pulse train as the pulse train CLK to the pulse period measuring circuit 12 and encodes the B-phase pulse train. To the pulse period measuring circuit 12.
In the encoding of the B-phase pulse train, the encoding may be performed so that the pulse train becomes zero. Of course, it is also possible to encode the A-phase pulse train and output the B-phase pulse train to the pulse period measuring circuit 12.

  When the pulse train CLK (m / n) frequency-divided by m / n is input from the frequency divider circuit 15, the second pulse shape change circuit 19 generates a pulse train CLK (m / n) delayed by 90 degrees. This is generated and output to the drive circuit 22 (see FIG. 8) as a B-phase pulse train, and the pulse train CLK (m / n) is output to the drive circuit 22 as an A-phase clock.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 1, 1a ... Frequency divider, 11 ... Reference clock generation circuit, 12 ... Pulse period measurement circuit, 13 ... Arithmetic circuit, 14 ... Pulse output circuit, 15 ... Frequency divider circuit, 16 ... First indication circuit, 17 ... Second Indication circuit, 18 ... first pulse form change circuit, 19 ... second pulse form change circuit, 2 ... servo control circuit, 21 ... control circuit, 22 ... drive circuit, 23 ... detection circuit, 231 ... rotary shaft, 24 …Servomotor.

Claims (6)

A frequency dividing device capable of dividing an input pulse by a frequency dividing ratio represented by a ratio of the second variable to the first variable, wherein the first variable and the second variable are different positive integers;
A counter circuit that counts a reference clock having a constant frequency over the period of the input pulse;
An operation is performed to divide the first count value obtained by the counter circuit into a value indicated by the first variable, and the counting of the reference clock is started, and the second count value by the count becomes the first count value. An arithmetic output circuit that outputs one pulse each time the divided value is reached;
A frequency dividing circuit for outputting a pulse obtained by dividing the output pulse train of the arithmetic output circuit by a value indicated by the second variable;
A frequency divider. The arithmetic output circuit is:
When the first count value is divided by the value indicated by the first variable and when the second count value reaches the value indicated by the integer part of the division result, one pulse is output,
After the output of the pulse, the value indicated by the integer part of the division result is subtracted from the first count value, and the subtraction result is evenly or as evenly as possible with the remaining number to be divided by the first variable. 2. The frequency dividing device according to claim 1, wherein the dividing unit outputs one pulse every time the second count value reaches a value obtained by dividing the subtraction result equally or as evenly as possible. The frequency dividing device according to claim 1, further comprising: a clock generation circuit that generates a clock having a frequency higher than a frequency of the input pulse as the reference clock. The frequency dividing device according to any one of claims 1 to 3, further comprising a measurement circuit that measures a cycle of the input pulse. The divider circuit is
5. The pulse output from the arithmetic output circuit is counted, and one pulse is output each time a third count value based on the count reaches a value indicated by the second variable. 6. Frequency divider. The first variable and the second variable take different positive integers, and have a frequency divider that can divide the input pulse by a frequency division ratio represented by the ratio of the second variable to the first variable. A control circuit that uses the output of the peripheral device,
The frequency divider is
A counter circuit that counts a reference clock having a constant frequency over the period of the input pulse;
An operation for dividing the first count value obtained by the counter circuit into a value indicated by the first variable is performed, and the counting of the reference clock is started. An arithmetic output circuit that outputs one pulse each time the divided value is reached;
A frequency dividing circuit for outputting a pulse obtained by dividing the output pulse train of the arithmetic output circuit by a value indicated by the second variable;
A control circuit.

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