JP2002116058A - Encoder data conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an encoder data conversion circuit capable of performing calculation by taking in detection position data at any time in the side of a high order controller for receiving the detection position data from a serial encoder to perform control. SOLUTION: A difference between current cyclic position data and position data before one cycle is taken with a subtractor 107, the data of the increment of differential data are converted into a pulse train by an adder 12 and a register 123, counting is performed by a counter 131 on the basis of the symbol of the differential data and the converted pulse train, the contents of the counter 131 are time-serially superposed on the current cyclic position data by the adder 141, and the position data are generated at an arbitrary time to linearly time- serially interpolate a part between the current cycles from the position data of the current cycle and before one cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoder data conversion circuit for receiving position data sent from an encoder at a constant period and converting the data into position data at an arbitrary time. The present invention relates to an encoder data conversion circuit in which a higher-level controller that receives and controls can always take in detection position data and perform an operation.

[0002]

2. Description of the Related Art A serial encoder used as a position detecting means in a FA system or a position / speed control of a servomotor of a FA robot sends out detected position data at a constant period. On the upper controller side, which performs the control in this way, it is necessary to match the operation cycle in the controller with the transmission cycle of the serial encoder.

[0003]

As described above, it is necessary for the host controller to match the operation cycle in the controller with the transmission cycle of the serial encoder, which means that the degree of freedom of the controller is limited. ,
In addition, a circuit for synchronizing the operation cycle of the controller with the transmission cycle of the serial encoder is required, which has been a factor that affects the system scale and cost. Further, in order to improve the control accuracy of the controller, it is necessary to prepare a serial encoder having a short transmission cycle, which also causes an increase in system cost. The present invention has been made in view of the above-described conventional circumstances, and an encoder data conversion circuit that receives position data sent from an encoder at a constant cycle and converts the data into position data at an arbitrary time. There is no need to adjust the operation cycle in the controller to the transmission cycle of the serial encoder on the higher-level controller that receives and controls the detection position data of the controller. It is an object of the present invention to provide an encoder data conversion circuit capable of improving the degree.

[0004]

According to a first aspect of the present invention, there is provided an encoder data conversion circuit which receives position data sent from an encoder at a constant period, and receives position data at an arbitrary time. An encoder data conversion circuit for converting the difference data between the position data of the current cycle and the position data of one cycle before; and a data for increasing the difference data based on the difference data obtained by the difference means. To a pulse train, a counting unit for counting based on the sign of the difference data and the pulse train of the pulse output unit, and superimposing the counting content of the counting unit on the current cycle position data in time series. And superimposing means. An encoder data conversion circuit according to a second aspect of the present invention is an encoder data conversion circuit for receiving position data sent from an encoder at a fixed period and converting the data into position data at an arbitrary time. Based on the position data of the current cycle and the position data of the previous cycle, based on the position data of the current cycle and the position data of the current cycle, based on the increment data obtained by the increment prediction means, Pulse output means for converting the increment data of the increment data into a pulse train; counting means for counting based on the sign of the incremental data and the pulse train of the pulse output means; And a superimposing means for superimposing in a time series. An encoder data conversion circuit according to a third aspect of the present invention is an encoder data conversion circuit for receiving position data sent from an encoder at a constant cycle and converting the data into position data for an arbitrary time. A timer that counts the current period, a difference unit that calculates a difference between the position data of the current period and the position data of the previous period, and a position data of the current period based on the difference data obtained by the difference unit and the count content of the timer. And a superimposing means for superimposing the calculation result of the incremental computing means on the position data of the current cycle in a time series manner. Further, in the encoder data conversion circuit according to claim 4, in the encoder data conversion circuit according to claim 1, 2, or 3, the final result of the superimposing means in the current cycle is the same as the position data after one cycle. That is what it was.

In the encoder data conversion circuit according to the first and fourth aspects of the present invention, when the position data sent from the encoder at a constant cycle is received, the difference data means the position data of the current cycle and the position data of the previous cycle are compared with each other. , And based on the difference data obtained by the difference means, the pulse output means converts the increased data of the difference data into a pulse train, and counts by the counting means based on the sign of the difference data and the pulse train of the pulse output means. Then, the counting content of the counting means is superimposed on the position data of the current cycle in time series by the superimposing means to generate position data for an arbitrary time. Here, it is desirable that the final result of the superimposing means in the current cycle be the same as the position data after one cycle. In this manner, the difference between the position data of the current cycle and the position data of one cycle before is assumed to be the incremental data from the position data of the current cycle to the position data of one cycle after, and the position data of the current cycle is added to the position data of the current cycle. The content of the count is superimposed in time series, and this is used as position data at an arbitrary time, so that linear interpolation is performed in time series from the current cycle and the position data of one cycle before in the current cycle. The upper controller, which receives and controls the detected position data, does not need to adjust the operation cycle in the controller to the transmission cycle of the serial encoder, and the apparently latest detected position data can be used without increasing the transmission cycle of the serial encoder. The calculation can be performed at any time, and as a result, the degree of freedom of the controller can be improved. Further, in the encoder data conversion circuit according to the second and fourth aspects, when the position data sent from the encoder at a constant cycle is received, the position data of the current cycle, the position data of one cycle before and the position data of two cycles before are received by the increment prediction means. Based on the position data of the current cycle, predicts the incremental data of the position data one cycle after the position data of the current cycle, and based on the incremental data obtained by the incremental predicting means,
The increment data of the increment data is converted into a pulse train by the pulse output means, and counting is performed by the counting means on the basis of the sign of the incremental data and the pulse train of the pulse output means. The content is superimposed in a time series to generate position data at an arbitrary time. Here, it is desirable that the final result of the superimposing means in the current cycle be the same as the position data after one cycle. Thus, based on the position data of the current cycle, the position data of one cycle before and the position data of two cycles before,
By predicting the incremental data of the position data one cycle after the current period position data, superimposing the count contents of the counting means on the current period position data in time series, and using this as the position data at an arbitrary time. The secondary controller performs time-sequential secondary interpolation (spiral interpolation) from the position data of the current period, the previous period, and the previous period during the current period. It is no longer necessary to adjust the operation cycle in the controller to the transmission cycle of the serial encoder, and it is possible to take the apparently latest detected position data at any time and perform the operation without increasing the transmission cycle of the serial encoder. As a result, the degree of freedom of the controller can be improved. Further, in the encoder data conversion circuit according to the third and fourth aspects, upon receiving the position data sent from the encoder at a constant cycle, the difference means calculates the difference between the position data of the current cycle and the position data of one cycle before. On the basis of the count value of the timer synchronized with the receiving cycle of the difference data and the position data obtained by the difference means, the incremental data for the current cycle position data is calculated in a time series by the incremental calculating means, and the current cycle is calculated by the superimposing means. The position data of an arbitrary time is generated by superimposing the calculation result of the increment operation means on the position data in time series. Here, it is desirable that the final result of the superimposing means in the current cycle be the same as the position data after one cycle. In this manner, the difference between the position data of the current cycle and the position data of one cycle before is multiplied by the ratio of the current time (contents counted by the timer) to the transmission cycle to calculate the incremental data at the current time. The position data of an arbitrary time is superimposed on the position data of the current cycle in a sequence, and the position data of the arbitrary period is interpolated in time series from the position data of the current cycle and the position of the previous cycle during the current cycle. It is no longer necessary to adjust the operation cycle in the controller to the transmission cycle of the serial encoder on the higher-level controller side that receives and controls the data, and the apparently latest detection position data can be fetched at any time without increasing the transmission cycle of the serial encoder. Calculation can be performed, and as a result, the degree of freedom of the controller can be improved.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of an encoder data conversion circuit according to the present invention will be described with reference to [first embodiment].
The second embodiment and the third embodiment will be described in detail with reference to the drawings. Note that the encoder data conversion circuit described in the following embodiment is an
It is provided on the host controller that controls the position and speed of the servomotor of the robot A, and receives position data sent from the serial encoder used as position detection means at regular intervals, and receives position data for an arbitrary time. To be provided to the calculation in the controller. [First Embodiment] FIG. 1 is a configuration diagram of an encoder data conversion circuit according to a first embodiment of the present invention. In the figure, an encoder data conversion circuit according to the present embodiment includes an n-bit shift register 101, an n-bit first buffer 103, an n-bit second buffer 105, and a subtractor 10
7, an adder 121, an n-bit register 123, an n-bit counter 131, and an adder 141. Here, n is an integer value set according to the resolution of the serial encoder, the calculation in the controller, and the like. The n-bit shift register 101 sequentially takes in the position data sent from the serial encoder at a constant period, that is, serial data SDT, and outputs it as parallel data. The n-bit first buffer 103, the n-bit second buffer 105, and the subtracter 107 correspond to a difference unit, and take the difference between the position data of the current cycle and the position data of one cycle before. That is, each of the first buffer 103 and the second buffer 105 is a register in which n D-type flip-flops are arranged in parallel.
Since the input data is latched by the sampling signal SAMP, the first buffer 103 holds the position data of the current cycle, and the second buffer 105 holds the position data of the previous cycle. By taking the difference between the output data of the first buffer 103 and the output data of the second buffer 105, the difference between the position data of the current cycle and the position data of the previous cycle can be obtained. Here, the sampling signal SAMP is a signal synchronized with the transmission cycle of the serial data SDT, and the contents of the first buffer 103 and the second buffer 105 are updated every transmission cycle of the serial data SDT.

Next, the adder 121 and the n-bit register 123 correspond to pulse output means, and convert the data of the increment of the differential data into a pulse train based on the differential data output from the subtracter 107. is there. That is, the pulse output means uses an n-bit half-integrator (DDA: Digital Differencial Analyzer) that repeatedly performs an addition operation on the difference data based on the clock CP and outputs an overflow OVF generated by the addition operation. For example, in a 10-bit semi-integrator, 102
The operation goes around by counting the pulses of 4 (this means that the content of the register 123 becomes 0),
An overflow signal OVF having the same number of pulses as the value of the difference data is generated. Next, the n-bit counter 131 corresponds to the counting means, and the sign SGN of the difference data is used.
And counting based on a pulse train (overflow OVF) output from the pulse output means (adder 121). First, in a pulse discriminator (not shown),
Based on the sign (positive or negative) of the difference data and the overflow OVF output from the adder 121, a pulse train for each rotation direction synchronized with the clock CP is generated. That is, since the most significant bit of the differential data is the sign bit SGN, when the sign bit SGN is “0”, the overflow signal OVF is reflected in the forward rotation direction pulse train, and when the sign bit SGN is “1”, Overflow signal OV
F is reflected in the negative rotation direction pulse train. Then, the up / down counter (131) counts up / down according to the pulse train for each rotation direction obtained by the pulse discriminating unit. That is, up-counting is performed by a positive rotation direction pulse train, and down-counting is performed by a negative rotation direction pulse train. Note that the counter 131 is cleared by the sampling signal SAMP. Further, adder 1
Reference numeral 41 corresponds to a superimposing unit, and obtains time-series superimposed data DATA by adding the count content of the counter 131 to the output of the first buffer 103, which is position data of the current cycle.

In the encoder data conversion circuit of the present embodiment, position data is sent from the serial encoder at a fixed period, so that the position data is received every period of the sampling signal SAMP, and as shown in FIG. When it increases with time, stepwise position data is input with respect to time. That is,
Position data SDT0 at time T0, position data SDT1 at time T1, position data SDT2 at time T2.
Assuming that the current cycle is a time zone between time T1 and time T2, the first buffer 103 stores the position data SD of the current cycle in the first buffer 103.
T1 holds the position data SDT0 of the previous cycle in the second buffer 105, and the subtracter 107 outputs these difference data ΔSD1. At this time, in the adder 121 and the register 123,
The addition operation is repeatedly performed on the difference data ΔSD1 based on the clock CP to generate an overflow signal OVF having the same number of pulses as the difference data ΔSD1.
The counter 131 detects the pulse train (overflow OV).
Since the counting of F) is performed, the value corresponding to the position data of the hatched portion in FIG. 2 is output from the counter 131 in time series. Further, the adder 141 adds the count value of the counter 131 to the output of the first buffer 103 (the position data SDT1 in the current cycle) to obtain superimposed data DATA in a time series. In other words, in the current cycle (time period between time T1 and time T2) in FIG. 2, position data obtained by time-series linear interpolation as position data at an arbitrary time is obtained. Note that the addition cycle of the counter 131, that is, the cycle of the output pulse generated by the adder 121 and the register 123 is the position data S
When the difference between the DR0 and the position data SDT1 of the current cycle (difference data ΔSD1) is large, it becomes shorter, so that the clock CP
Of the clock cycle of the above. Also, the counter 13
Since 1 is cleared by the sampling signal SAMP, an error due to interpolation does not propagate in the next cycle.
The superimposition data DATA of the current cycle and the position data SDT2 of the current cycle in the next cycle can be identified.

As described above, in the encoder data conversion circuit of the present embodiment, the position data SDT1
(ΔSD1) between the position data SDT0 and the position data SDT0 one cycle before
Is assumed to be incremental data (SDT2) from the current cycle position data SDT1 to the position data SDT2 one cycle later, and a counting means (counter 13) is added to the current cycle position data SDT1.
By superimposing the count contents of 1) in time series and using this as position data at an arbitrary time, linear interpolation is performed in time series between the current cycle and the position data of the current cycle and one cycle before, so that The host controller, which receives and controls the detection position data from the serial encoder, does not need to adjust the operation cycle in the controller to the transmission cycle of the serial encoder, and the apparent latest detection without increasing the transmission cycle of the serial encoder The position data can be fetched at any time to perform the calculation, and as a result, the degree of freedom of the controller can be improved. Since the transmission cycle of the serial encoder is usually several tens of microseconds, sufficient accuracy can be obtained by the encoder data conversion circuit of the present embodiment using linear interpolation, considering the mechanical time constant of the servo system. Is possible.
In the present embodiment, the adder 1 is used as the pulse output means.
Although the configuration of the n-bit half-integrator (DDA) using the 21-bit and the n-bit register 123 is used, the invention is not limited to this, and an n-bit binary rate multiplier (BRM) may be used.

[Second Embodiment] FIG. 3 is a block diagram of an encoder data conversion circuit according to a second embodiment of the present invention. In the figure, an encoder data conversion circuit according to the present embodiment includes an n-bit shift register 301, an n-bit first buffer 303, and an n-bit second buffer 3.
05, n-bit third buffer 307, first subtractor 31
1, a second subtractor 309, a first constant multiplier 315, a second constant multiplier 313, an adder 317, an adder 321, an n-bit register 323, an n-bit counter 331, and an adder 341. ing. Here, n is the same as in the first embodiment. As in the first embodiment, the n-bit shift register 301 sequentially takes in position data, that is, serial data SDT sent from the serial encoder at a constant period, and outputs it as parallel data. Also, the n-bit first buffer 30
3, an n-bit second buffer 305, an n-bit third buffer 307, a first subtractor 311, a second subtractor 309,
The first constant multiplier 315, the second constant multiplier 313, and the adder 317 correspond to incremental prediction means, and include position data of the current cycle,
Based on the position data of one cycle before and the position data of two cycles before, the incremental data of the position data of one cycle after the current cycle position data is predicted. That is, the first buffer 3
03, second buffer 305 and third buffer 307
Are registers in which n D-type flip-flops are arranged in parallel, and input data is latched by the sampling signal SAMP. Therefore, the first buffer 303 stores position data of the current cycle, and the second buffer 305 stores one cycle of position data. The previous position data is stored in the third buffer 307, and the position data two cycles before is stored in the third buffer 307. Further, the first buffer 303 and the second buffer 305 are
, The difference is multiplied by K1 in the first constant multiplier 315, and the second buffer 305 is calculated in the second subtractor 309.
And the difference between the output data of the third buffer 307 and
The difference is multiplied by K2 in a second constant multiplier 313. Further, the adder 317 adds the two to obtain the incremental data of the position data after one cycle. Here, the sampling signal SAM
P is a signal synchronized with the transmission cycle of the serial data SDT, and the contents of the first buffer 303, the second buffer 305, and the third buffer 307 are updated every transmission cycle of the serial data SDT.

Next, the adder 321 and the n-bit register 323 correspond to pulse output means, and convert the increment data of the increment data into a pulse train based on the increment data output from the adder 317. is there. That is, the pulse output means uses an n-bit half-integrator (DDA) that repeatedly performs an addition operation on the incremental data based on the clock CP and outputs an overflow OVF generated by the addition operation. An overflow signal OVF having the same number of pulses as the value will be generated. Next, the n-bit counter 331 corresponds to the counting means, and counts based on the sign SGN of the incremental data and the pulse train (overflow OVF) output from the pulse output means (adder 321). First, a pulse discriminator (not shown) generates a pulse train for each rotation direction synchronized with the clock CP based on the sign (positive or negative) of the incremental data and the overflow OVF output from the adder 321. That is, since the most significant bit of the incremental data is the sign bit SGN, the sign bit SGN
When GN is “0”, the overflow signal OVF is reflected in the pulse train in the forward rotation direction, and the sign bit SGN is set to “1”.
, The overflow signal OVF is reflected in the pulse train in the negative rotation direction. Then, the up / down counter (331) counts up / down according to the pulse train for each rotation direction obtained by the pulse discriminating unit. In other words, the up-count by the forward rotation direction pulse train,
The down count is performed by the pulse train in the negative rotation direction.
Note that the counter 331 has been cleared by the sampling signal SAMP. Further, the adder 341 corresponds to the superimposing means, and adds the count content of the counter 331 to the output of the first buffer 303, which is the position data of the current cycle, to obtain time-series superimposed data DATA.

Also in the encoder data conversion circuit of this embodiment, as shown in FIG. 4, the position data is stepwise with respect to time, that is, the position data SDT0 at time T0, the position data SDT1 at time T1, and the position data SDT1 at time T2. Position data SD
T2,... Are input. Assuming that the current cycle is a time zone between time T2 and time T3, the first buffer 303
Contains the position data SDT2 of the current cycle in the second buffer 30.
5, the third buffer 307 holds the position data SDT0 of the current cycle, and the third buffer 307 holds the position data SDT0 of the current cycle. The difference data ΔSD2 of the data SDT1 is output, the difference data ΔSD2 is multiplied by K1 in the first constant multiplier 315, and the second subtractor 309
, The difference data ΔSD1 between the position data SDT1 one cycle before and the position data SDT0 two cycles before is output,
The difference data ΔSD1 is multiplied by K2 in the constant multiplier 313,
Further, in the adder 317, these K1 × ΔSD2 and K1
2 × ΔSD1 is added. That is, the incremental data ΔD
Is calculated by the following equation. ΔD = K1 × (SDT2-SDT1) + K2 × (SDT1-SDT0) = K1 × ΔSD2 + K2 × ΔSD1 Here, the constants K1 and K2 are determined by the secondary interpolation formula used. At this time, the adder 321 and the register 323 repeatedly perform an addition operation on the increment data ΔD based on the clock CP to generate an overflow signal OVF having the same number of pulses as the increment data ΔD. Overflow OVF)
Therefore, the value corresponding to the position data of the hatched portion in FIG. 4 is output from the counter 331 in time series. Further, the adder 341 adds the count value of the counter 331 to the output of the first buffer 303 (the position data SDT2 of the current cycle) to obtain superimposed data DATA in a time series. That is, in the current period (time zone between time T2 and time T3) in FIG. 4, position data obtained by linearly interpolating time-series as position data at an arbitrary time is obtained. Note that the addition period of the counter 331, that is, the period of the output pulse generated by the adder 321 and the register 323 becomes shorter when the increment data ΔD is large, and therefore, the clock period of the clock CP may be divided. The counter 331 outputs the sampling signal S
Since the signal is cleared by the AMP, an error due to interpolation does not propagate to the next cycle, and the superimposition data DAT of the current cycle is not transmitted.
A can be identified with the current cycle position data SDT3 in the next cycle.

As described above, in the encoder data conversion circuit of the present embodiment, the position data SDT of the current cycle is
2, based on the position data SDT1 one cycle before and the position data SDT0 two cycles before,
2 increment data (ΔSD) of the position data after one cycle
3) is predicted, and the count content of the counting means (counter 331) is superimposed in a time series on the position data SDT2 of the current cycle, and this is used as position data of an arbitrary time. Since the position data of one cycle before and two cycles before are subjected to secondary interpolation (spiral interpolation) in a time series, the upper controller which receives and controls the detected position data from the serial encoder determines the operation cycle in the controller. It is no longer necessary to match the transmission cycle of the serial encoder, and it is possible to take the apparently latest detection position data at any time and perform calculations without increasing the transmission cycle of the serial encoder, thereby improving the flexibility of the controller. The obtained encoder data conversion circuit can be provided. As described in the first embodiment, sufficient accuracy can be obtained by linear interpolation. However, if higher accuracy is desired, the encoder data using the secondary interpolation as in the present embodiment is used. What is necessary is just to use the structure of a conversion circuit. In this embodiment, an n-bit semi-integrator (DD) composed of an adder 321 and an n-bit register 323 as pulse output means is used.
Although the configuration of A) was used, the present invention is not limited thereto.
Bit binary rate multiplier (BRM)
May be used.

[Third Embodiment] FIG. 5 is a configuration diagram of an encoder data conversion circuit according to a third embodiment of the present invention. In the figure, the encoder data conversion circuit of the present embodiment includes an n-bit shift register 501, an n-bit first buffer 503, an n-bit second buffer 505,
Subtractor 507, increment calculator 521, timer counter 53
1 and an adder 541. Here, n is an integer value set according to the resolution of the serial encoder, the calculation in the controller, and the like. n
As in the first embodiment, the bit shift register 501 sequentially fetches position data, that is, serial data SDT sent from the serial encoder at a constant period, and outputs it as parallel data. The n-bit first buffer 503, the n-bit second buffer 505, and the subtracter 507 correspond to a difference means, and take the difference between the current cycle position data and the previous cycle position data. That is, since the first buffer 503 and the second buffer 505 latch the input data with the sampling signal SAMP, the position data of the current cycle is stored in the first buffer 503, and the position data of the previous cycle is stored in the second buffer 505, respectively. The difference between the output data of the first buffer 503 and the output data of the second buffer 505 is obtained by the subtracter 507, whereby the difference between the position data of the current cycle and the position data of the previous cycle is obtained. Here, the sampling signal SAMP is a signal synchronized with the transmission cycle of the serial data SDT, and the contents of the first buffer 503 and the second buffer 505 are updated every transmission cycle of the serial data SDT. Next, the timer counter 531
The clock C is synchronized with the transmission cycle of the serial data SDT.
It counts P and is cleared by the sampling signal SAMP. Further, the increment calculator 521 is configured to output the difference data output from the subtractor 507 and the timer counter 5.
Based on the count value of 31, the incremental data with respect to the position data of the current cycle is calculated in time series. That is, the increment calculator 521 calculates the following data by calculating the following equation. Increment data = difference data × count value of timer counter / transmission cycle Further, the adder 541 corresponds to the superimposing means, and adds the increment data calculated by the increment calculator 521 to the output of the first buffer 503 which is the position data of the current cycle. The addition results in time-series superimposed data DATA.

In the encoder data conversion circuit of the present embodiment, as in the first embodiment, referring to FIG. 2, if the current cycle is a time zone between time T1 and time T2, the first buffer 503 Contains position data SDT1 of the current cycle,
In the second buffer 505, the position data SDT0 one cycle before is stored.
Are held, and the difference data ΔSD1 is output from the subtractor 507. on the other hand,
In the timer counter 531, the clock C
Since the current time is counted by counting the number of pulses of P, the increment calculator 521 multiplies the difference data ΔSD1 by the ratio of the current time (the count value of the timer counter 531) to the transmission cycle, thereby obtaining the current time. Incremental data can be calculated. Therefore, the adder 541
In, by adding the increment data calculated by the increment calculator 521 to the output of the first buffer 503 (position data SDT1 of the current cycle), superimposed data DATA is obtained in a time series. In other words, in the current cycle (time period between time T1 and time T2) in FIG. 2, position data obtained by time-series linear interpolation as position data at an arbitrary time is obtained.

As described above, in the encoder data conversion circuit of the present embodiment, the current period position data SDT1
Data ΔSD between the position data SDT0 and the position data SDT0 one cycle before
1 is multiplied by the ratio of the current time (the count value of the timer counter 531) to the transmission cycle to calculate the incremental data at the current time. Time position data is used, and linear interpolation is performed in time series between the current cycle and the position data of the current cycle and the previous cycle during the current cycle. There is no need to match the operation cycle of the serial encoder with the transmission cycle of the serial encoder, and it is possible to take in the apparently latest detected position data at any time and perform the operation without increasing the transmission cycle of the serial encoder. An encoder data conversion circuit capable of improving the degree can be provided.

[0017]

As described above, according to the encoder data conversion circuit of the present invention, the difference between the position data of the current cycle and the position data of one cycle before is determined by the position of the position data one cycle after the current cycle. By assuming incremental data to the data, the count content of the counting means is superimposed in time series on the position data of the current cycle, and this is used as position data at an arbitrary time,
Since the current cycle and the position data of one cycle before are linearly interpolated in time series during the current cycle, the operation cycle in the controller is determined by the serial encoder on the higher-level controller that receives and controls the detected position data from the serial encoder. It is no longer necessary to adjust to the transmission cycle of the encoder, and it is possible to take in the apparently latest detected position data at any time and perform calculations without increasing the transmission cycle of the serial encoder, and as a result, an encoder that can improve the degree of freedom of the controller A data conversion circuit can be provided. Further, according to the encoder data conversion circuit of the present invention, based on the position data of the current cycle, the position data of one cycle before and the position data of two cycles before, the incremental data of the position data of one cycle after with respect to the position data of the current cycle Predict
The count data of the counting means is superimposed on the position data of the current cycle in a time-series manner, and this is used as position data of an arbitrary time. Time-series secondary interpolation (spiral interpolation)
Therefore, it is not necessary for the host controller that receives and controls the detected position data from the serial encoder to adjust the operation cycle in the controller to the transmission cycle of the serial encoder. The latest detection position data can be taken at any time to perform calculations,
As a result, an encoder data conversion circuit capable of improving the degree of freedom of the controller can be provided. further,
According to the encoder data conversion circuit of the present invention, the difference between the position data of the current cycle and the position data of one cycle before is multiplied by the ratio of the current time (contents counted by the timer) to the transmission cycle to obtain the incremental data at the current time. Is calculated, and this is superimposed on the position data of the current cycle in a time series to obtain position data at an arbitrary time, and linear interpolation is performed in a time series between the current cycle and the position data of one cycle before the current cycle. The upper controller that receives and controls the detection position data from the serial encoder does not need to adjust the operation cycle in the controller to the transmission cycle of the serial encoder, without increasing the transmission cycle of the serial encoder.
It is possible to fetch the apparently latest detected position data at any time to perform the calculation, and as a result, it is possible to provide an encoder data conversion circuit capable of improving the degree of freedom of the controller.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an encoder data conversion circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating linear correction in an encoder data conversion circuit according to the first and third embodiments.

FIG. 3 is a configuration diagram of an encoder data conversion circuit according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram illustrating secondary correction in an encoder data conversion circuit according to a third embodiment.

FIG. 5 is a configuration diagram of an encoder data conversion circuit according to a third embodiment of the present invention.

[Explanation of symbols]

 101, 301, 501 n-bit shift register 103, 303, 503 n-bit first buffer 105, 305, 505 n-bit second buffer 107, 507 subtractor 307 n-bit third buffer 309 second subtracter 311 1st subtracter 313 2nd constant multiplier 315 1st constant multiplier 317 Adder 121,321 Adder 521 Increment calculator 123,323 n-bit register 131,331 n-bit counter 531 timer counter 141,341,541 Adder SDT Serial data SAMP Sampling signal CP clock DATA Superimposed data

Claims (4)

[Claims] An encoder data conversion circuit for receiving position data sent from an encoder at a constant period and converting the data into position data at an arbitrary time, wherein a difference between the current period position data and the position data one period before is obtained. A difference unit; a pulse output unit configured to convert an increase in the difference data into a pulse train based on the difference data obtained by the difference unit; and a count based on a sign of the difference data and a pulse train of the pulse output unit. An encoder data conversion circuit, comprising: a counting unit that performs counting; and a superimposing unit that superimposes the count content of the counting unit on the position data of the current cycle in a time-series manner. 2. An encoder data conversion circuit for receiving position data sent from an encoder at a constant period and converting the data into position data at an arbitrary time, comprising: a position data of a current period, a position data of one period before, and a position data of two periods before. On the basis of the position data, incremental prediction means for predicting the incremental data of the position data one cycle after the current cycle position data, based on the incremental data obtained by the incremental predicting means,
Pulse output means for converting the increment data of the increment data into a pulse train; counting means for counting based on the sign of the incremental data and the pulse train of the pulse output means; counting of the count means to the current period position data An encoder data conversion circuit, comprising: superimposing means for superimposing contents in time series. 3. An encoder data conversion circuit for receiving position data sent from an encoder at a constant cycle and converting the data into position data for an arbitrary time, a timer for counting in synchronization with a cycle of receiving the position data, A difference means for calculating a difference between the position data of the current cycle and the position data of one cycle before; and, based on the difference data obtained by the difference means and the count content of the timer, incrementally increasing the position data of the current cycle in time series. An encoder data conversion circuit comprising: an increment calculating means for calculating; and a superimposing means for superimposing a calculation result of the increment calculating means on the position data of the current cycle in a time-series manner. 4. The encoder data conversion circuit according to claim 1, wherein the final result of said superimposing means in the current cycle is the same as the position data after one cycle.