JPH01223310A - Position detector - Google Patents

Abstract

PURPOSE:To generate not only absolute position data with time resolving power closer than the cycle of sampling timing but also an incremental pulse of high resolving power, by providing an absolute position detection means and an interpolation means. CONSTITUTION:When it is supposed that absolute position data is detected by an absolute position detection means 10, absolute position data after interpolation is densely generated by the estimate interpolation in an interpolation circuit 22 and an incremental pulse can be obtained on the basis of the output of the circuit 22. Further, one cycle of the first sampling timing is divided into interpolation steps by the processing of an interpolation data generation circuit 25 to be successively outputted as position interpolation data D at every interpolation step. This data D is added to the position data from a latch circuit 21 in an operator 26 to be outputted as interpolated absolute position data. Further, an incremental pulse can be formed corresponding to each of the interpolation steps on the basis of the output of the circuit 22 by an incremental data generating circuit 29. Therefore, a problem of pulse omission or the like is not generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a position detection device that can generate absolute position data densely by interpolation, and further relates to a position detection device that can generate incremental pulses densely based on such interpolation. The present invention relates to a position detection device that can be used to detect a position.

[Conventional technology]

In a phase shift type position detection device as shown in Japanese Patent Application Laid-Open No. 57-70406, for example, as shown in FIG.
Next AC signal sin ωt (77 Secondary output signal su obtained by shifting the electrical phase angle by an angle θ according to the position of the detection target)
n (ωt+θ), and data θ1°θ2 .of the phase shift amount θ in this secondary output signal. θ1. ... is sampled and held every cycle to provide absolute position data of the object to be detected. For example, the phase angle is counted from a predetermined phase angle (for example, O) of the primary AC signal sinωt to a predetermined phase angle (for example, 0) of the secondary output signal sin (ω is 10), and this count value is It is sampled and held (by sampling pulse SP) at every sampling timing synchronized with one cycle of the output signal. In this case, if the object to be detected is stationary at that position, data θ, obtained at each sampling timing.

θ2. θ1. ... does not change and indicates its static position. When the object to be detected is moving, data θ0. θ2. θ,,
... changes as appropriate. However, the minimum time unit of this change is each sampling timing.

The above-mentioned phase shift type position detection device.

Generally, it is an absolute position sensing device and does not generate incremental pulses.

An example of generating incremental pulses using such an absolute position detection device is disclosed in Utility Model Application No. 57-168.
No. 061. There, the top ii! Incremental pulses are generated in synchronization with the sampling pulse SP for each secondary output signal period. By being able to generate incremental pulses using an absolute position detection device in this way, it is possible to enjoy the unique advantages of an absolute position detection device while also applying this position detection device to a control device for incremental pulses. This has the advantage of increasing versatility.

On the other hand, as a conventionally known incremental pulse generating means, there is an optical incremental encoder that optically reads the pulse pattern of a rotary code plate.

[Problem to be solved by the invention]

In the phase shift type position detection device as described above, the minimum time unit of change in absolute position detection data is limited to one period of the sampling pulse SP.
If the moving speed of the object to be detected is fast, the values of the absolute position detection data that are output will be scattered, resulting in a loss of accuracy. In other words, during one period of the sampling pulse SP, no matter how much the object to be detected moves, it cannot be detected, which adversely affects accuracy. In particular, when the output of this position detection device is given to a control device for use, the operating clock on the control device side is completely asynchronous with the sampling timing of the position detection device, so the position data given from the position detection device to the control device is Although it is desirable that the change time resolution of the position data be as fine as possible in order to prevent beats, it is not preferable that the change time resolution of the position data is limited to one cycle of the sampling pulse SP as described above.

In addition, when generating incremental pulses using an absolute position detection device, the above-mentioned Utility Model Application No. 57-1680
The method of generating incremental pulses in synchronization with the sampling pulse SP, as shown in No. 61, is not preferable because the resolution of the incremental pulse is limited to one cycle of the sampling pulse SP. In view of such limitations, Utility Model Application Publication No. 57-168061 sets the condition that the speed of the object to be detected is limited to a predetermined speed or less, but this results in a low speed response. If it were to be applied to a speed higher than the limited speed response, the incremental pulses generated would be lacking, and the number of pulses would not correspond to the amount of displacement.

Furthermore, in the conventionally known optical incremental encoder, the speed response performance is limited due to the limit of pulse generation performance, and the speed response is usually around 50kHz, and even if it can be improved, it can only be increased to around 200kHz. Ta.

The present invention has been made in view of the above points, and is a position detecting device equipped with an absolute position detecting means that samples and outputs a digital value of absolute position data of an object at every predetermined sampling timing. It is an object of the present invention to provide a position detection device that is capable of generating absolute position data with a finer time resolution than that of the present invention, and is also capable of generating incremental pulses with a similarly high resolution.

[Means to solve the problem]

A position detecting device according to the present invention includes an absolute position detecting means for sampling and outputting a digital value of absolute position data of an object at each predetermined sampling timing, and a position detecting means for sampling and outputting a digital value of absolute position data of an object at each predetermined sampling timing, and a position detecting means for sampling and outputting a digital value of absolute position data of an object at each predetermined sampling timing. The apparatus is equipped with interpolation means for interpolating data and densely generating absolute position data.

Further, the position detection device according to the present invention further includes incremental data generation means for forming and outputting incremental pulses based on the output of the interpolation means.

[For production]

By interpolating between position data of different sampling timings by the interpolation means, absolute position data can be generated densely, and absolute position data can be generated with a time resolution finer than the period of the sampling timing. Furthermore, by forming and outputting incremental pulses based on the output of the interpolation means, it is possible to generate high-resolution incremental pulses equivalent to interpolation steps as well as absolute position data. Further, the speed response can be made as high as the interpolation calculation clock allows.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, the absolute position detecting means 10 samples and outputs the digital value of the absolute position data of the object at every predetermined sampling timing, and is, for example, the one shown in the above-mentioned Japanese Patent Laid-Open No. 70406/1983. like,
A plurality of primary coils C1l, 012 and a secondary coil C are separately excited by a plurality of alternating current signals having mutually different phases.
A variable magnetic resistance type position sensor 11 is provided. This position sensor 11 may be of a rotating type or a linear type. The oscillator 12 oscillates a master clock pulse CP of a predetermined frequency (for example, I MHz), which is input to the counter 13 and counted. The output of the counter 13 is input to a sine data generator 14 and a cosine data generator 15 to generate data of a sine function and a cosine function. The data of the sine function and the cosine function are input to digital/analog conversion and drivers 16 and 17, respectively, and the analog sine signal s
in ω and a cosine signal cos ωt are generated.

This sine signal sinω and cosine signal cos(IJt) are input to the primary coils C1l and C12 of the position sensor 11 as reference AC signals for excitation, respectively.
It is assumed that the cycle of the count value 3 corresponds to one cycle of the reference AC signals sinωt and cosωt for excitation. That is, the count value of the counter 13 is all “O”.
” to all 111 II, one cycle of the reference AC signal sinωt occurs.

In the position sensor 11, the magnetic resistance corresponding to each of the primary coils C1l and C12 changes according to the position of the object to be detected, and the output signal Y=K is phase-modulated according to this position.
sin (ω is - θ) is output from the secondary coil C2. Phase difference θ in this output signal Y with respect to the primary AC signal
corresponds to the position of the object to be detected, and this phase difference θ
By measuring the position of the object, absolute position data of the object to be detected can be obtained. Therefore, the output signal Y of the position sensor 11 is input to the zero cross comparator 19 via the amplifier and filter 18, and the zero cross phase, that is, the phase angle O is detected. A signal generated corresponding to the detection timing of the phase angle O of this output signal Y is applied as a sampling pulse SP to the latch control input of the latch circuit 21 via the delay circuit 20. The delay circuit 20 is for producing a sampling pulse SP' having a slight delay with respect to the sampling pulse SP. In response to this sampling pulse SP', the latch circuit 21 controls the counter 13.
Latch the output count value data. In this way, the measurement data Dθ of the phase difference θ corresponding to the current position of the position detection object is latched in the latch circuit 21. In other words,
The output of this latch circuit 21 is current absolute position data of the position detection target. However, the minimum unit of change timing of the absolute position data output from the latch circuit 21 is the timing of the sampling pulse SP, that is, the time of one cycle of the output signal Y of the position sensor 11. The explanation up to this point is the same as the example of the timing chart in FIG.

The interpolation circuit 22 interpolates between the position data of different sampling timings output from the latch circuit 21, and generates absolute position data densely. The storage circuit 23 receives the output of the latch circuit 21 and stores data N sampling timings before the data currently output from the latch circuit 21. Sampling pulse S output from zero cross comparator 19
P is input as an acquisition control signal to the storage circuit 23.

The memory circuit 23 is constituted by a latch or a shift 1 register, and takes in data for N sampling timings in response to a sampling pulse SP. For example, N=
If it is 1, the storage circuit 23 may be configured by a simple latch. Sampling pulse sP' from delay circuit 20
In order to take in the position data previously stored in the latch circuit 21 immediately before taking in the position data at a new sampling timing into the latch circuit 21, the timing of the sampling pulse SP is slightly ahead of SP'. There is.

Position data A at the current sampling timing output from the latch circuit 21 and N output from the storage circuit 23
The position data B before the sampling timing is calculated by the computing unit 2.
4, and the calculation AB=C is performed. As a result, the difference C between the position data B N sampling timings ago and the position data A at the current sampling timing is determined. The data of this difference C is generated by the interpolation data generation circuit 25.
given to. In the interpolation data generation circuit 25, this difference C
Based on the data, position interpolation data D is generated for each interpolation step in one period of sampling timing. This position interpolation data D for each interpolation step is given to the arithmetic unit 26 and added to the position data A at the current sampling timing given from the latch circuit 21. That is, this position interpolation data D is used as predicted change value data for each interpolation step from the current sampling timing to the next sampling timing. In this way, absolute position data E (E=A+D) obtained by interpolating position data from the current sampling timing to the next sampling timing is densely outputted from the calculator 26 at each interpolation step.

Interpolated absolute position data E output from the calculator 26
is input to the latch circuit 27. On the other hand, the interpolation data generation circuit 25 generates a clock selection signal C8L according to the number of interpolation steps in one period of sampling timing, and applies it to the clock gate 28. clock gate 28
Then, the signal of the bit selected by the clock selection signal C8L among the respective bits of the count value data output from the counter 13 is selectively outputted as the clock pulse CLK. The clock pulse CLK selectively output from this clock gate 28 corresponds to the timing of each interpolation step. The latch circuit 27 is latch-controlled by the clock pulse CLK selectively output from the clock gate 28.
Interpolated absolute position data E for each interpolation step is latched in synchronization with K.

The multi-bit output signal of the latch circuit 27 is output as absolute position data that is densely generated by interpolation.

Further, the clock pulse CLK corresponding to the timing of each interpolation step is also given to the incremental data generation circuit 29. The incremental data generation circuit 29 generates incremental pulses based on this clock pulse CLK and, if necessary, the count output of the counter 13 and the in signal SB indicating the direction of movement of the object to be detected. Incremental data generation circuit 2
9, for example, outputs a divided output obtained by dividing the clock pulse CLK by 1/2 as an A-phase incremental pulse, and also forms a pulse delayed by 90 degrees and outputs this as a B-phase incremental pulse. Also, the origin is detected from the value of the absolute position data, and based on this, an origin pulse is formed and output. In addition, latch circuit 2
It is also possible to input the absolute position data output from 7 to the incremental data generation circuit 29 and generate incremental pulses based on this (for example, the data of the least significant bit LSB of the absolute position data may be used as the incremental pulse). (and so on).

With the above configuration, 1. For example, if absolute position data is detected by the absolute position detection means 10 at each sampling timing having a period of 100 μs as shown in FIG. , as shown in FIG. 2(b), interpolated absolute position data is generated densely. Based on the output of this interpolation circuit 22, incremental pulses as shown in FIG. 2(c) can be obtained. In this example, N=
1, data that is one sampling timing before the data output from the latch circuit 21 is output from the storage circuit 23. When the position data "5" at the first sampling timing is latched by the latch circuit 21, the data output from the storage circuit 23 is "0", and the output C of the arithmetic unit 24 is "5". By the processing of the interpolation data generation circuit 25 corresponding to this, one period of the first sampling timing is divided into five interpolation steps, and the position interpolation data D for each interpolation step is rOJ, r
"l", "r2", "r3", and "r4" are sequentially output. This position interpolation data D is sent to the latch circuit 21 in the arithmetic unit 26.
It is added to the position data "5" from , and "5", "6", "
7'', ``8'', and ``9'' are sequentially output. The same process as described above is performed at the next sampling timing as well.

As a result, interpolated absolute position data is generated densely as shown in FIG. 2(b). Further, based on the output of the interpolation circuit 22 (clock pulse CLK or interpolated absolute position data), an incremental pulse as shown in FIG. 2(c) can be generated in the incremental data generation circuit 29 corresponding to the interpolation step. can. In this way, incremental pulses can be generated with the same precision as the resolution of the interpolated absolute position data.

Even if the object to be detected moves at high speed, problems such as pulse extraction do not occur.

Next, a third detailed example of the interpolation data generation circuit 25 will be explained.
This will be explained with reference to the figures.

In the interpolation data generation circuit 25 shown in the embodiment of FIG. 3, the output signal of each bit of the counter 13 (FIG. 1) is treated as a clock pulse, and a clock selection signal is used to select one clock pulse. C8L is generated according to the number of interpolation steps in one period of sampling timing, and the clock pulse CLK is selected by the clock gate 28 according to this clock selection signal C8L.
is input, and position interpolation data D is generated based on this clock pulse CLK. In this case, the number of interpolation steps is determined by the data of the difference C given from the calculator 24 (FIG. 1). Ideally, it is preferable to divide one cycle of the sampling timing into a number equal to the difference C at approximately equal intervals, and to set a number of interpolation steps corresponding to the difference C. However, since the clock pulse that sets the interpolation step is the output signal of the counter 13 in FIG. It ends up. Therefore, in the interpolation data generation circuit 25 of FIG. 3, the difference C output from the arithmetic unit 24 is
The clock pulse CLK is selected by generating a clock selection signal C8L (more specifically, one of C3LI or C:SL2) according to the rounded value of 2n, and fraction k (however = C
-2'') is carried over to the difference C at the next sampling timing.

In FIG. 3, the data of the difference C output from the arithmetic unit 24 is input to the register 31 via the adder 30,
It is input to selection signal generation logic 32 and 33. The count output of the counter 34 is applied to the other input of the adder 30, which is initially assumed to be "0". Therefore, the value corresponding to the difference C is initially loaded into the register 31. Note that the sampling pulse SP' is input to the acquisition control input of the register 31 by the arithmetic unit 24.
The sampling pulse SP is slightly delayed by the calculation time of
″′ is input.

The selection signal generation logic 32.33 rounds the data corresponding to the difference C output from the register 31 to a value of 20, and generates a clock selection signal C3LI or C3L2 according to the rounded value of 2n.

Note that the difference C between the position data B before N sampling timings and the position data A at the current sampling timing is C=
Since the position data obtained from the absolute position detection means 10 is absolute position data, A-B has a positive or negative sign depending on the direction of movement of the object to be detected (in the case of a rotating shaft, the direction of rotation). .

Therefore, the data of the difference C given from the arithmetic unit 24 is accompanied by a sign signal (sign bit) SB.

For example, when the sign signal SB is II OII, it indicates movement in the positive direction, and '1' indicates movement in the negative direction.Also, when the sign signal SB is '1', indicating movement in the negative direction, The data for the difference C is negative, and 29 is expressed in two's complement.

The selection signal generation logic 32 for the positive direction generates a sign signal S.
It is enabled when B is 0", detects the most significant "1" bit of the data given from the register 31, and generates the clock selection signal C3LI accordingly. For example, if the data given from the register 31 is ”OOOOOO11
0'', a clock selection signal C3LI is generated corresponding to the third bit from the bottom, that is, the bit with a weight of 22.

The negative direction selection signal generation logic 33 generates a sine signal S.
It is enabled when B is "1", detects the most significant "0" bit of the data provided from the register 31, and generates the clock selection signal C3L2 in response. for example,
The data given from register 31 is "111100"
10'', the clock selection signal C3L2 is generated corresponding to the fourth bit from the bottom, that is, the bit with a weight of 23.

In this way, the selection signal generation logic 32 and 33 round the data of the difference C in the register 31 to a value of 2n, and the rounded 2n
Clock selection signal C3LI or C3L2 depending on the value of
occurs.

The clock gate 28 (FIG. 1) selects the output bit of the counter 13 according to the weight of the applied clock selection signal C3LI or C3L2 as shown in Table 1 below, and outputs it as a clock pulse CLK.

Here, an example of the clock cycle for each output bit of the counter 13 will be shown. The period of the data of the most significant bit of the counter 13 is the excitation reference AC signal sinωt, c
This corresponds to one period of osωt, and is assumed to be 100 μs, for example. Assuming that the counter 13 is an 8-bit binary counter, the period of the output clock pulse for each bit is as shown in Table 1 below.

Note that one period of the sampling timing is 100 μs, which is almost the same as one period of the reference AC signal for excitation (in practice, when the object to be detected is moving, the output of the position sensor 11 is changed depending on the speed and direction of the object to be detected. (The frequency of the signal Y deviates somewhat in the positive or negative direction from the frequency of the excitation signal).

Table 1 For example, as mentioned above, the value of the data in register 31 is 10.
Suppose that the clock selection signal C3LI is generated in response to the bit with a weight of 22 in "r6" in decimal ("00000110" in binary), then according to Table 1, the period of 25 μs starts from the bit with a weight of 25 of the counter 13. clock pulse CL
K is selected. This is 1 of the sampling timing.
This means that four pulses are generated in a period (100 μs), and therefore, one period of sampling timing is divided into four interpolation steps by this clock pulse CLK. In other words, the data "6" of the difference C in the register 31 is rounded to 22=4, and the number of interpolation steps corresponding to the rounded "4" is set.

Further, as described above, the data value of the register 31 is lO
decimal r-14J (binary complement “11110010”
), and the clock selection signal C3L2 is generated corresponding to the bit with a weight of 23, the clock pulse CLK with a period of 6.25 μs is selected from the bit with a weight of 23 of the counter 13 according to Table 1. This means that 16 pulses are generated in one period of sampling timing = 100 μS, and therefore, one period of sampling timing is divided into 16 interpolation steps by this clock pulse CLK.

In other words, the data r-14J of the difference C in the register 31 is rounded to 12'=-16, and the number of interpolated Stella 1 corresponding to the rounded "16" is set.

The up/down counter 35 inputs the clock pulse CLK selected by the clock gate 28 to the count input GK, and inputs a signal obtained by inverting the sign signal SB to the up/down control human power U/D. When the sign signal SB is 0'', that is, when the direction of movement of the object to be detected is the positive direction, the up mode is activated and the clock pulse CLK is counted up.When the sign signal SB is 1'', that is, the direction of movement of the object to be detected is When it is in the negative direction, it becomes a down mode and counts down the clock pulse CLK. Moreover, this up/down counter 35 is operated by the sampling pulse s
p" is reset at the beginning of one cycle of the sampling timing. The count content of this up/down counter 35 is output as position interpolation data D. In the case of direction, it is a negative value consisting of two's complement.

For example, appropriate delay processing is performed so that the start of one cycle of the clock pulse CLK is synchronized with the sampling pulse sp", and from the time when it is reset by the sampling pulse Sp j l, approximately one cycle of the clock pulse CLK
If the count value is held at "0" during the cycle, rOJ is used as position interpolation data D in the first interpolation step.
can be given, which is convenient for interpolation calculation processing.

The up/down counter 34 inputs the clock pulse CLK selected by the clock gate 28 to the count input GK, and inputs the sign signal SB to the up/down control manually U/
D, the sampling pulse s p" is input to the preset control input PR, and the output of the register 31 is input to the preset data input. It is assumed that there is no time delay between the input and output of the register 31, and the sampling pulse s p
It is assumed that when data is taken into the register 31 by ``, the data is preset into the counter 34 at the same time.The up/down counter 34 is
Conversely, when the sign signal SB is 410 II, that is, when the direction of motion of the object to be detected is in the positive direction, the down mode is entered, and the clock pulse CLK is counted down from the preset value. When the sign signal SB is 141 It, that is, when the direction of motion of the object to be detected is in the negative direction, the up mode is entered, and the clock pulse CLK is counted up from the preset value. The count contents of this counter 34 are given to an adder 30 and added to the difference C data given from the arithmetic unit 24 (FIG. 1), and the addition result is stored in the register 31.

This up/down counter 34 is for finding the fraction k (however, = C-2") generated by the above-mentioned rounding. The data for the fraction output from this counter 34 is given to the adder 30. The fraction k is carried forward by adding it to the data of the difference C at the next sampling timing.By carrying over the fraction k, errors due to rounding are removed.

FIG. 4 shows an example of input/output signals of each circuit in relation to the circuits of FIGS. 1 and 3. For example, the absolute position detection means 10
Assume that the absolute position data Dθ outputted from the sensor changes at each sampling timing as shown in FIG. 4(a).

The difference C output from the arithmetic unit 24 is as shown in FIG. 4(b), the contents of the register 31 in FIG. 3 are as shown in FIG. 4(c), and FIG. 4(d) is the register. 31 contents 2
This is the value rounded by r'. FIG. 4(e) shows the fraction generated by the rounding, that is, the output of the counter 34 in FIG. 3 at the end of one cycle of the sampling timing. FIG. 4(f) is an example of the clock pulse CLK selected according to Table 1 using the rounded value 2n, that is, the clock selection signal C8L.

FIG. 4(g) is an example of the output of the counter 35 in response to this clock pulse CLK, that is, the position interpolation data D.

FIG. 4(h) is an example of the value obtained by adding this position interpolation data D to the current absolute position data Dθ, that is, the interpolated absolute position data output from the latch circuit 27 (FIG. 1). FIG. 4(i) is an example of an incremental pulse output from the incremental data generation circuit 29 (FIG. 1) in response to the clock pulse CLK.

In FIG. 4<i), 1 is also written with the cumulative number of incremental pulses. Comparing this with FIG. 4(h), the cumulative number of incremental pulses lags behind the value of the interpolated absolute position data by approximately one cycle of the sampling timing. In order to eliminate such a delay, appropriate processing such as adding the value obtained by subtracting the cumulative value of the incremental pulses from the current absolute position data Dθ to the difference C and performing the above-mentioned interpolation processing may be performed. In addition, the manner in which the incremental pulses are generated can be changed to a certain degree based on the design.

In the interpolation data generation circuit 25 shown in FIG.
The value of the difference C is rounded in accordance with the output clock frequency of 3, thereby omitting the branch calculation for setting the interpolation step and simplifying the circuit configuration. On the other hand,
There will be a delay due to the carryover of fractions. In another detailed example of the interpolation data generation circuit 25 shown in FIG.
By dividing one cycle of the sampling timing at approximately equal intervals by the difference C and setting a number of interpolation steps corresponding to the difference C, the carryover to fractions as described above is eliminated.

In FIG. 5, the division value memory 36 stores in advance division value data for dividing one period of the sampling timing at approximately equal intervals for each possible value of the difference C. The frequency division value memory 36 stores frequency division value data that takes into account not only the absolute value of the difference C but also its sign signal SB. For example, the frequency division value data corresponding to 1'1'' of the sine signal SB, that is, when moving in the negative direction, is expressed in two's complement. The sine signal SB is stored in the frequency division value memory 36.
is input to the memory 36, and the corresponding frequency division value data is input to the memory 36.
is read from. This frequency division value data is applied to a preset data input of a preset type up/down counter 37.

At the preset control input of this counter 37, a sampling pulse SP''' obtained by slightly delaying the sampling pulse SP' by the calculation time of the arithmetic unit 24 and the readout time of the memory 36 and the frequency-divided output of the counter 37 are input. The clock pulse CPL extracted from the least significant bit LSB of the counter 13 in FIG. 1 is applied to the count input of the counter 37.

In addition, a sign signal SB is input to the up/down control human power U/D of the up/down counter 37, and when the sign signal SB is "0", that is, when the direction of motion of the detection object is in the positive direction, the down mode is activated. , the clock pulse CPL is counted down from the preset value. When the sign signal SB is "1", that is, when the direction of motion of the object to be detected is in the negative direction, the up mode is entered, and the clock pulse CPL is counted up from the preset value.

The counter 37 presets the frequency division value data from the memory 36 by the sampling pulse sp'' at the beginning of one cycle of sampling timing, and thereafter uses the clock pulse CPL.
count down or up. When the clock pulse CPL is counted down or up by the number of preset frequency division values, the count value becomes "0" and one frequency division output pulse is output. This frequency division output pulse presets the frequency division value data again, and the clock pulse CPL
Continue counting. The generation time interval of the frequency-divided output pulses of this counter 37 corresponds to the time interval of one interpolation step.

The frequency-divided output pulses of counter 37 are applied to the count input of up/down counter 39. A sine signal S is input to the up/down control input of the up/down counter 39.
An inverted signal of B is input, and when it is 110'', that is, in the positive direction, it instructs to count up, and when it is '1'', that is, in the negative direction, it instructs to count down. The up/down counter 39 is also given the sampling pulse sp'' to its reset control input.The up/down counter 39 is reset by the sampling pulse sp'' at the beginning of one sampling period, and the counter 37 Count up or down the divided output pulses. When the sign signal SB is "O", that is, when it is in the positive direction, up-counting is performed, and the count value is increased by 1 at every interpolation step. When the sign signal SB is "1", that is, when it is in the negative direction, down counting is performed, and the count value is decreased by 1 at every interpolation step. The output of this up/down counter 39 is given to the arithmetic unit 26 (FIG. 1) as the position interpolation data D mentioned above. In the arithmetic unit 26, the count value of the up/down counter 39 is treated as complement data, and the count value when counting down becomes a negative value. Note that, as described above, in order to be able to give "0" as the position interpolation data D in the first interpolation step, the counter 37 is
The count value is held at rOJ for approximately one cycle of the output pulse.

An example of how to determine the frequency division value data to be stored in the frequency division value memory 36 is as follows: - For boat fishing, one period of sampling timing is T, the number of interpolation steps is C (that is, the difference C), and 1
The time of the interpolation step is t.

Let d be one period of the clock pulse CPL for frequency division, and F be the frequency division value.

T/C=t, t/d=F It can be determined according to the relational expression:

Furthermore, to give a specific example, the reference AC signal sin for excitation
(1) t, cos (one period of 11t is 100
ps, and assuming that one cycle of sampling timing is approximately the same as this, T=100 μs. Furthermore, assuming that the counter 13 in FIG. 1 is an 8-bit binary counter, the period of the data of its most significant bit corresponds to 100 μs of the excitation reference AC signal, and the clock pulse CPL extracted from its least significant bit LSB corresponds to 100 μs of the excitation reference AC signal. One period is 0.78125 ps. Therefore, T=10
0 μs, d = 0.78125 μs, execute the above calculation formula corresponding to various values of C (1, 2, 3, 4, 5, 6,...), and calculate various values of C. The frequency division value data corresponding to is determined and stored in the memory 36. In that case, instead of using the result F of the above equation as the frequency division value data, it is preferable to determine an integer value that is somewhat smaller than the actual calculation result F after a calculation time delay as the division value data.

The branch value data is determined taking into consideration the moving direction, that is, the sign signal SB.

For example, if C=3, - the above formula is T/C=+100/3=33.3...=tt/d
=33.3...10.78125 =42.66・
...=F, but the frequency division value is set to, for example, r41 in the case of movement in the positive direction (when the sine signal SB of the difference C is 10'').

The frequency-divided output pulse of the counter 37 indicates the timing of the interpolation step, and is also applied to the incremental data generation circuit 29 (FIG. 1), which generates incremental pulses based on this.

In the above embodiment, the predetermined frequency division value data is stored in the memory 36, but this may also be determined by calculation using dedicated hardware or software.

In each of the above embodiments, the interpolation calculation involves adding position interpolation data D obtained based on the difference in absolute position between N sampling timings before and the current sampling timing to the absolute position data at the current sampling timing as predicted change value data. Although the prediction interpolation is not limited to this, N
Position interpolation data D obtained based on the difference in absolute position between the previous sampling timing and the current sampling timing
Actual interpolation may be used in which the actual interpolation data is added to the absolute position data N sampling timings ago. In that case, for example, in the adder 26 in FIG.
What is necessary is to add absolute position data B and position interpolation data D output N sampling timings ago. Further, the configuration of the interpolation calculation in the interpolation circuit 22 may be changed as appropriate according to the general actual interpolation calculation.

Further, in each of the above embodiments, the time interval of the interpolation step is arbitrary for each sampling timing, but the interpolation calculation process may be performed at a constant interpolation time interval. In that case, the incremental pulse is generated not at each interpolation step timing but at each interpolation data change timing.

〔Effect of the invention〕

As explained above, according to the present invention, in a position detection device equipped with an absolute position detection means that samples and outputs a digital value of absolute position data of an object at every predetermined sampling timing, It has the excellent effect of being able to generate absolute position data with a fine time resolution and also generating incremental pulses with a similarly high resolution. Further, the speed response can be made as high as the interpolation calculation clock allows.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a position detection device according to the present invention, FIG. 2 is a timing chart showing an example of interpolation operation and incremental pulse generation in the same embodiment, and FIG. 3 is an example of interpolation in FIG. 1. 4 is a timing chart showing an example of the operation of FIG. 3; FIG. 5 is a block diagram showing another detailed example of the interpolation data generating circuit in FIG. 1; FIG. 6 is a timing chart showing an example of the detection operation of the phase shift type absolute position detection device. 10... Absolute position detection means, 11... Position sensor,
12... Clock oscillator, 13... Counter, 21
゜27...Latch circuit, 22...Interpolation circuit, 23.
...Memory circuit, 24.26... Arithmetic unit, 25 River interpolation data generation circuit, 28... Clock gate, 29...
Incremental data generation circuit.

Claims (2)

[Claims] (1) Absolute position detection means that samples and outputs the digital value of the absolute position data of the object at each predetermined sampling timing, and interpolates the position data between different sampling timings output from this absolute position detection means, and A position detection device comprising interpolation means for densely generating position data. (2) The interpolation means includes means for determining the number of interpolation steps according to the difference between position data before N sampling timings and position data at the current sampling timing, and means for determining the number of interpolation steps according to the determined number of interpolation steps. means for setting the timing of the interpolation, means for generating position interpolation data for each set interpolation step, and calculating the position interpolation data for the absolute position data output from the absolute position detection means, 2. The position detection device according to claim 1, further comprising means for outputting absolute position data for each interpolation step. (3) Absolute position detection means that samples and outputs the digital value of the absolute position data of the object at each predetermined sampling timing, and interpolates the position data between different sampling timings output from this absolute position detection means, and A position detection device comprising: interpolation means for densely generating position data; and incremental data generation means for forming and outputting incremental pulses based on the output of the interpolation means.