JP3439814B2 - Digital PLL device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to the detection target rotation angle speed
Digital phase locked loop (digital PL) for detecting displacement speed and phase of position
L) relates to the device.

[0002]

2. Description of the Related Art A phase locked loop (hereinafter referred to as PLL) device for detecting a rotation angle or displacement of a detection target with high accuracy is known. This device detects an angle or displacement by a magnetic or optical sensor, obtains a sine signal (sin θ signal) and a cosine signal (cos θ signal) having a phase difference of 90 ° from each other, and obtains these signals and a certain signal. Output value from the function generator for the reference phase ψ (sine value sin
ψ and the cosine value cos ψ) and the phase θ of the detection target
Between the reference phase ψ and the reference phase ψ, and the difference (θ−ψ) is repeatedly calculated while increasing or decreasing the reference phase ψ.
-Ψ) is converged to 0.

FIG. 2 is a circuit diagram of a conventional analog PLL device. In this figure, φ _A and φ _B are a sine signal (sin θ) and a cosine signal (cos θ) indicating the angle or displacement of the object to be detected, and these are output by a magnetic resistance (MR) type sensor or an optical sensor. In FIG. 2, reference numeral 10 is a function generator composed of a ROM, and a reference phase ψ which is an output of a counter 26 described later is used as address data, and a sine value sin ψ corresponding to the address data is used.
And the cosine value cos ψ are output.

These sine value sin ψ and cosine value cos
ψ is converted into an analog value by the D / A converters 12 and 14, respectively, and then input to the first and second multipliers 16 and 18. The multiplier 16 calculates the cosine signal cos θ and the sine value sin.
The product of ψ and cos θ · sin ψ is obtained. The multiplier 18 calculates the product of the sine signal sin θ and the cosine value cos ψ sin θ ·
Find cos ψ.

The difference between these products is obtained by the subtracter 20. This difference is (sin θcos ψ-cos θsin)
ψ) = sin (θ−ψ), and if θ≈ψ, then si
Since it can be approximated by n (θ−ψ) ≈ (θ−ψ), the output of the subtractor 20 eventually becomes the phase difference (θ−ψ).

This phase difference (θ-ψ) is PID controlled (proportional / integral / derivative control) in the PID circuit 22 and output as the displacement velocity of the detection target, that is, the angular velocity ω. The angular velocity ω is also input to the voltage controlled oscillator (VCO) 24. This VCO 24 is the magnitude of the angular velocity ω (absolute value)
Up / down counter 2 for pulse of frequency corresponding to and up / down signal corresponding to positive / negative of angular velocity ω
Send to 6.

This counter 26 is V when the angular velocity ω is positive.
The output pulse of the CO 24 is up-counted, and conversely, when the angular velocity ω is negative, the output pulse of the VCO 24 is down-counted. The output ψ of the counter 26 is supplied to the function generator 10, and the function generator 10 generates a sine value sin ψ and a cosine value cos ψ with the output ψ as address data, and repeats the above operation.

Thus, as ψ approaches θ, the VCO
Since the frequency of the pulse output from 24 becomes small, the reference phase ψ eventually coincides with the current phase θ to be detected. That is, the function generator 10, the multipliers 16 and 18, the subtractor 20, and P
Phase with ID22, VCO24, counter 26
A locked loop is constructed.

Although this embodiment is constructed by an analog circuit, it is of course possible to construct it by a digital circuit. FIG. 3 is a circuit diagram of an example thereof. The analog sine signal sin θ and the analog cosine signal cos θ are the first and second signals.
Are converted into digital signals by the A / D converters 12A and 14A and input to the multipliers 16A and 18A. Function generator 1
0A is a sine value sin using the reference phase ψ as address data.
When ψ and the cosine value cos ψ are output, the multipliers 16A, 18
The phase difference (θ−ψ) is calculated by A and the subtractor 20A.

The sign of the phase difference (θ-ψ) is the comparator 24.
As determined by A, the up / down counter 26A adds or subtracts the clock pulse CL having a constant frequency. That is, when the phase difference (θ−ψ) is negative, it counts up, and when it is positive, it counts down. Then, by repeating the above operation, the counter 26A counts and the phase difference (θ−ψ) converges to zero.

[0011]

As described above, the conventional PLL device counts the pulses by using the up / down counters 26 and 26A. That is, in the device of FIG.
, And the device of FIG. 3 was counting clock pulses CL.

If the pulses are counted one by one in this way, it takes a long time to perform the addition, and the number of repetitive operations required until the phase difference (θ-ψ) converges to 0 also increases. For this reason, there is a problem that the followability to the high-speed operation of the detection target becomes poor. Further, in the case of the digital PLL, it is necessary to use a high-speed clock pulse CL and a high-speed LSI in order to improve the followability, and there is also a problem that the circuit becomes complicated and expensive.

Further, in the conventional PLL device described above,
Position detection of the encoder output within one cycle, that is, interpolation division is possible, but it is necessary to separately provide a counter for multiple cycles for movement / rotation over multiple cycles. For example, it was necessary to shape the output signal of the sensor, discriminate the direction, and add / subtract the up / down counter. Therefore, there is a problem that the circuit becomes complicated.

[0014]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a digital PLL capable of using an inexpensive computer (microcomputer or the like) having a significantly improved high-speed followability and a relatively low calculation speed. The purpose is to provide a device.

Another object of the present invention is to provide a digital PLL device capable of detecting the amount of movement / rotation with a relatively simple structure even when the encoder output signal is moved / rotated over multiple cycles.

[0016]

According to the present invention, the above object is to detect the displacement velocity and phase of the object to be detected from the output signal of the encoder which outputs the analog sine signal and the analog cosine signal corresponding to the displacement of the object to be detected. Digital PLL
An apparatus; first and second A / D converters for converting the sine signal and the cosine signal into digital signals at a predetermined sampling period; and a function generator for storing sine and cosine values for a predetermined reference phase First calculating the product of the sine signal and the cosine value obtained from the function generator
A second multiplier for obtaining a product of the cosine signal and a sine value obtained from the function generator; and a subtractor for obtaining a difference between outputs of the first and second multipliers; A cycle adder for obtaining a current reference phase by adding the output of the subtractor and a reference phase of one sampling period before; a current reference phase output from the adder is delayed by one sampling period and input to the adder. A first delay element for supplying the reference phase delayed by one sampling period as the address data to the function generator, the function generator, the first and second multipliers, the subtractor, the adder, one of the first <br/> delay element to form a phase locked loop, the displacement speed of the detected output of said subtractor
However, this is independent of the phase locked loop
The cumulative number of times calculated by the circuit
This is achieved by a digital PLL device characterized in that the turning angle is the current phase to be detected .

The other purpose is to obtain the cumulative rotation angle.
For this purpose, an upper adder that obtains the current phase of the detection target by the sum of the output of the subtractor and the phase of the detection target that is one sampling period before, and the current phase output by this upper adder for one sampling period This can be achieved by providing a second delay element which is delayed and input to the upper adder.

In this case, it is desirable that the upper adder has a data length corresponding to the entire movement range of the detection target and can be reset at any position.

[0019]

FIG. 1 is a circuit diagram of an embodiment of the present invention. In this figure, a function generator 10A and an A / D converter 12
A, 14A, first and second multipliers 16A, 18A,
Subtractor 20A is the same as that shown in FIG. 3, and therefore description thereof will not be repeated. In FIG. 1, the current phase to be detected is θ _K , the reference phase is ψ _K , and the reference phase one sampling period before is ψ _K−1 .

In FIG. 1, reference numeral 30 is a periodic adder, and 32 is a first delay element. The period adder 30 sets 360 degrees to 1
The output of the subtractor 20A and the output of the delay element 32 are input to the cycle, and the sum of these is obtained by the adder 30. Here, the output of the subtractor 20A is (sin θ _K · cos ψ _{K −1} −cos θ _K · sin
ψ _K-1 ) = sin (θ _K −ψ _K-1 ) ≈ (θ _K −ψ _K-1 ).
Becomes

The output of the delay element 32 becomes ψ _{K-1 and the} adder 30 outputs {(θ _K −ψ _K-1 ) + ψ _K-1 } = θ _K as a new reference phase ψ _K. This new reference phase ψ _K is temporarily stored in the first delay element 32 and is output with a delay of one sampling period. That is, when the adder 30 calculates θ _K (= ψ _K ) as described above, the delay element 32 outputs the reference phase ψ _K−1 one sampling period before.

As described above, according to this embodiment, since the addition operation is performed in the periodic adder 30, extremely high-speed processing is possible. That is, the up / down described in FIGS.
In the case of using the down counters 26 and 26A, the operation is very slow because the pulses are added and subtracted one by one, but according to the embodiment of FIG. 1, each digit of the adder 30 is added and subtracted simultaneously. Because you can.

The reference values i.e. sinψ _K-1 and the reference phase [psi _K-1 the address data, cos _K-1 is determined by the function generator 10A, the multiplier 16A, 18A, subtractors 20A, periodic adder 30 , The operation along the phase locked loop consisting of the first delay element 32 is repeated.
As a result, the reference phase ψ _K-1 quickly follows the current phase θ _K.

The output of the subtractor 20A is sin (θ _K −
_{ψ K-1) ≒ (θ} K -ψ K-1) in [psi _K-1 phase theta
_Since it follows _K-1, it is considered that ψ _K-1 = θ _K-1 . Therefore, (θ _K −ψ _K−1 ) = (θ _K −θ _K−1 ) = Δθ _K can be considered as the angular velocity ω _K.

In FIG. 1, 34 is a high-order adder, and 36 is a second delay element. The upper adder 34 outputs the angular velocity ω _K = (θ _K −ψ _K−1 ) = (θ _K −θ which is the output of the subtractor 20A.
_K-1 ) = Δθ _K and the output θ _K-1 of the second delay element 36 are added to output θ _K. The adder 34 is reset by the reset signal at the external reference position, the reset time is set to k = 0, and the addition is repeated for n sampling cycles until k = n. As a result, the cumulative rotation angle θ _n = ΣΔθ _K can be obtained.

Here, θ _K includes an error because it is obtained approximately, but since a loop is formed by the second delay element 36, this error does not accumulate and θ _K is highly accurate.
_n can be detected. By resetting, the absolute amount of movement / rotation from the reference position can be detected.

[0027]

As described above, according to the invention of claim ₁ , the difference θ _K −ψ _K-1 between the current phase θ _K and the reference phase ψ _K-1 and the output ψ of the first delay element (32). The sum θ _K with _K-1 is obtained by the periodic adder (30), and the output θ _K of this adder (30) is input to the first delay element (32) as the reference phase ψ _K. The reference phases ψ _K and ψ _K-1 can be obtained at extremely high speed.

Therefore, the high speed followability is improved. Also, an inexpensive microcomputer with a relatively low calculation speed can be used. In particular, if the signal processing is performed by a microcomputer, these processing can be performed as a part of the input signal processing, and the software can be configured without adding special hardware. For this reason, it is possible to detect the displacement speed with high accuracy , and
It is possible to inexpensively provide a high-resolution position detection device that can perform angle interpolation division.

According to the second aspect of the invention, the amount of change in position / angle can be obtained with high accuracy. In particular, if the upper adder (34) can be reset, the absolute displacement amount from an arbitrary reference position can be accurately detected.
(Claim 3).

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional device.

FIG. 3 is a circuit diagram of a conventional device.

[Explanation of symbols]

10, 10A function generator 12A, 14A A / D converter 16A First multiplier 18A Second multiplier 20A subtractor 30 period adder 32 First delay element 34 High-order adder 36 Second delay factor

Claims (3)

(57) [Claims] 1. A digital PLL device for detecting the displacement speed and phase of the detection target from an output signal of an encoder that outputs an analog sine signal and an analog cosine signal corresponding to the displacement of the detection target; First and second A / D converters for converting a cosine signal into a digital signal at a predetermined sampling period; a function generator for storing a sine value and a cosine value for a predetermined reference phase; the sine signal and function generation thereof A first multiplier for obtaining a product of a cosine value obtained from a generator; a second multiplier for obtaining a product of the cosine signal and a sine value obtained from the function generator; and the first and second A subtractor for obtaining the difference between the outputs of the multipliers; A first delay element for delaying the current reference phase output from the adder by one sampling cycle and inputting it to the adder, and supplying the reference phase delayed by one sampling cycle as the address data to the function generator. wherein the function generator, the first and second multipliers, a subtractor, an adder, by a first delay element to form a phase locked loop, the output of the subtractor and the displacement speed of the detection object On the other hand, is this the Phase Locked Loop?
It is calculated by adding a circuit independent of each sampling cycle.
A digital PLL device, wherein the accumulated rotation angle is set as a current phase of a detection target . 2. The phase locked device according to claim 1.
A circuit independent of the loop, an upper adder for obtaining the current phase of the detection target by the sum of the output of the subtracter and the phase of the detection target one sampling period before, and the output of this upper addition unit for one sampling period A digital PLL having a second delay element delayed by a minute and input to the upper adder.
apparatus. 3. The digital PLL device according to claim 2, wherein the higher-order adder has a data length corresponding to the entire moving range of the detection target and can be reset at an arbitrary position.