JPH1144555A - Data conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an output pulse from fluctuating by a method wherein encoder data calculates previous differential data as current differential data when a transmission error occurs. SOLUTION: At the time of occurrence of a transmission error, if a calculation error of CRC occurs, a sampling block is not output from a transmission control part 3 so that it is missing. Therefore, a D-type flip-flop DFF1-1 keeps current data held, the held current data is output from the DFF1-1 to a subsequent stage, and the same pulse as a previous one is output to an addition circuit. Therefore, even if input data to an encoder is temporarily stopped, a dangerous phenomenon such as jump or stop of the pulse with the DFF1-1 absent in conventional examples may be prevented, maintaining continuity. The number of output pulses at this time is compared with shift register data of a conversion part 4 when transmission is recovered to a normal state and converged to normal calculation, thereby causing no problem. This can be realized both in a DDA-scheme circuit and in a BRM-scheme circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a servo drive
The present invention relates to a circuit for converting data of a serial encoder that transmits data serially into a pulse train in a system.

[0002]

2. Description of the Related Art Regarding a pulse sequence conversion method of a serial encoder in a conventional servo drive system,
Japanese Patent Application Laid-Open No. 63-179213 discloses a data conversion circuit for converting absolute position data output from an absolute encoder into an incremental pulse train for use. FIG. 3 is a block diagram of the conventional data conversion circuit. In FIG. 3, when the rotation of the absolute encoder starts, absolute position data is input to the shift register 10, and this serial data is transmitted by the clock CL.
It is converted in parallel at every constant period T of K and input to the ALU (arithmetic logic circuit) 30. The reversible counter 20 counts up or down the input pulse signal. The ALU 30 receives the input from the shift register 10 and the output of the reversible counter 20, subtracts the latter count number from the former data, and outputs the result as differential data. The ALU 40 adds the data on the bus 7 and the output of the ALU 30, and the D-type flip-flop (DFF) 50 receives the output of the ALU 40 and outputs it on the bus 7 according to the internal clock signal CP. Decoder 60
Is the carry signal C generated in the ALU 40 and the ALU 30
The data MSB for positive / negative discrimination is input, and a pulse train + FB corresponding to the positive rotation direction of the encoder when MSB: 0, and a negative rotation of the encoder when MSB: 1 when MSB: 0. By outputting −FB and inputting the signals to terminals UP and DOWN of the reversible counter 20, respectively, the count value of the reversible counter 20 always follows the absolute position data output from the encoder. Therefore, the pulse trains + FB and -FB output from the decoder are used as a normal incremental feedback pulse signal converted from the absolute position data of the encoder, as a servo drive system,
It can be used in programmable controller systems.
The configuration of the circuit shown in FIG. 3 above is a known circuit called a DDA system (digital data interpolation circuit system), in which the difference data of the ALU 20 is transferred to the ALU 40 and the D-FF.
C and is integrated by an integrating circuit composed of
It is to convert to a pulse train by P. In addition, this DD
In addition to the A method, the integration circuit can be configured by a well-known BRM method (binary rate, multiplier). In this case, similarly, it can be realized by creating an up pulse and a down pulse with a configuration including a reversible counter, a bidirectional BRM circuit, a D-FF circuit, a demultiplexer, and the like.

[0003]

However, in the above-mentioned conventional example, pulse train conversion is performed based on the difference data. For example, as shown in the explanatory diagram of the sampling clock shown in FIG. S (NO
1, 2, 3, 4, 5,...) Are received in a unit time, the difference from the count value C of the counter, (S−C) is calculated, and the integral calculation is performed to generate an output pulse. Therefore, if a transmission error occurs, the encoder position information S-
As in NO4, since the input data is not input, the difference data becomes "0", the output is stopped, and then a double frequency pulse is output as indicated by the dotted line. Thus, when the conventional DDA method is simply implemented, the data sent from the serial encoder is H
When a CRC calculation error or the like in the DLC occurs,
In the worst case, the encoder data is not updated and the pulse stops, and there is a danger that the entire servo drive system will lose control. SUMMARY OF THE INVENTION It is an object of the present invention to provide a data conversion circuit in a servo drive system for converting data transmitted from a serial encoder into a pulse train, in which output pulses do not fluctuate even if a transmission error occurs.

[0004]

According to the first aspect of the present invention, there is provided a data conversion circuit for converting data of an encoder for transmitting data serially into a pulse train of a plurality of phases such as AB. When a transmission error occurs in the data conversion circuit that determines the difference between the data sent from the encoder and the pulse train and determines the pulse train per unit time by the DDA or BRM integrator, when the transmission error occurs, the encoder data is replaced with the previous difference data. Is provided as a current difference data. According to the second aspect of the present invention, the pulse train output means in the data conversion circuit specifically includes a DFF circuit that operates with a sampling clock output from a transmission control unit only when transmission data is normal. It is provided between the ALU that outputs the difference data and the integration circuit, and outputs the held previous pulse when the sampling clock is not output. With the above configuration, when a transmission error occurs, the same data as the previous data can be added, thereby preventing a change in the output pulse.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a data conversion circuit according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a sampling clock shown in FIG. In FIG. 1, reference numeral 1 denotes a D-type flip-flop (DFF) 1 used in the present invention, which is connected between the output side of the ALU 30 for difference data and the input side of the data addition ALU 40. The data of the serial encoder is input to the transmission control unit 3 of the HDLC system, and when the CRC operation result is normal, the read data is input to the serial / parallel conversion unit 4 with the shift clock to be converted into parallel data. The sampling clock based on
Send to FF1-1. The EXOR (exclusive OR) circuit 5 is a circuit for generating A-phase and B-phase pulses. The same reference numerals are given to the same circuits as the conventional circuit shown in FIG. That is, reference numeral 20 denotes a reversible counter which counts up or down the input pulse signal. Reference numeral 30 denotes an ALU (arithmetic logic circuit) which receives the input S from the serial / parallel converter 4 and the output C of the reversible counter 20, subtracts the latter count number from the former data, and uses it as difference data in the present invention. To the D-type flip-flop (DFF) 1 to be output. An ALU (arithmetic logic circuit) 40 adds the data on the bus 7 and the output of the D-type flip-flop 1 and outputs the result to a D-type flip-flop (DFF) 50. D-type flip-flop (DFF) 50 receives the output of ALU 40 and outputs it on bus 7 in accordance with internal clock signal CP. Decoder 60 carries carry signal C generated by ALU 40 and D
MSB for positive / negative discrimination from flip-flop 1
According to the internal clock CP, a pulse train + FB corresponding to the positive rotation direction of the encoder is output when MSB: 0, and -FB corresponding to a negative rotation of the encoder is output when MSB: 1. By inputting the signals to the terminals UP and DOWN of the reversible counter 20, the count value of the reversible counter 20 always follows the absolute position data output from the encoder. Therefore, the pulse trains + FB and -FB output from the decoder are used as a normal incremental feedback pulse signal converted from the absolute position data of the encoder, as a servo drive system,
It can be used in programmable controller systems.
Next, the operation will be described. HDLC for data transmission
The transmission control section 3 reads the data of the serial encoder and performs serial / parallel conversion section 4 using the shift clock.
When the CRC operation result is normal, the sampling clock is supplied to DFF1-
Send to 1. The sampling clock is not transmitted if there is an error in the CRC operation result. The count number C of the up / down counter 20 is subtracted by the ALU 30 from the serial data / parallel converted parallel data S. The subtracted difference data is input via the DFF 1-1 which is inputting a sampling clock shown on the scale of the horizontal T axis in FIG. 2 and which is latched at the falling edge of the clock and is operating normally.
The signal is input to the addition ALU 40 and added to the output of the DFF 2-50. The decoder 60 inputs the MSB and the carry, and outputs a pulse train. The up / down counter 20 counts an input pulse train, and outputs an A / B-phase two-phase pulse train that follows input data of the serial encoder by the EXOR circuit 5 based on the LSB of the counter 20 and the next bit. On the other hand, when a transmission error occurs, the sampling clock is transmitted to the transmission control unit 3 when a CRC calculation error occurs.
Is not output from the encoder, the encoder one-position information S in FIG.
As in the case of -N04, the data is lost, the DFF1-1 keeps the previous data, the previous data held is output from the DFF1-1 to the subsequent stage, and the same pulse as the previous one is added to the adder circuit. Therefore, even if the input data of the encoder is stopped at 1 o'clock, the danger phenomenon such as jumping and stopping of the pulse without the DFF 1-1 in the conventional example shown by the dotted line in FIG. Sex is maintained. In this case, the number of output pulses is compared with the data in the shift register of the conversion unit 4 when the transmission is restored to normal, and converges to a normal operation, so that there is no problem. In this embodiment, a circuit example of the DDA system has been described. However, it is needless to say that a circuit of the BRM system can be realized by a similar configuration.

[0006]

As described above, according to the present invention,
When a transmission error such as CRC occurs in the encoder data, the DFF circuit operated by the sampling clock output only when the transmission data is normal outputs the previous pulse to be held. Even if a transmission error occurs, there is no change in the output pulse.
A data conversion circuit that does not adversely affect the entire servo drive system can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data conversion circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a sampling clock shown in FIG.

FIG. 3 is a block diagram of a conventional data conversion circuit.

[Explanation of symbols]

 1, 50 D-type flip-flop (DFF) 2 inverter 3 transmission control unit 4 serial / parallel conversion unit 5 EXOR (exclusive OR) circuit 7 bus 10 shift register 20 reversible counter 30, 40 ALU (arithmetic logic circuit) 60 decoder

Claims (2)

[Claims] 1. A data conversion circuit for converting data of an encoder for transmitting data serially into a pulse train of a plurality of phases such as AB, wherein a difference between the data sent from the encoder and the pulse train is obtained by DDA or BRM integration means. In the data conversion circuit for obtaining a pulse train per unit time, when a transmission error occurs, the data of the encoder includes pulse train output means for calculating the previous difference data as the present difference data. Conversion circuit. 2. The data conversion circuit, wherein the pulse train output means operates a DFF circuit operated by a sampling clock output from a transmission control unit only when transmission data is normal, and outputs an AL signal that outputs differential data.
2. The data conversion circuit according to claim 1, wherein said data conversion circuit is provided between U and an integration circuit, and outputs the held previous pulse when the sampling clock is not output.