JP2006138822A - Encoder position detecting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an encoder position detecting circuit which is never influenced by offset and has a low manufacturing cost. <P>SOLUTION: This detecting circuit comprises an AD conversion part 2 including a chopper-type comparator which time-divides A-phase signal and B-phase signal outputted from an incremental encoder with 90°-phase difference to provide a voltage to be compared, and uses a voltage between resistance serially connected between a reference voltage VRT and a reference voltage VRB; an arithmetic part 3 correcting offset errors of the A-phase signal and the B-phase signal respectively based on data outputted from the AD conversion part 2, and then reversing the A-phase signal and the B-phase signal, thereby generating a reversed A-phase signal and a reversed B-phase signal, respectively, and generating a multiplication signal in which one period of the incremental encoder is multiplied in one cycle based on the A-phase signal, the reversed A-phase signal, the B-phase signal and the reversed B-phase signal; and a clock generator 1 supplying operation clocks to the AD converting means and the arithmetic means. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit incorporating an output signal processing circuit of an encoder used for angle and position detection, and more particularly to a general machine requiring position detection such as a motor.

A machine (such as a motor or a belt conveyance device) provided with a moving body (rotor, belt) needs to include an encoder for detecting the position of the moving body. An example of an encoder according to the prior art is an “encoder” disclosed in Patent Document 1.
An apparatus including an encoder generates a multiplied signal based on a 90-degree phase difference signal output from the encoder, and controls the moving source of the moving body based on the generated signal, thereby controlling the moving speed of the moving body to a desired speed. It becomes possible to control to.

FIG. 15 shows a conventional example of a circuit that generates a multiplied signal from a 90-degree phase difference signal.
For the A phase input (A signal) and the B phase input (B signal), an A-phase inverted signal AB and a B-phase inverted signal BB are generated by an inverting amplifier using an OP-AMP (operational amplifier). Further, AB and BB are further inverted to generate an A ′ signal (= A signal) and a B ′ signal (= B signal).
Next, the A ′ signal and the AB signal are input to the comparator, and AOUT0 that is a comparison result of A-AB is generated. Similarly, AOUT1 which is the comparison result of B-BB, AOUT2 which is the comparison result of A-BB, and AOUT3 which is the comparison result of AB-BB are respectively generated by the comparators.
Then, EXOUT0 is generated by taking the exclusive OR of AOUT0 and AOUT1, and EXOUT1 is generated by taking the exclusive OR of AOUT2 and AOUT3. Further, by taking exclusive OR between EXOUT0 and EXOUT1, a multiplied EXOUT signal is generated. The signal waveform of this circuit is shown in FIG.

  If this circuit is to be built in a semiconductor integrated circuit, the OP-AMP occupies a large area, which increases the chip size and increases the cost. Further, the effect of the offset of the OP-AMP and the comparator (mismatch between the positive threshold and the negative threshold) becomes a problem.

As a prior art for solving the problem of cost increase due to the use of OP-AMP, there is an “encoder device” disclosed in Patent Document 2.
The invention disclosed in Patent Document 2 reads a moving body in which an incremental phase signal having a constant constant pitch is recorded on a signal track and an origin phase signal indicating a predetermined position is recorded, and an incremental phase signal of the signal track. The first sensor for obtaining a plurality of output signals having phase differences, the second sensor for reading the origin phase signal, and the number of pulses m times (m ≧ 2) from the output signal of the first sensor And a multiplier circuit for outputting two incremental signals having a phase difference of 90 °, a signal for forming an incremental output signal of the multiplier circuit, and an origin phase signal obtained from the second sensor, It is an encoder device having period conversion means for converting to an origin signal having a pulse width less than 1.5 times the period.

  In the invention disclosed in Patent Document 2, as shown in FIGS. 19A and 19B, the OP-AMP in the configuration shown in FIG. 15 is not required by making the encoder output differential.

However, in the actual encoding output, offsets may occur individually in the A phase and the B phase. FIG. 17 shows a signal waveform of a portion where an offset occurs in the A phase and the B phase. FIG. 18 shows an enlarged signal waveform of the portion where the offset occurs. As shown in the figure, when there is an offset between the A phase and the B phase, the timing multiplied by one cycle is not accurate by comparing the A and B phases.
As a conventional technique for improving the influence of the offset, there is a “rotational position detector and rotational speed detection device” disclosed in Patent Document 3.
The invention disclosed in Patent Document 3 includes a position detector that performs position detection using a two-phase signal having orthogonality, and means for converting a two-phase analog signal output from the position detector into a digital signal And a means for performing arithmetic processing for adjusting the phase difference of each phase to 90 degrees by removing the offset error of each phase and making the amplitude of each phase of the two-phase digital signal the same Then, after making the amplitude of each phase of the position detector the same and removing the offset of each phase, the sum and difference of each phase signal are calculated, and the phase of each phase is calculated using the two generated signals. This is a rotational position detector provided with means for setting the phase difference to 90 degrees.
JP 11-325973 A Japanese Patent No. 2558287 JP 2001-296142 A

  As shown in FIGS. 20A and 20B, the invention disclosed in Patent Document 3 adopts a method of performing offset adjustment of the A phase and the B phase by digital arithmetic processing after AD conversion. For this reason, the circuit configuration requires two AD converters, and the chip size increases and the manufacturing cost increases.

  Thus, conventionally, an encoder position detection circuit that is not affected by an offset cannot be provided at a low manufacturing cost.

  The present invention has been made in view of such a problem, and an object thereof is to provide an encoder position detection circuit that is not affected by an offset and that is low in manufacturing cost.

  In order to achieve the above object, the present invention time-divides the A-phase signal and the B-phase signal output from the incremental encoder with a phase difference of 90 degrees into a comparison voltage, and compares the reference voltage VRT and the reference voltage VRB. A / D conversion means having a chopper comparator that uses a voltage between resistors connected in series between them as a comparison voltage, and offset errors of the A-phase signal and B-phase signal are corrected based on data output from the AD conversion means. Then, an inverted A phase signal obtained by inverting the A phase signal and an inverted B phase signal obtained by inverting the B phase signal are generated, and based on the A phase signal, the inverted A phase signal, the B phase signal, and the inverted B phase signal. And an arithmetic means for generating a multiplied signal obtained by multiplying one cycle of the incremental encoder in one cycle, an AD conversion means and a clock generator for supplying an operation clock to the arithmetic means. There is provided an encoder position detection circuit, wherein the door.

  In the present invention, by calculating the arithmetic average of the A phase signal and the A phase signal of the previous cycle or the B phase signal and the B phase signal of the previous cycle, the sampling time of the A phase signal and the B phase signal are calculated. It is preferable to virtually match the sampling time. Further, it is preferable that two or more resistors are connected in series between the reference voltage VRT and the reference voltage VRB.

  According to the present invention, it is possible to provide an encoder position detection circuit that is not affected by an offset and has a low manufacturing cost.

[First Embodiment]
A first embodiment in which the present invention is suitably implemented will be described. FIG. 1 shows a configuration of an encoder position detection circuit according to this embodiment. The encoder position detection circuit includes a clock generator (CLKGEN) 1, an AD conversion unit 2, and a calculation unit 3.
The clock generator 1 generates a clock signal and outputs it to the AD conversion unit 2 and the calculation unit 3. The AD converter 2 operates according to the clock signal input from the clock generator 1 and converts the analog signals input from AIN and BIN into digital signals. The calculation unit 3 performs a predetermined calculation process on the digital signal output from the AD conversion unit 3 and outputs the digital signal to the motor control unit 4 as a multiplied signal.

  A clock signal input from CLKIN to the clock generator 1 is a master clock. The A-phase signal and B-phase signal from the encoder are input to AIN and BIN, respectively. VRT and VRB are input terminals for the reference voltage of the AD converter 2.

FIG. 2 shows a configuration of the AD conversion unit 2. A plurality of resistance elements are connected in series between VRT and VRB, and a voltage at both ends of each resistance element is a comparison voltage. The voltage to be compared (voltage to be compared) is input from AIN or BIN by switching the switch according to the INSEL and INSELB signals input from the clock generator 1 and becomes an INA signal.
A circuit that compares the resistance-divided reference voltage and the INA signal is configured by a chopper comparator. The switch of the chopper type comparator is switched according to the INCK signal and the CPCK signal input from the clock generator 1. Each signal of HD0 to HD14, which is a comparison result in the chopper type comparator, is input to the encoding unit.

  FIG. 3 shows the configuration of the encoding unit. Each signal of HD0 to HD14 is inverted by an inverter and then latched at the rising timing of the CLK signal input from the clock generator 1. After latching, AND with the adjacent bit is performed by a 3-input AND circuit. Thus, an abnormal comparison result is not obtained due to the influence of noise or the like. Each signal of ENN0 to ENN14, which is the comparison result of the 3-input AND, is input to the encoding circuit.

  FIG. 4 shows the configuration of the encoding circuit. As shown in the figure, the encoding circuit is a circuit that converts a 15-bit input into 4 bits.

FIG. 5 shows the operation timing of the AD conversion unit 2.
AIN and BIN are A-phase and B-phase signal inputs. CLKIN is a master clock input. INSEL and INSELB are signals divided by two from CLKIN. INSEL and INSELB are non-overlapping signals in order to prevent collision of signals when switching. When INSEL = 1, the AIN input and INA are connected, and when INSELB = 1, BIN and INA are connected. INCK and CPCK are switch signals of the chopper type comparator, the period of INCK = 1 is the sampling period, and the period of CPCK = 1 is the comparison period with the reference voltage. HD0 to HD14 are output signals of the chopper type comparator. Since the input / output of the inverter is connected during the period of INCK = 1, the intermediate potential of the LSI is obtained, and the comparison result is output during the period of CPCK = 1. In FIG. 5, the period (1) is a sampling period of A-phase input. The period (2) is an A-phase comparative output period. The period (3) is a B-phase input sampling period. The period (4) is a B-phase comparative output period. HD [14: 0] is a signal in which HD0 to HD14 are represented by a bus (15 bits represented by HD14 as MSB and HD0 as LSB). HD_B [14: 0] is an inverted signal of HD [14: 0]. CLK is a clock input from the clock generator 1, and the HD_B signal is latched at the rising edge of this clock. ENIN [14: 0] is a 3-input AND output signal with adjacent bits, and is a signal input to the encoding circuit. ENOUT [3: 0] is an output signal from the encoding circuit.

  As shown in the figure, sampling is performed during the periods (1) and (2), and digital coding is performed after a half cycle of CLK.

  FIG. 6 shows the configuration of the calculation unit 3. The calculation unit 3 includes an average detection circuit 31, an inverting circuit 32, a correction processing circuit 33, and a multiplied signal output circuit 34.

  CLK is the same as that input to the AD converter 2 and is input from the clock generator 1. ENOUT [3: 0] is an output signal of the AD conversion unit 2. As shown in FIG. 10, ABSEL is a signal that indicates whether the ENOUT data is converted data of A phase or B phase for each cycle, and is generated in the clock generator 1.

  ADATA is a signal obtained by latching ENOUT at the rising edge of CLK when ASEL = 1, and is obtained by latching A-phase conversion data. BDATA is a signal obtained by latching ENOUT at the rising edge of CLK when ASEL = 0, and is obtained by latching B-phase conversion data.

  In BFAD and BFBD, data of one cycle before the A phase and the B phase are latched, respectively.

  The average detection circuit 31 is a circuit that detects a minimum value and a maximum value for each of the A phase and the B phase based on the ADATA, BDATA, BFAD, and BFBD signals, and calculates an average value from the minimum value and the maximum value. . The average detection circuit outputs AAVEREG as the average value of the A phase and BAVEREG as the average value of the B phase. The configuration of the average detection circuit 31 will be described in detail later.

The inversion circuit 32 inverts EOUT input from the A / D conversion unit 2 with AAVREG input from the average detection circuit 31 and outputs the result as XDATA.
The inversion processing circuit performs the following processing
assign XDATA = AAVEREG- (ENOUT-AAVEREG);

The correction processing circuit 33 is a circuit for correcting a shift between the A phase signal and the B phase signal, and performs the following processing.
assign ABDIFF = AAVEREG-BAVEREG;
assign BDATAX = ENOUT + ABDIFF
assign XBDATA = AAVEREG- (BDATAX-AAVEREG);

XADATA is a result of subtracting AAVEREG from ENOUT from AAVEREG, and is latched as ADATAB by a subsequent flip-flop (FF). BDATAX is the result of adding the difference between AAVEREG and BAVEREG to ENOUT, and is latched as BDATA2 by the subsequent FF. XBDATA is a calculation result obtained by inverting BDATAX with AAVEREG, and is latched as BDATAB in the subsequent FF.
By correcting the B phase data with the difference between AAVEREG and BAVEREG, the B phase data can be corrected to a signal centered on the average value of the A phase, as shown in FIG.

The multiplication signal output circuit 34 outputs a signal obtained by multiplying one cycle of the encoder, and performs the following processing.
assign AOUT0 = (ADATA> = ADATAB)? 1b'1: 1'B0;
assign AOUT1 = (BDATA> = BDATAB)? 1'b1: 1'B0;
assign AOUT2 = (ADATA> = BDATAB)? 1'b1: 1'B0;
assign AOUT3 = (ADATA> = BDATA2)? 1'b1: 1'B0:
assign EXOUT0 = AOUT0 ^ AOUT1;
assign EXOUT1 = AOUT2 ^ AOUT3;
assign EXOUT = EXOUT = EXOUT0 ^ EXOUT1;

  The multiplied signals AOUT and EXOUT are calculated by the logical expressions shown in FIG. 6 based on ADATA, ADATAB, BDATA2, and BDATAB.

  FIG. 7 shows the configuration of the average detection circuit 31. FIG. 8 shows the operation timing of the average detection circuit.

  The average detection circuit 31 includes an A-phase counter 311, a B-phase counter 312, an A-phase flag determination unit 313, a B-phase flag determination unit 314, an A-phase maximum value / minimum value sleeve grain 315, and a B-phase maximum value / minimum value extraction. A unit 316, a phase A maximum / minimum value selector 317, a phase B maximum / minimum value selector 318, and an average value output unit 319.

The A-phase counter 311 compares the A-phase input data with the buffered A-phase data, and determines whether or not a state in which the input data is larger than the buffered data continues for a predetermined cycle. .
The A phase counter 311 performs the following processing.
always @ (posedge CLK) begin
if (aict == 2'b11 | BFAD> ADATA) aint <= 2'b00;
else if (BFAD <ADATA) aict <= aint + 1;
else aict <= aict;
end
assign AUPFLG = (aict == 2'b10);
always @ (posedge CLK) begin
if (aict2 == 2'b11 | BFAD <ADATA) aict2 <= 2'b00;
else if (BFAD> ADATA) aict2 <= aict2 + 1;
else aict2 <= aict2;
end
assign ADOWNFLG = (aict2 == 2'b10);

The B-phase counter 312 compares the B-phase input data with the buffered B-phase data, and determines whether or not a state in which the input data is larger than the buffered data continues for a predetermined cycle. .
The B-phase counter 312 performs the following processing.
always @ (posedge CLK) begin
if (aict == 2'b11 | BFBD> BDATA) aint <= 2'b00;
else if (BFBD <BDATA) bict <= bint + 1;
else bict <= bict;
end
assign BUPFLG = (bict == 2'b10);
always @ (posedge CLK) begin
if (bict2 == 2'b11 | BFBD <BDATA) bict2 <= 2'b00;
else if (BFBD> BDATA) bict2 <= bict2 + 1;
else bict2 <= bict2;
end
assign BDOWNFLG = (bict2 == 2'b10);

AUPFLG is a signal that is turned on when ADATA is larger than BFAD, and ADOWNFLG is a signal that is turned on when ADATA is smaller than BFAD. BUPFLG is a signal that is turned on when BDATA is larger than BFBD, and BDOWNFLG is a signal that is turned on when BDATA is smaller than BFBD.
When ADATA (or BDATA) is larger (or smaller) than BFAD (or BFBD) for two consecutive cycles, it is determined that ADATA (or BDATA) is larger (or smaller) than BFAD (or BFBD). For example, even if ADATA exceeds BFAD for one cycle, AUPFLG does not turn ON if it falls below BFAD in the next cycle. By doing so, the same effect as when hysteresis is added to eliminate the influence of noise and the like can be obtained. Needless to say, the number of times can be arbitrarily changed.

A-phase flag determination unit 313 determines whether AUPFLG or ADOWNFLG is ON.
The A-phase flag determination unit 313 performs the following operation.
always @ (posedge CLK) begin
if (ADOWNFLG) AUPREG <= 1'b0;
else if (AUPREG == 1'b1) AUPREG <= 1'b1;
else AUPREG <= AUPREG;
end
always @ (posedge CLK) begin
if (AUPFLG) ADNREG <= 1'b0;
else if (ADOWNFLG = 1'b1) ADNREG <= 1b1;
else ADNREG <= ADNREG;
end

  AUPREG is a signal that is turned on when AUPFLG is turned on and turned off when ADOWNFLG is turned on. In contrast to AUPREG, ADNREG is a signal that is turned on when ADOWNFLG is turned on and turned off when AUPFLG is turned on.

The B phase flag determination unit 314 determines whether BUPFLG or BDOWNFLG is ON.
The B-phase flag determination unit 314 performs the following operation.
always @ (posedge CLK) begin
if (BDOWNFLG) BUPREG <= 1'b0;
else if (BUPREG == 1'b1) BUPREG <= 1'b1;
else BUPREG <= BUPREG;
end
always @ (posedge CLK) begin
if (BUPFLG) BDNREG <= 1'b0;
else if (BDOWNFLG = 1'b1) BDNREG <= 1b1;
else BDNREG <= BDNREG;
end

  BUPREG is a signal that is turned on when BUPFLG is turned on and turned off when BDOWNFLG is turned on. In contrast to BUPREG, BDNREG is a signal that is turned on when BDOWNFLG is turned on and turned off when BUPFLG is turned on.

The A-phase maximum / minimum value extraction unit 315 monitors changes in the A-phase signal and extracts maximum and minimum values. The A-phase signal maximum value / minimum value extraction unit 315 performs the following processing.
always @ (posedge CLK) begin
if (ADOWNFLG) AMAX <= 4'b0111;
else if (AMAX <= ADATA) AMAX <= ADATA;
else AMAX <= AMAX;
end
always @ (posedge CLK) begin
if (AUPFLG) AMIN <= 4'b0111;
else if (AMIN> = ADATA) AMIN <= ADATA;
else AMIN <= AMIN;
end

  AMAX is an intermediate value while ADNREG is ON (here, “7” because the arithmetic unit 3 has a 4-bit configuration), and ADATA is captured when ADATA is greater than AMAX while ADNREG is OFF. By this operation, the maximum value of ADATA is detected. On the other hand, AMIN is an intermediate value while AUPREG is ON, and ADATA is taken in if ADATA is smaller than AMIN while AUPREG is OFF. By this operation, the minimum value of ADATA is detected.

The B-phase maximum / minimum value extraction unit 316 monitors changes in the B-phase signal and extracts maximum and minimum values. The B-phase signal maximum value / minimum value extraction unit 316 performs the following processing.
always @ (posedge CLK) begin
if (BDOWNFLG) BMAX <= 4'b0111;
else if (BMAX <= BDATA) BMAX <= BDATA;
else BMAX <= BMAX;
end
always @ (posedge CLK) begin
if (BUPFLG) BMIN <= 4'b0111;
else if (BMIN> = BDATA) BMIN <= BDATA;
else BMIN <= BMIN;
end

  The output values of BMAX and BMIN are determined in the same manner as AMAX and AMIN, and the maximum value and the minimum value of BDATA are detected in the same manner as described above.

The A-phase maximum / minimum value selector 317 latches the maximum and minimum values of the A-phase signal at a predetermined timing. The A-phase maximum / minimum value selection unit 317 performs the following processing.
assign aulat = adownfig &! adwreg;
assign adnlat = aupflg &! aupreg;
always @ (posedge CLK) begin
if (auplat) AMAX2 <= AMAX;
else AMAX2 <= AMAX2;
end
always @ (posedge CLK) begin
if (adnlat) AMIN2 <= AMIN;
else AMIN <= AMIN2;
end
assign ALAT = auplat || adnlat;

AMAX2 is ADOWNNFLG &! Latched at the rising edge of CLK when the result of the logic expression of ADNREG is positive. ADOWNFLG &! A positive of the result of the logical expression of ADNREG is a signal that is turned ON in the first cycle when ADATA starts to decrease.
AMIN2 is AUPFLG &! Latched at the rising edge of CLK when the result of the AUPREG logical expression adnlat is positive. AUPFLG &! The positive result adnreg of AUPREG is a signal that is turned ON in the first cycle when ADATA begins to increase.

The B-phase maximum / minimum value selection unit 318 latches the maximum and minimum values of the B-phase signal at a predetermined timing. The B-phase maximum value / minimum value selection unit 318 performs the following processing.
assign bulat = bdownfig &! bdnreg;
assign bdnlat = bupflg &! bupreg;
always @ (posedge CLK) begin
if (buplat) BMAX2 <= BMAX;
else BMAX2 <= BMAX2;
end
always @ (posedge CLK) begin
if (bdnlat) BMIN2 <= BMIN;
else BMIN <= BMIN2;
end
assign BLAT = buplat || bdnlat;

BMAX2 is BDOWNNFLG &! Latched at the rising edge of CLK when the Bupreg logical expression result buplat is positive. BDOWNNFLG &! A positive bupreg as a result of the logical expression of BDNREG is a signal that is turned on in the first cycle when BDATA starts to decrease.
BMIN2 is BUPFLG &! Latched at the rising edge of CLK when bdnlat is positive as a result of the logical expression of BUPREG. BUPFLG &! The positive bdnlat as a result of the logical expression of BUPREG is a signal that is turned ON in the first cycle when BDATA starts to increase.

  ALAT is a logical sum signal of auplat and adnlat, and BLAT is a logical sum signal of buplat and bdnlat.

Average value output section 319 outputs the average value of the A-phase signal and the average value of the B-phase signal. The average value output unit 319 performs the following processing.
assign aave = (AMAX2-AMIN2) / 2 + AMIN2;
assign bave = (BMAX2-BMIN2) / 2 + BMIN2;
always @ (posedge CLKS) begin
if (ALAT) AAVEREG <= aave;
else AAVEREG <= AAVEREG;
end
always @ (posedge CLK) begin
if (BLAT) BAVEREG <= bave;
else BAVEREG <= BAVEREG <= BAVEREG;
end

  AAVEREG is latched at the rising edge of CLK when the average value of AMAX2 and AMIN2 is ALAT and ON. BAVEREG is latched at the rising edge of CLK when the average value of BMAX2 and BMIN2 is BLAT ON.

  By adopting such a circuit configuration, as shown in FIG. 9, AMAX2, AMIN2, and AAVEREG can follow the change of AIN.

  FIG. 11 shows the operation of the arithmetic circuit when there is an offset between the A phase and the B phase. Here, the case where the offset value is “2” is shown, but BDATA is added by the amount of the offset (ABDIFF) to become BDATA2, and the offset adjustment with the A phase is performed. Here, a method of correcting BDATA by AAVEREG is shown, but the same effect can be obtained by correcting ADATA by BAVEREG.

  FIG. 12 shows signal waveforms in a circuit configuration in which offset adjustment is not performed on BDATA2. In this case, the multiplication error of one cycle becomes larger than that in the case of performing offset adjustment (the waveform shown in FIG. 11).

  FIG. 13 shows a signal waveform when the output of the AD conversion unit 2 and the input of the calculation unit 3 are 5 bits. Compared to the case of 4 bits shown in FIG. 11, the multiplication error is further reduced. Thus, by increasing the output of the AD conversion unit 2 and the number of input bits of the calculation unit 3, the accuracy of multiplication can be increased.

  The encoder position detection circuit according to the present embodiment uses a chopper type comparator for A / D conversion, and performs A / D conversion of A-phase and B-phase signals in a time-sharing manner by one A / D conversion circuit. The chip size can be reduced. Thereby, manufacturing cost can be reduced. In addition, the multiplied signal can be output without being affected by the offset.

[Second Embodiment]
A second embodiment in which the present invention is suitably implemented will be described.
The configuration of the encoder position detection circuit is the same as that of the first embodiment. However, in this embodiment, the structure of the calculating part 3 is different from 1st Embodiment.

  FIG. 21 shows a configuration of the calculation unit 3 in the present embodiment. In the present embodiment, the calculation unit 3 includes an average detection circuit 31, an inverting circuit 32, a correction processing circuit 33 ', and a multiplied signal output circuit 34'.

  The average value detection circuit 31 and the inverting circuit 32 are the same as those of the calculation unit 3 of the first embodiment.

The correction processing circuit 33 ′ is a circuit for correcting a shift between the A phase signal and the B phase signal, and performs the following processing.
assign ABDIFF = AAVEREG-BAVEREG;
assign BDATAX = (ENOUT + BFBD) / 2 + ABDIFF
assign XBDATA = AAVEREG- (BDATAX-AAVEREG);

The multiplied signal output circuit 34 ′ is a circuit that outputs a signal obtained by multiplying one cycle of the encoder, and performs the following processing.
assign AOUT0 = (ADATA> = ADATAB)? 1b'1: 1'B0;
assign AOUT1 = (BDATA2> = BDATAB)? 1'b1: 1'B0;
assign AOUT2 = (BFAD> = BDATAB)? 1'b1: 1'B0;
assign AOUT3 = (BFAD> = BDATA2)? 1'b1: 1'B0:
assign EXOUT0 = AOUT0 ^ AOUT1;
assign EXOUT1 = AOUT2 ^ AOUT3;
assign EXOUT = EXOUT = EXOUT0 ^ EXOUT1;

In this embodiment, the calculating part 3 is set as the structure which correct | amends the time difference of A phase and B phase to the comparison data which produces | generates the signal for multiplication.
In the correction, the arithmetic average of the B phase data and the data one cycle before is taken, and the result is used as the B phase data for comparison. As for the A-phase data, BFAD, which is data one cycle before, is used as the A-phase data for comparison in order to synchronize with the B-phase data.

  The AD conversion in the AD conversion unit 2 is performed by time-sharing the A phase and the B phase. In this method, when the sampling clock is high for the A-phase and B-phase analog inputs, the influence of the sampling time difference between the A-phase and the B-phase is small, but the sampling clock is high-speed for the analog input. If not, it is necessary to consider the sampling time difference.

  In order to perform sampling simultaneously, a sampling hold amplifier may be provided for each of the A phase and the B phase. However, if this is provided, the manufacturing cost of the circuit increases.

  FIG. 22 shows signal waveforms of the encoder detection circuit according to the first embodiment when the sampling clock is not sufficiently large with respect to the analog input. In order to clarify the sampling errors of the A phase and the B phase, the same waveform is input to the A phase and the B phase, but the data does not match between ADATA and BDATA2.

  FIG. 23 shows a signal waveform picture of the encoder detection circuit according to the present embodiment when the sampling clock is not sufficiently large with respect to the analog input. As shown in the figure, in the present embodiment, the sampling time difference between the A phase and B phase data is corrected by performing the above calculation. 24A shows an analog input signal, FIG. 24B shows an output signal of the arithmetic unit 3 included in the encoder detection circuit according to this embodiment, and FIG. 24C shows an encoder detection according to the first embodiment. The output signal of the calculating part 3 with which a circuit is provided is shown. As shown in the drawing, in this embodiment, the error between the A phase and the B phase is reduced as compared with the first embodiment.

  The encoder position detection circuit according to the present embodiment uses a chopper type comparator for A / D conversion, and performs A / D conversion of A-phase and B-phase signals in a time-sharing manner by one A / D conversion circuit. The chip size can be reduced. Thereby, manufacturing cost can be reduced. In addition, the multiplied signal can be output without being affected by the offset.

  Further, the invention disclosed in Patent Document 3 has a problem that it cannot cope with a high-speed encoder output because it requires 12 steps for phase adjustment of the A phase and the B phase performed by digital arithmetic processing. Since the encoder detection apparatus according to the embodiment has a circuit configuration that corrects a sampling error due to time division of the A phase and the B phase, the influence of the error is small even if the frequency of the encoder is higher than the sampling clock. That is, it is possible to cope with a case where the encoder output is high speed.

  Each of the above embodiments is an example of a preferred embodiment of the present invention, and the present invention is not limited to these and can be variously modified.

It is a figure which shows the structure of the encoder position detection circuit concerning 1st Embodiment which implemented this invention suitably. It is a figure which shows the internal structure of an AD conversion part, and a connection state with a clock generator. It is a figure which shows the structure of an encoder circuit. It is a figure which shows the structure of an encoding circuit. It is a figure which shows the operation timing of an AD conversion part. It is a figure which shows the structure of a calculating part. It is a figure which shows the structure of an average detection circuit. It is a figure which shows the operation | movement timing of an average detection circuit. (A) is a figure showing the A phase signal input into an average detection circuit, (b) is a figure which shows the value converted inside an average detection circuit based on an A phase signal. It is a figure which shows the operation timing of a calculating part. It is a figure which shows the operation timing of a calculating part. It is a figure which shows the operation | movement timing of the calculating part when not performing offset correction to a B-phase signal. It is a figure which shows the operation | movement timing in case the calculating part is a structure which calculates 5 bits. (A) is a figure which shows the value converted inside an average detection circuit based on a B-phase signal, (b) is an A-phase signal, the average value of an A-phase signal, and the average value of a B-phase signal. It is a figure which shows a relationship. It is a figure which shows the structure of the encoder detection apparatus by a prior art. It is a figure which shows the signal waveform of the encoder detection apparatus by a prior art. It is a figure which shows the state which offset generate | occur | produced in the A phase signal and the B phase signal. It is a figure which shows the state which offset generate | occur | produced in the A phase signal and the B phase signal. It is a figure which shows the structure and operation | movement of the invention disclosed by patent document 2. FIG. It is a figure which shows the structure and operation | movement of the invention disclosed by patent document 3. FIG. It is a figure which shows the structure of the calculating part with which the encoder detection apparatus concerning 2nd Embodiment which implemented this invention suitably is provided. It is a figure which shows the operation | movement timing of the calculating part with which the encoder detection apparatus concerning 1st Embodiment is provided. It is a figure which shows the operation | movement timing of the calculating part with which the encoder detection apparatus concerning 2nd Embodiment is provided. (A) is a figure which shows an analog input signal, (b) is a figure which shows the output of the calculating part which concerns on 2nd Embodiment, (c) is the output of the calculating part concerning 1st Embodiment. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Clock generator 2 AD conversion part 3 Operation part 4 Motor control part 31 Average detection circuit 32 Inversion circuit 33, 33 'Correction processing circuit 34, 34' Multiplication signal output circuit 311 A phase counter 312 B phase counter 313 A phase flag determination part 314 B-phase flag determination unit 315 A-phase maximum / minimum value extraction unit 316 B-phase maximum / minimum value extraction unit 317 A-phase maximum / minimum value selection unit 318 B-phase maximum / minimum value selection unit 319 Average value output Part

Claims (3)

The A-phase signal and B-phase signal output with a phase difference of 90 degrees from the incremental encoder are time-divided to be compared voltages, and the voltage between resistors connected in series between the reference voltage VRT and the reference voltage VRB is AD conversion means including a chopper type comparator as a comparison voltage;
After correcting the offset error of the A phase signal and the B phase signal based on the data output from the AD conversion means, the inverted A phase signal and the B phase signal obtained by inverting the A phase signal are inverted. The inverted B phase signal is generated, and a multiplied signal obtained by multiplying one cycle of the incremental encoder based on the A phase signal, the inverted A phase signal, the B phase signal, and the inverted B phase signal is generated in one cycle. A computing means to generate;
An encoder position detection circuit comprising: a clock generator for supplying an operation clock to the AD conversion means and the calculation means.   By calculating an arithmetic average of the A phase signal and the A phase signal one cycle before or the B phase signal and the B phase signal one cycle before, the sampling time of the A phase signal and the sampling of the B phase signal are calculated. 2. The encoder position detection circuit according to claim 1, wherein time is virtually matched.   3. The encoder position detection circuit according to claim 1, wherein two or more resistors are connected in series between the reference voltage VRT and the reference voltage VRB.

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