CN112187257A - High-speed low-jitter data synchronous phase discriminator - Google Patents
High-speed low-jitter data synchronous phase discriminator Download PDFInfo
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- H—ELECTRICITY
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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Abstract
The invention discloses a high-speed low-jitter data synchronous phase discriminator, which comprises a data latch circuit, a data clock comparison circuit, a data correction circuit and a decision circuit, wherein the data latch circuit is connected with the data clock comparison circuit; the data latch circuit is used for receiving an externally input high-speed data stream and latching the data stream when the rising edge of the next clock period comes; the data clock comparison circuit compares the time sequence of the data stream with the input reference clock; the data correction circuit corrects the data signal latched by the front end and the received clock signal to ensure that each data is temporarily aligned with the input clock at the next clock; the decision circuit is used for determining the lead-lag relationship of data and a clock; the invention has the advantages of small jitter of recovered clock, large tuning range, low power consumption, simple structure and the like.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a high-speed low-jitter data synchronous phase discriminator.
Background
In order to reduce the bit error rate and improve the jitter tolerance of the clock data recovery circuit, the data receiving speed and precision of the phase detector are required to be improved as much as possible, and clock and data jitter generated by the structure of the phase detector is reduced. The current phase detector usually only has two processes of data acquisition and clock comparison, and only the inherent jitter factor existing in the transmission data is considered during data acquisition. Meanwhile, the defects of low synchronization precision of data and clock and the like exist. In order to reduce the bit error rate and improve the jitter tolerance of the clock data recovery circuit, the data synchronization time of the phase detector needs to be reduced. Meanwhile, jitter is a very important index of the circuit, and a low-jitter phase detector should be designed to reduce jitter between an input clock and data.
Disclosure of Invention
The invention aims to: aiming at the defects, the invention provides a high-speed low-jitter data synchronous phase discriminator.
In order to achieve the purpose, the invention provides the following technical scheme:
a high-speed low-jitter data synchronous phase discriminator comprises a data latch circuit, a data clock comparison circuit, a data correction circuit and a decision circuit; the data latch circuit is respectively connected with the data clock comparison circuit, the data correction circuit and the decision circuit, the data clock comparison circuit is connected with the data correction circuit, and the data correction circuit is connected with the decision circuit;
the data latch circuit includes: a buffer BUF1, a buffer BUF2, a buffer BUF3, a flip-flop DFF1, a flip-flop DFF2, a flip-flop DFF3, a DATA terminal, a CLK1 terminal, and a CLK2 terminal; the CLK2 end is connected to the input end of the DATA correction circuit and the input end of the decision circuit respectively, Q ends of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3 are connected to the input end of the DATA clock comparison circuit and the input end of the DATA correction circuit respectively, D ends of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3 are correspondingly connected to the output ends of the buffer BUF1, the buffer BUF2 and the buffer BUF3 respectively, the CLK1 end is connected to the clock input ends of the flip-flop DFF1 and the flip-flop DFF2 respectively, the CLK2 end is connected to the clock input end of the flip-flop DFF3, and the DATA end is connected to the input ends of the buffer BUF1, the buffer BUF2 and the buffer BUF3 respectively.
Removing burrs and micro jitter possibly existing in input data through a buffer; and the input data is latched by a trigger according to the added orthogonal input reference clock, so that a short data latching task is completed.
Further, the data clock comparison circuit comprises a three-input AND gate AND; the output end of the three-input AND gate AND is connected with the input end of the data correction circuit; AND three input ends of the three-input AND gate AND are respectively AND correspondingly connected with the Q ends of the trigger DFF1, the trigger DFF2 AND the trigger DFF 3.
The time sequence comparison AND unification of the clocks with different data are realized by adopting a three-input AND gate AND.
Further, the data correction circuit comprises a decision register; the ENABLE input end REG _ ENABLE of the decision register is connected with the output end of the DATA clock comparison circuit, the DATA output end DATA _ IN1, the DATA output end DATA _ IN2 and the DATA output end DATA _ IN3 of the decision register are respectively connected with the input end of the decision circuit, the clock input end of the decision register is connected with the DATA latch circuit, the DATA input end DATA1, the DATA input end DATA2 and the DATA input end DATA3 of the decision register are respectively correspondingly connected with the Q ends of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3, and the clock output end of the decision register outputs a RE _ TIMING signal.
The data signal latched at the front end and the received clock signal are corrected through the data correcting circuit, and data can be collected at the rising edge of the input clock, so that an optimal sampling interval is formed, clock jitter is reduced, and the accuracy of recovered data is improved.
Furthermore, the judgment register is a first-in first-out memory with a data selection end; the decision register is utilized to realize the continuous storage task of the data with larger bit width, thereby reducing the clock jitter and improving the precision of the recovered data.
Further, the decision circuit comprises a flip-flop DFF4, a flip-flop DFF5, a flip-flop DFF6, and an exclusive or gate XOR1 and an exclusive or gate XOR 2; clock input ends of the flip-flop DFF4, the flip-flop DFF5 and the flip-flop DFF6 are connected with a data latch circuit, D ends of the flip-flop DFF4, the flip-flop DFF5 and the flip-flop DFF6 are correspondingly connected with an output end of the data correction circuit respectively, a Q end of the flip-flop DFF4 is connected with an XOR gate XOR1, a Q end of the flip-flop DFF5 is connected with an XOR gate 1 and an XOR gate XOR2 respectively, and a Q end of the flip-flop DFF6 is connected with the XOR gate 2; the exclusive or gate XOR1 and the exclusive or gate XOR2 are used to output the EARLY signal EARLY or the LATE signal LATE.
By latching data into the flip-flop for discrimination, the phase error of the data and clock accumulated in the circuit is reduced to the lowest level, so that the timing sequence of the data is greatly improved.
The invention has the beneficial effects that: the high-speed low-jitter data synchronous phase discriminator provided by the invention contains six data triggers, can simultaneously receive a group of orthogonal clocks, controls the data flow rate by clock signals, has the advantages of small clock jitter recovery, large tuning range, low power consumption, simple structure and the like compared with the traditional phase discriminator, and can be widely applied to integrated circuit design.
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Fig. 1 is an overall circuit diagram of a high-speed low-jitter data synchronous phase discriminator according to the present invention;
fig. 2 is a data transmission waveform diagram of a high-speed low-jitter data synchronous phase discriminator according to the present invention;
FIG. 3 is a schematic diagram of an optimal sampling point of the high-speed low-jitter data synchronous phase discriminator according to the present invention;
fig. 4 is a schematic diagram of adjusting the data timing of the high-speed low-jitter data synchronization phase discriminator according to the present invention.
Detailed Description
As shown in fig. 1, a high-speed low-jitter data synchronous phase discriminator includes a data latch circuit, a data clock comparison circuit, a data correction circuit, and a decision circuit; the data latch circuit is connected with the data clock comparison circuit, the data correction circuit and the decision circuit, the data clock comparison circuit is connected with the data correction circuit, and the data correction circuit is connected with the decision circuit.
The data latch circuit includes: a buffer BUF1, a buffer BUF2, a buffer BUF3, a flip-flop DFF1, a flip-flop DFF2, a flip-flop DFF3, a DATA terminal, a CLK1 terminal, and a CLK2 terminal; when a clock signal in CLK1 and CLK2 is high level, the DATA end sends the DATA DATA into buffers BUF1, BUF2 and BUF3, and buffers BUF1, BUF2 and BUF3 to transmit the DATA DATA into D ends of flip-flops DFF1, DFF2 and DFF3 which are correspondingly connected, at this time, two groups of orthogonal input reference clocks CLK1 and CLK2 are added through CLK1 ends and CLK2 ends to respectively lock the DATA DATA in different flip-flops, and when the rising edge of the next clock arrives, the Q ends of the flip-flops DFF1, DFF2 and DFF3 correspond to output DATA DATA1, DATA2 and DATA3 to the DATA clock comparison circuit input end, thereby completing the transient DATA latching task.
Removing burrs and micro jitter possibly existing in input data through a buffer; and the input data is latched by a trigger according to the added orthogonal input reference clock, so that a short data latching task is completed.
The data clock comparison circuit comprises a three-input AND gate AND; the DATA DATA1, the DATA DATA2 AND the DATA DATA3 which are correspondingly output by the Q ends of the flip-flop DFF1, the flip-flop DFF2 AND the flip-flop DFF3 enter a three-input AND gate AND through three input ends of the three-input AND gate AND, AND when the output DATA DATA1, the DATA DATA2 AND the DATA DATA3 all reach the output end of the three-input AND gate AND, the output end of the three-input AND gate AND outputs the REG _ ENABLE signal to the input end of the DATA correction circuit.
The time sequence comparison AND unification of the clocks with different data are realized by adopting a three-input AND gate AND.
The data correction circuit comprises a decision register; when the REG _ ENABLE signal output by the output end of the three-input AND gate AND is received by the input ENABLE end REG _ ENABLE of the judgment register, the DATA DATA1, the DATA DATA2 AND the DATA DATA3 which are correspondingly output by the Q end of the flip-flop DFF1, the Q end of the flip-flop DFF2 AND the Q end of the flip-flop DFF3 are all stored in the judgment register; when the rising edge of the next clock of the input reference clock CLK2 arrives, the latched three paths of DATA are uniformly output to the decision circuit through the DATA output end DATA _ IN1, the DATA output end DATA _ IN2 and the DATA output end DATA _ IN3 of the decision register; the clock output terminal of the decision register outputs the RE _ TIMING signal. The decision register is a first-in first-out memory with a data selection end; the decision register is utilized to realize the continuous storage task of the data with larger bit width, thereby reducing the clock jitter and improving the precision of the recovered data.
The data signal latched at the front end and the received clock signal are corrected through the data correcting circuit, and data can be collected at the rising edge of the input clock, so that an optimal sampling interval is formed, clock jitter is reduced, and the accuracy of recovered data is improved.
The decision circuit comprises a trigger DFF4, a trigger DFF5, a trigger DFF6, an exclusive OR gate XOR1 and an exclusive OR gate XOR 2; the DATA _ IN1, DATA _ IN2, and DATA _ IN3 outputted from the decision register flow into the decision circuit corresponding to the D terminal of the flip-flop DFF4, the D terminal of the flip-flop DFF5, and the D terminal of the flip-flop DFF 6; when the rising edge of the next clock of the input reference clock CLK2 comes, three paths of DATA are uniformly latched into the flip-flop DFF4, the flip-flop DFF5 and the flip-flop DFF6, then, after a clock cycle passes, the DATA _ IN1 is latched by the flip-flop DFF4, the DATA _ OUT1 is output to the exclusive or gate XOR1 through the Q terminal of the flip-flop DFF4, the DATA _ IN2 is latched by the flip-flop DFF5, the DATA _ OUT2 is output to the exclusive or gate XOR1 and XOR2 through the Q terminal of the flip-flop DFF5, and the DATA _ IN3 is latched by the flip-flop DFF6, and then the DATA OUT _ 3 is output to the exclusive or gate XOR2 through the Q terminal of the flip-flop DFF 6; the outputs of the XOR gates XOR1 and XOR2 are both the outputs of the decision circuit and the outputs of the entire data synchronization phase detector. By determining the lead-lag relationship after the three sets of data have passed through the same input reference clock CLK2, the corresponding lead signal EARLY or lag signal LATE is generated.
The phase errors of data and clock accumulated in the circuit are reduced to the lowest level through the decision circuit, and the data timing is greatly improved.
While the invention has been described in terms of its preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Claims (5)
1. A high-speed low-jitter data synchronous phase discriminator is characterized by comprising a data latch circuit, a data clock comparison circuit, a data correction circuit and a decision circuit; the data latch circuit is respectively connected with the data clock comparison circuit, the data correction circuit and the decision circuit, the data clock comparison circuit is connected with the data correction circuit, and the data correction circuit is connected with the decision circuit;
the data latch circuit includes: a buffer BUF1, a buffer BUF2, a buffer BUF3, a flip-flop DFF1, a flip-flop DFF2, a flip-flop DFF3, a DATA terminal, a CLK1 terminal, and a CLK2 terminal; the CLK2 end is connected to the input end of the DATA correction circuit and the input end of the decision circuit respectively, Q ends of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3 are connected to the input end of the DATA clock comparison circuit and the input end of the DATA correction circuit respectively, D ends of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3 are correspondingly connected to the output ends of the buffer BUF1, the buffer BUF2 and the buffer BUF3 respectively, the CLK1 end is connected to the clock input ends of the flip-flop DFF1 and the flip-flop DFF2 respectively, the CLK2 end is connected to the clock input end of the flip-flop DFF3, and the DATA end is connected to the input ends of the buffer BUF1, the buffer BUF2 and the buffer BUF3 respectively.
2. The high-speed low-jitter data synchronous phase detector according to claim 1, wherein said data clock comparison circuit comprises a three-input AND gate AND; the output end of the three-input AND gate AND is connected with the input end of the data correction circuit, AND the three input ends of the three-input AND gate AND are respectively AND correspondingly connected with the Q ends of the trigger DFF1, the trigger DFF2 AND the trigger DFF 3.
3. A high-speed low-jitter data synchronous phase detector as claimed in claim 1, wherein said data correction circuit includes a decision register; the ENABLE input end REG _ ENABLE of the decision register is connected with the output end of the DATA clock comparison circuit, the DATA output end DATA _ IN1, the DATA output end DATA _ IN2 and the DATA output end DATA _ IN3 of the decision register are respectively connected with the input end of the decision circuit, the clock input end of the decision register is connected with the DATA latch circuit, the DATA input end DATA1, the DATA input end DATA2 and the DATA input end DATA3 of the decision register are respectively correspondingly connected with the Q ends of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3, and the clock output end of the decision register outputs a RE _ TIMING signal.
4. A high-speed low-jitter data synchronization phase detector as claimed in claim 3, wherein said decision register is a first-in-first-out memory with data select terminal.
5. The high-speed low-jitter data synchronization phase detector of claim 1, wherein said decision circuit comprises flip-flop DFF4, flip-flop DFF5, flip-flop DFF6, and XOR gate XOR1 and XOR gate XOR 2; clock input ends of the flip-flop DFF4, the flip-flop DFF5 and the flip-flop DFF6 are connected with a data latch circuit, D ends of the flip-flop DFF4, the flip-flop DFF5 and the flip-flop DFF6 are correspondingly connected with an output end of the data correction circuit respectively, a Q end of the flip-flop DFF4 is connected with an exclusive-OR gate XOR1, a Q end of the flip-flop DFF5 is connected with an exclusive-OR gate XOR1 and an exclusive-OR gate XOR2 respectively, and a Q end of the flip-flop DFF6 is connected with an exclusive-OR gate XOR 2.
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